TWI419224B - 提供特徵結構於蝕刻層上的方法和裝置 - Google Patents

提供特徵結構於蝕刻層上的方法和裝置 Download PDF

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TWI419224B
TWI419224B TW096116156A TW96116156A TWI419224B TW I419224 B TWI419224 B TW I419224B TW 096116156 A TW096116156 A TW 096116156A TW 96116156 A TW96116156 A TW 96116156A TW I419224 B TWI419224 B TW I419224B
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layer
forming
sacrificial
etch
sidewall
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TW200746296A (en
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Zhisong Huang
Jeffrey Marks
S M Reza Sadjadi
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Lam Res Corp
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
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    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

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  • Drying Of Semiconductors (AREA)

Claims (20)

  1. 一種用來形成特徵結構於蝕刻層上的方法，其包含：形成一具有犧牲特徵結構的犧牲圖案層於一蝕刻層上；形成保形側壁於犧牲特徵結構中，其包含一側壁形成處理的至少兩個循環，其中每一循環都包含：一側壁沉積階段；及一側壁輪廓形塑階段，其將該側壁的輪廓形塑成垂直的輪廓；選擇性地去除掉該犧牲圖案層之介於保形側壁之間的部分，留下具有間隙的保形側壁，間隙係介於保形側壁之犧牲圖案層被選擇性地去除掉的部分之間；及使用保形側壁作為一蝕刻罩幕來將特徵結構蝕刻於蝕刻層上，其中在蝕刻層上的特徵結構係透過介於保形側壁之間的間隙而被蝕刻的，該間隙為犧牲圖案層被選擇性地去除掉的部分。
  2. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中該側壁沉積階段包含：提供一沉積氣體；由該沉積氣體形成一電漿；及停止該沉積氣體流。
  3. 如申請專利範圍第2項之形成特徵結構於蝕刻層上的方法，其中該側壁輪廓形塑階段包含： 提供一不同於該沉積氣體之輪廓形塑氣體；由該輪廓形塑氣體形成一電漿；及停止該輪廓形塑氣體流。
  4. 如申請專利範圍第3項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層包含：形成一犧牲層於該蝕刻層上；形成一圖案罩幕於該犧牲層上；及將犧牲特徵結構蝕刻至該犧牲層中。
  5. 如申請專利範圍第4項之形成特徵結構於蝕刻層上的方法，其中該圖案罩幕為一光阻罩幕，及其中形成該犧牲圖案層更包含修剪(trimming)該光阻罩幕。
  6. 如申請專利範圍第5項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層更包含在將該犧牲特徵結構蝕刻到該犧牲層中之後去除掉該光阻罩幕。
  7. 如申請專利範圍第6項之形成特徵結構於蝕刻層上的方法，其中該犧牲圖案層界定一陣列區及一邏輯區，更包含在形成該犧牲圖案層之後覆蓋該犧牲圖案層的邏輯區，其中選擇性地去除該犧牲圖案層的一部分係去除掉該犧牲圖案層之未被覆蓋的部分。
  8. 如申請專利範圍第7項之形成特徵結構於蝕刻層上的方法，其更包含在選擇性地去除該犧牲圖案層的一部分之後去除該犧牲圖案層的邏輯區的覆蓋。
  9. 如申請專利範圍第8項之形成特徵結構於蝕刻層上的方法，其更包含去除掉側壁及去除掉該犧牲圖案層 之剩下來的部分。
  10. 如申請專利範圍第9項之形成特徵結構於蝕刻層上的方法，其中側壁是被沉積的矽。
  11. 如申請專利範圍第10項之形成特徵結構於蝕刻層上的方法，其中側壁具有實質垂直的斜度。
  12. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層包含：形成一光阻層於該蝕刻層上；將該光阻層圖案化以形成一圖案光阻罩幕，其中該圖案光阻罩幕為該犧牲圖案層及其中保形側壁被形成在該光阻罩幕上。
  13. 如申請專利範圍第3項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層包含：形成一第一犧牲層，一第二犧牲層及蝕刻停止堆疊(stack)，其包含：將該第二犧牲層形成在該蝕刻層上；形成一蝕刻停止層於該第二犧牲層上；及將該第一犧牲層形成在該蝕刻停止層上；形成一圖案罩幕於該第一犧牲層上；將犧牲特徵結構蝕刻到該第一犧牲層中；形成保形側壁形成於該第一犧牲層的犧牲特徵結構中；選擇性地去除掉該第一犧牲層介於保形側壁之間的部分，留下具有間隙的保形側壁，間隙係介於保形側壁 之第一犧牲層被去除掉的部分之間；將特徵結構蝕刻至該第二犧牲層中用以形成該犧牲圖案層；及去除掉保形側壁。
  14. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層包含：形形成一光阻罩幕於該犧牲層上；及修剪該光阻罩幕；其中該光阻罩幕是該犧牲層，及其中保形側壁被形成在該光阻罩幕上。
  15. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中該犧牲圖案層界定一陣列區及一邏輯區，更包含：在形成該犧牲圖案層之後覆蓋該犧牲圖案層的邏輯區，其中選擇性地去除該犧牲圖案層的一部分係去除掉該犧牲圖案層之未被覆蓋的部分；及在選擇性地去除掉一部分的犧牲圖案層之後，揭除該犧牲圖案層的邏輯區的覆蓋。
  16. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中形成保形側壁並不形成沿著水平表面的沉積。
  17. 如申請專利範圍第11項之形成特徵結構於蝕刻層上的方法，其中該等保形壁從下到上形成一相對於該犧牲層特徵結構的底部介於88°至90°的角度。
  18. 如申請專利範圍第1項之形成特徵結構於蝕刻層上的方法，其中該等保形側壁係在低於100℃的溫度下形成。
  19. 一種用來形成特徵結構於蝕刻層上的方法，其包含：形成具有犧牲特徵結構的犧牲圖案層於一蝕刻層上，其中該犧牲圖案層界定一陣列區及一邏輯區，此步驟包含：提供一光阻層；及用該光阻層形成一光阻罩幕，其中該犧牲圖案層是該光阻罩幕；覆蓋該犧牲圖案層的邏輯區，其中該犧牲圖案層之界定該陣列區的部分被揭露；形成保形側壁於該犧牲特徵結構中，其中該等側壁是在該光阻罩幕上，此步驟包含一側壁形成處理的至少兩個循環，其中每一循環都包含：一側壁沉積階段，其包含：提供一沉積氣體；由該沉積氣體形成一電漿；及停止該沉積氣體流；及一側壁輪廓形塑階段，其將測壁的輪廓形塑成垂直的輪廓，此步驟包含：提供一不同於該沉積氣體之輪廓形塑氣體；由該輪廓形塑氣體形成一電漿；及 停止該輪廓形塑氣體流；及選擇性地去除掉該犧牲圖案層之介於保形側壁之間未被覆蓋的部分，留下具有間隙的保形側壁，間隙係介於保形側壁之犧牲圖案層被選擇性地去除掉的部分之間；揭露該犧牲圖案層之邏輯區；及使用保形側壁作為一蝕刻罩幕來將特徵結構蝕刻於蝕刻層上，其中在蝕刻層上的該特徵結構係透過介於保形側壁之間的間隙而被蝕刻的，該間隙為該犧牲圖案層被選擇性地去除掉的部分。
  20. 如申請專利範圍第19項之形成特徵結構於蝕刻層上的方法，其中形成該犧牲圖案層更包含：修剪該光阻罩幕。
TW096116156A 2006-05-10 2007-05-07 提供特徵結構於蝕刻層上的方法和裝置 TWI419224B (zh)

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WO2007133442A1 (en) 2007-11-22
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KR20090009312A (ko) 2009-01-22
US20070264830A1 (en) 2007-11-15
CN101496141A (zh) 2009-07-29
TW200746296A (en) 2007-12-16
US7429533B2 (en) 2008-09-30
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