TWI419224B - 提供特徵結構於蝕刻層上的方法和裝置 - Google Patents

提供特徵結構於蝕刻層上的方法和裝置 Download PDF

Info

Publication number
TWI419224B
TWI419224B TW096116156A TW96116156A TWI419224B TW I419224 B TWI419224 B TW I419224B TW 096116156 A TW096116156 A TW 096116156A TW 96116156 A TW96116156 A TW 96116156A TW I419224 B TWI419224 B TW I419224B
Authority
TW
Taiwan
Prior art keywords
layer
forming
sacrificial
etch
sidewall
Prior art date
Application number
TW096116156A
Other languages
English (en)
Chinese (zh)
Other versions
TW200746296A (en
Inventor
Zhisong Huang
Jeffrey Marks
S M Reza Sadjadi
Original Assignee
Lam Res Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Lam Res Corp filed Critical Lam Res Corp
Publication of TW200746296A publication Critical patent/TW200746296A/zh
Application granted granted Critical
Publication of TWI419224B publication Critical patent/TWI419224B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0337—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H01L21/0334—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/0338—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3088—Process specially adapted to improve the resolution of the mask
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3105—After-treatment
    • H01L21/311—Etching the insulating layers by chemical or physical means
    • H01L21/31144—Etching the insulating layers by chemical or physical means using masks
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/3213—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer
    • H01L21/32139—Physical or chemical etching of the layers, e.g. to produce a patterned layer from a pre-deposited extensive layer using masks

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Chemical & Material Sciences (AREA)
  • Inorganic Chemistry (AREA)
  • Drying Of Semiconductors (AREA)
TW096116156A 2006-05-10 2007-05-07 提供特徵結構於蝕刻層上的方法和裝置 TWI419224B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/432,194 US7429533B2 (en) 2006-05-10 2006-05-10 Pitch reduction

Publications (2)

Publication Number Publication Date
TW200746296A TW200746296A (en) 2007-12-16
TWI419224B true TWI419224B (zh) 2013-12-11

Family

ID=38596323

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096116156A TWI419224B (zh) 2006-05-10 2007-05-07 提供特徵結構於蝕刻層上的方法和裝置

Country Status (7)

Country Link
US (1) US7429533B2 (ja)
EP (1) EP2018661A1 (ja)
JP (1) JP5048055B2 (ja)
KR (1) KR101353239B1 (ja)
CN (1) CN101496141B (ja)
TW (1) TWI419224B (ja)
WO (1) WO2007133442A1 (ja)

Families Citing this family (51)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7271106B2 (en) * 2004-08-31 2007-09-18 Micron Technology, Inc. Critical dimension control for integrated circuits
US7695632B2 (en) * 2005-05-31 2010-04-13 Lam Research Corporation Critical dimension reduction and roughness control
US7682516B2 (en) * 2005-10-05 2010-03-23 Lam Research Corporation Vertical profile fixing
US7488685B2 (en) * 2006-04-25 2009-02-10 Micron Technology, Inc. Process for improving critical dimension uniformity of integrated circuit arrays
US8852851B2 (en) 2006-07-10 2014-10-07 Micron Technology, Inc. Pitch reduction technology using alternating spacer depositions during the formation of a semiconductor device and systems including same
KR20080012055A (ko) * 2006-08-02 2008-02-11 주식회사 하이닉스반도체 마스크 패턴 형성 방법
US7914974B2 (en) * 2006-08-18 2011-03-29 Brewer Science Inc. Anti-reflective imaging layer for multiple patterning process
US20080152823A1 (en) * 2006-12-20 2008-06-26 Lam Research Corporation Self-limiting plating method
US7794530B2 (en) * 2006-12-22 2010-09-14 Lam Research Corporation Electroless deposition of cobalt alloys
US7521358B2 (en) * 2006-12-26 2009-04-21 Lam Research Corporation Process integration scheme to lower overall dielectric constant in BEoL interconnect structures
US8980756B2 (en) 2007-07-30 2015-03-17 Micron Technology, Inc. Methods for device fabrication using pitch reduction
KR101573954B1 (ko) * 2007-12-21 2015-12-02 램 리써치 코포레이션 포토레지스트 더블 패터닝
WO2009085564A2 (en) * 2007-12-21 2009-07-09 Lam Research Corporation Etch with high etch rate resist mask
CN101903978B (zh) * 2007-12-21 2014-11-19 朗姆研究公司 用于注入光刻胶的保护层
KR101647158B1 (ko) 2008-01-29 2016-08-09 브레우어 사이언스 인코포레이션 다중 다크 필드 노출에 의한, 하드마스크 패턴화를 위한 온-트랙 공정
US7989307B2 (en) 2008-05-05 2011-08-02 Micron Technology, Inc. Methods of forming isolated active areas, trenches, and conductive lines in semiconductor structures and semiconductor structures including the same
US10151981B2 (en) * 2008-05-22 2018-12-11 Micron Technology, Inc. Methods of forming structures supported by semiconductor substrates
JP5224919B2 (ja) * 2008-06-10 2013-07-03 株式会社東芝 半導体装置の製造方法
WO2009150870A1 (ja) * 2008-06-13 2009-12-17 東京エレクトロン株式会社 半導体装置の製造方法
US8409457B2 (en) * 2008-08-29 2013-04-02 Micron Technology, Inc. Methods of forming a photoresist-comprising pattern on a substrate
JP2010087298A (ja) * 2008-09-30 2010-04-15 Toshiba Corp 半導体装置の製造方法
KR101045090B1 (ko) 2008-11-13 2011-06-29 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US8273634B2 (en) 2008-12-04 2012-09-25 Micron Technology, Inc. Methods of fabricating substrates
US8247302B2 (en) 2008-12-04 2012-08-21 Micron Technology, Inc. Methods of fabricating substrates
US8796155B2 (en) 2008-12-04 2014-08-05 Micron Technology, Inc. Methods of fabricating substrates
US9640396B2 (en) * 2009-01-07 2017-05-02 Brewer Science Inc. Spin-on spacer materials for double- and triple-patterning lithography
US8138092B2 (en) 2009-01-09 2012-03-20 Lam Research Corporation Spacer formation for array double patterning
US8268543B2 (en) 2009-03-23 2012-09-18 Micron Technology, Inc. Methods of forming patterns on substrates
US9330934B2 (en) 2009-05-18 2016-05-03 Micron Technology, Inc. Methods of forming patterns on substrates
KR20110064661A (ko) * 2009-12-08 2011-06-15 삼성전자주식회사 반도체소자의 제조방법
US8222140B2 (en) * 2009-12-23 2012-07-17 Intel Corporation Pitch division patterning techniques
US8518788B2 (en) 2010-08-11 2013-08-27 Micron Technology, Inc. Methods of forming a plurality of capacitors
US8455341B2 (en) 2010-09-02 2013-06-04 Micron Technology, Inc. Methods of forming features of integrated circuitry
JP5330440B2 (ja) * 2011-03-23 2013-10-30 株式会社東芝 半導体装置の製造方法
US8575032B2 (en) 2011-05-05 2013-11-05 Micron Technology, Inc. Methods of forming a pattern on a substrate
US8802571B2 (en) * 2011-07-28 2014-08-12 Lam Research Corporation Method of hard mask CD control by Ar sputtering
US9076680B2 (en) 2011-10-18 2015-07-07 Micron Technology, Inc. Integrated circuitry, methods of forming capacitors, and methods of forming integrated circuitry comprising an array of capacitors and circuitry peripheral to the array
US9177794B2 (en) 2012-01-13 2015-11-03 Micron Technology, Inc. Methods of patterning substrates
US8629048B1 (en) 2012-07-06 2014-01-14 Micron Technology, Inc. Methods of forming a pattern on a substrate
US9349595B2 (en) * 2012-07-11 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Methods of manufacturing semiconductor devices
CN103839781B (zh) 2012-11-21 2016-05-25 中芯国际集成电路制造(上海)有限公司 半导体精细图案的形成方法
TWI487004B (zh) * 2013-03-01 2015-06-01 Winbond Electronics Corp 圖案化的方法及記憶體元件的形成方法
US9437479B2 (en) * 2013-11-19 2016-09-06 Applied Materials, Inc. Methods for forming an interconnect pattern on a substrate
JP6151215B2 (ja) * 2014-05-15 2017-06-21 東京エレクトロン株式会社 プラズマエッチング方法
KR102365159B1 (ko) * 2014-07-15 2022-02-18 삼성전자주식회사 커브된 터치 패널 및 이를 포함하는 표시 장치
US9184060B1 (en) * 2014-11-14 2015-11-10 Lam Research Corporation Plated metal hard mask for vertical NAND hole etch
KR102420150B1 (ko) 2015-08-19 2022-07-13 삼성전자주식회사 반도체 소자의 제조 방법
JP6748354B2 (ja) * 2015-09-18 2020-09-02 セントラル硝子株式会社 ドライエッチング方法及びドライエッチング剤
US10529617B2 (en) 2017-09-29 2020-01-07 Taiwan Semiconductor Manufacturing Company, Ltd. Metal routing with flexible space formed using self-aligned spacer patterning
DE102017127124B4 (de) * 2017-09-29 2023-09-21 Taiwan Semiconductor Manufacturing Company, Ltd. Metallbearbeitung mit flexiblen Zwischenräumen, gebildet unter Verwendung einer Strukturierung mit selbstjustierenden Spacern
CN109860041B (zh) * 2018-12-28 2020-12-29 芯创智（北京）微电子有限公司 一种集成电路精密图形制备方法

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040087114A1 (en) * 2002-10-24 2004-05-06 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US20060068596A1 (en) * 2004-09-30 2006-03-30 International Business Machines Corporation Formation of Controlled Sublithographic Structures

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5748237A (en) * 1980-09-05 1982-03-19 Nec Corp Manufacture of 2n doubling pattern
JPS6435916A (en) * 1987-07-31 1989-02-07 Hitachi Ltd Formation of fine pattern
AU2002245124A1 (en) 2000-11-13 2002-07-24 Vram Technologies, Llc Sidewalls as semiconductor etch stop and diffusion barrier
US6835665B2 (en) * 2002-03-06 2004-12-28 Hitachi High-Technologies Corporation Etching method of hardly-etched material and semiconductor fabricating method and apparatus using the method
US6713396B2 (en) * 2002-04-29 2004-03-30 Hewlett-Packard Development Company, L.P. Method of fabricating high density sub-lithographic features on a substrate
US20040161946A1 (en) * 2002-06-24 2004-08-19 Hsin-Yi Tsai Method for fluorocarbon film depositing
US7169695B2 (en) 2002-10-11 2007-01-30 Lam Research Corporation Method for forming a dual damascene structure
JP2004193400A (ja) * 2002-12-12 2004-07-08 Toshiba Corp 半導体装置の製造方法及びフォトマスク
US7250371B2 (en) 2003-08-26 2007-07-31 Lam Research Corporation Reduction of feature critical dimensions
US7115525B2 (en) * 2004-09-02 2006-10-03 Micron Technology, Inc. Method for integrated circuit fabrication using pitch multiplication
US7271107B2 (en) 2005-02-03 2007-09-18 Lam Research Corporation Reduction of feature critical dimensions using multiple masks
US20070026682A1 (en) * 2005-02-10 2007-02-01 Hochberg Michael J Method for advanced time-multiplexed etching
US20060249784A1 (en) * 2005-05-06 2006-11-09 International Business Machines Corporation Field effect transistor device including an array of channel elements and methods for forming
US7422775B2 (en) * 2005-05-17 2008-09-09 Applied Materials, Inc. Process for low temperature plasma deposition of an optical absorption layer and high speed optical annealing
US7696101B2 (en) 2005-11-01 2010-04-13 Micron Technology, Inc. Process for increasing feature density during the manufacture of a semiconductor device
US7390749B2 (en) 2005-11-30 2008-06-24 Lam Research Corporation Self-aligned pitch reduction

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20040087114A1 (en) * 2002-10-24 2004-05-06 Advanced Micro Devices, Inc. Semiconductor device having a thick strained silicon layer and method of its formation
US20060068596A1 (en) * 2004-09-30 2006-03-30 International Business Machines Corporation Formation of Controlled Sublithographic Structures

Also Published As

Publication number Publication date
US20070264830A1 (en) 2007-11-15
CN101496141A (zh) 2009-07-29
TW200746296A (en) 2007-12-16
KR101353239B1 (ko) 2014-01-17
KR20090009312A (ko) 2009-01-22
JP2009536787A (ja) 2009-10-15
WO2007133442A1 (en) 2007-11-22
CN101496141B (zh) 2011-04-06
EP2018661A1 (en) 2009-01-28
JP5048055B2 (ja) 2012-10-17
US7429533B2 (en) 2008-09-30

Similar Documents

Publication Publication Date Title
TWI419224B (zh) 提供特徵結構於蝕刻層上的方法和裝置
TWI576897B (zh) 製造方法與圖案化方法
TWI447440B (zh) 光柵之製備方法
WO2010033434A3 (en) Sidewall forming processes
US20150031201A1 (en) Trench patterning with block first sidewall image transfer
WO2009085564A3 (en) Etch with high etch rate resist mask
KR20110115101A (ko) 반도체 소자의 미세 패턴 형성 방법
JP2010516059A5 (ja)
KR20080100690A (ko) 나노 임프린트 리소그라피 공정용 템플릿 및 이를 이용한 반도체 소자 제조 방법
JP2018524814A5 (ja)
TW201633407A (zh) 半導體裝置之圖案化結構的製作方法
JP5537400B2 (ja) パターン形成方法及び装置
TW201403863A (zh) 具有孔隙之磊晶層的磊晶成長方法
JP2007133153A5 (ja)
TWI448741B (zh) 光柵之製備方法
CN106298507B (zh) 图案化方法
JP2012199410A (ja) パターン形成方法
TW201317639A (zh) 光柵
CN107403719B (zh) 在半导体器件中形成图形的方法
KR20090089497A (ko) 반도체 소자의 미세패턴 제조 방법
TW200802512A (en) Method of manufacturing suspension structure
JP2012187757A5 (ja)
JP2020516050A5 (ja)
US20140096385A1 (en) Method for producing liquid-ejection head
TWI456635B (zh) 半導體製程

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees