TWI413212B - 半導體裝置及其製造方法 - Google Patents

半導體裝置及其製造方法 Download PDF

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Publication number
TWI413212B
TWI413212B TW094122545A TW94122545A TWI413212B TW I413212 B TWI413212 B TW I413212B TW 094122545 A TW094122545 A TW 094122545A TW 94122545 A TW94122545 A TW 94122545A TW I413212 B TWI413212 B TW I413212B
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TW
Taiwan
Prior art keywords
insulating film
film
forming
layer
semiconductor device
Prior art date
Application number
TW094122545A
Other languages
English (en)
Chinese (zh)
Other versions
TW200608519A (en
Inventor
古澤健志
三浦典子
後藤欣哉
松浦正純
Original Assignee
瑞薩電子股份有限公司
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Publication of TW200608519A publication Critical patent/TW200608519A/zh
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Publication of TWI413212B publication Critical patent/TWI413212B/zh

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/081—Manufacture or treatment of dielectric parts thereof by forming openings in the dielectric parts
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/40—Formation of materials, e.g. in the shape of layers or pillars of conductive or resistive materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6529—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour
    • H10P14/6532—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by exposure to a gas or vapour by exposure to a plasma
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6516—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials
    • H10P14/6548—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed after formation of the materials by forming intermediate materials, e.g. capping layers or diffusion barriers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P70/00—Cleaning of wafers, substrates or parts of devices
    • H10P70/20—Cleaning during device manufacture
    • H10P70/27—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers
    • H10P70/277—Cleaning during device manufacture during, before or after processing of conductive materials, e.g. polysilicon or amorphous silicon layers the processing being a planarisation of conductive layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P95/00—Generic processes or apparatus for manufacture or treatments not covered by the other groups of this subclass
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/074—Manufacture or treatment of dielectric parts thereof of dielectric parts comprising thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/01—Manufacture or treatment
    • H10W20/071—Manufacture or treatment of dielectric parts thereof
    • H10W20/093—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts
    • H10W20/096—Manufacture or treatment of dielectric parts thereof by modifying materials of the dielectric parts by contacting with gases, liquids or plasmas
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/47—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts comprising two or more dielectric layers having different properties, e.g. different dielectric constants
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W20/00—Interconnections in chips, wafers or substrates
    • H10W20/40—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes
    • H10W20/45—Interconnections external to wafers or substrates, e.g. back-end-of-line [BEOL] metallisations or vias connecting to gate electrodes characterised by their insulating parts
    • H10W20/48—Insulating materials thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/63—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the formation processes
    • H10P14/6326—Deposition processes
    • H10P14/6328—Deposition from the gas or vapour phase
    • H10P14/6334—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H10P14/6336—Deposition from the gas or vapour phase using decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition in the presence of a plasma [PECVD]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/65—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials
    • H10P14/6502—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by treatments performed before or after the formation of the materials of treatments performed before formation of the materials
    • H10P14/6506—Formation of intermediate materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/66—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials
    • H10P14/668—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials
    • H10P14/6681—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si
    • H10P14/6684—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen
    • H10P14/6686—Formation of materials, e.g. in the shape of layers or pillars of insulating materials characterised by the type of materials the materials being characterised by the deposition precursor materials the precursor containing a compound comprising Si the compound comprising silicon and oxygen the compound being a molecule comprising at least one silicon-oxygen bond and the compound having hydrogen or an organic group attached to the silicon or oxygen, e.g. a siloxane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P14/00—Formation of materials, e.g. in the shape of layers or pillars
    • H10P14/60—Formation of materials, e.g. in the shape of layers or pillars of insulating materials
    • H10P14/69—Inorganic materials
    • H10P14/692—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses
    • H10P14/6921—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon
    • H10P14/6922—Inorganic materials composed of oxides, glassy oxides or oxide-based glasses containing silicon the material containing Si, O and at least one of H, N, C, F or other non-metal elements, e.g. SiOC, SiOC:H or SiONC

Landscapes

  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Formation Of Insulating Films (AREA)
TW094122545A 2004-07-06 2005-07-04 半導體裝置及其製造方法 TWI413212B (zh)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2004199709A JP4854938B2 (ja) 2004-07-06 2004-07-06 半導体装置およびその製造方法

Publications (2)

Publication Number Publication Date
TW200608519A TW200608519A (en) 2006-03-01
TWI413212B true TWI413212B (zh) 2013-10-21

Family

ID=35540448

Family Applications (1)

Application Number Title Priority Date Filing Date
TW094122545A TWI413212B (zh) 2004-07-06 2005-07-04 半導體裝置及其製造方法

Country Status (5)

Country Link
US (2) US7602063B2 (enExample)
JP (1) JP4854938B2 (enExample)
KR (1) KR101139034B1 (enExample)
CN (2) CN100539116C (enExample)
TW (1) TWI413212B (enExample)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPWO2006126536A1 (ja) * 2005-05-25 2008-12-25 日本電気株式会社 半導体装置及びその製造方法
JP5060037B2 (ja) * 2005-10-07 2012-10-31 ルネサスエレクトロニクス株式会社 半導体装置の製造方法
US8368220B2 (en) * 2005-10-18 2013-02-05 Taiwan Semiconductor Manufacturing Co. Ltd. Anchored damascene structures
US8043957B2 (en) 2006-05-17 2011-10-25 Nec Corporation Semiconductor device, method for manufacturing semiconductor device and apparatus for manufacturing semiconductor
KR100829385B1 (ko) * 2006-11-27 2008-05-13 동부일렉트로닉스 주식회사 반도체 소자 및 그 제조 방법
JP2011249678A (ja) * 2010-05-28 2011-12-08 Elpida Memory Inc 半導体装置及びその製造方法
JP5972679B2 (ja) * 2012-06-18 2016-08-17 東海旅客鉄道株式会社 炭素含有酸化ケイ素膜の製造方法
US10755995B2 (en) 2018-06-28 2020-08-25 Taiwan Semiconductor Manufacturing Co., Ltd. Warpage control of semiconductor die
JP2022037944A (ja) * 2018-12-28 2022-03-10 日産化学株式会社 水素ガスを用いた前処理によるレジスト下層膜のエッチング耐性を向上する方法
US11410879B2 (en) * 2020-04-07 2022-08-09 International Business Machines Corporation Subtractive back-end-of-line vias
US11456242B2 (en) * 2020-07-21 2022-09-27 Nanya Technology Corporation Semiconductor device with stress-relieving structures and method for fabricating the same

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20030162410A1 (en) * 1998-02-11 2003-08-28 Applied Materials, Inc. Method of depositing low K films

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JP3726226B2 (ja) * 1998-02-05 2005-12-14 日本エー・エス・エム株式会社 絶縁膜及びその製造方法
JP3078811B1 (ja) * 1998-03-26 2000-08-21 松下電器産業株式会社 配線構造体の形成方法
US6068884A (en) * 1998-04-28 2000-05-30 Silcon Valley Group Thermal Systems, Llc Method of making low κ dielectric inorganic/organic hybrid films
JP3727818B2 (ja) 1999-03-19 2005-12-21 株式会社東芝 半導体装置の配線構造及びその形成方法
JP3197007B2 (ja) 1999-06-08 2001-08-13 日本エー・エス・エム株式会社 半導体基板上のシリコン重合体絶縁膜及びその膜を形成する方法
JP4554011B2 (ja) * 1999-08-10 2010-09-29 ルネサスエレクトロニクス株式会社 半導体集積回路装置の製造方法
JP3615979B2 (ja) 2000-01-18 2005-02-02 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2001338978A (ja) * 2000-05-25 2001-12-07 Hitachi Ltd 半導体装置及びその製造方法
JP2003031580A (ja) * 2001-07-18 2003-01-31 Toshiba Corp 半導体装置の製造方法
JP3545364B2 (ja) * 2000-12-19 2004-07-21 キヤノン販売株式会社 半導体装置及びその製造方法
SG98468A1 (en) * 2001-01-17 2003-09-19 Air Prod & Chem Organosilicon precursors for interlayer dielectric films with low dielectric constants
KR100926722B1 (ko) 2001-04-06 2009-11-16 에이에스엠 저펜 가부시기가이샤 반도체 기판상의 실록산 중합체막 및 그 제조방법
JP3924501B2 (ja) * 2001-06-25 2007-06-06 Ｎｅｃエレクトロニクス株式会社 集積回路装置の製造方法
JP2003142579A (ja) * 2001-11-07 2003-05-16 Hitachi Ltd 半導体装置の製造方法および半導体装置
JP4177993B2 (ja) * 2002-04-18 2008-11-05 株式会社ルネサステクノロジ 半導体装置及びその製造方法
JP2004023030A (ja) * 2002-06-20 2004-01-22 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
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Patent Citations (1)

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Publication number Priority date Publication date Assignee Title
US20030162410A1 (en) * 1998-02-11 2003-08-28 Applied Materials, Inc. Method of depositing low K films

Also Published As

Publication number Publication date
US7602063B2 (en) 2009-10-13
US20090263963A1 (en) 2009-10-22
US20060006530A1 (en) 2006-01-12
KR101139034B1 (ko) 2012-04-30
CN100539116C (zh) 2009-09-09
CN101330045B (zh) 2010-08-11
CN101330045A (zh) 2008-12-24
KR20060049890A (ko) 2006-05-19
JP4854938B2 (ja) 2012-01-18
TW200608519A (en) 2006-03-01
US7960279B2 (en) 2011-06-14
CN1728375A (zh) 2006-02-01
JP2006024641A (ja) 2006-01-26

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