TWI408791B - 用於在三維堆疊裝置上致能靜電放電保護之系統與方法 - Google Patents

用於在三維堆疊裝置上致能靜電放電保護之系統與方法 Download PDF

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TWI408791B
TWI408791B TW098130420A TW98130420A TWI408791B TW I408791 B TWI408791 B TW I408791B TW 098130420 A TW098130420 A TW 098130420A TW 98130420 A TW98130420 A TW 98130420A TW I408791 B TWI408791 B TW I408791B
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semiconductor die
esd
semiconductor
circuit
diode
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TW201027705A (en
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Kenneth Kaskoun
Shiqun Gu
Matthew Nowak
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Qualcomm Inc
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Description

用於在三維堆疊裝置上致能靜電放電保護之系統與方法
本發明大體上係關於用於半導體裝置之靜電放電(ESD)保護，且更特定言之，係關於用於在三維堆疊半導體裝置中致能ESD保護的系統及方法。
在矽穿堆疊(through silicon stacking,TSS)中，矽晶片經堆疊以形成三維電子裝置。在此等裝置中，建構晶片之間的互連件。此等互連件常包括矽穿孔(TSV)。
經堆疊之晶片中之每一者上之每一電路需要電路的I/O埠上之ESD保護。不幸地，ESD保護電路在矽上具有相對大的佔據面積。當現存電路在三維裝置之多個晶片間分割時，可分離該等電路(及其各別ESD保護)。因此，在每一晶片上提供ESD保護以保護在不同晶片間分割的電路之每一部分。結果，ESD保護電路需要三維堆疊晶片上之甚至更多的空間。
ESD保護電路建構於三維堆疊裝置之不同晶片上之作用層之間的垂直空間(例如，矽穿孔(TSV))中，藉此利用否則將僅用於通信目的之空間。矽穿孔之垂直表面區域吸收大的ESD事件。
在一實施例中，一種半導體晶粒包括在建構於一基板中之至少一介層孔內的至少一主動電路。
在另一實施例中，一ESD保護二極體在垂直維度上形成於堆疊晶粒之作用層之間。此ESD保護二極體可由該堆疊之兩個半導體晶粒上之電路共用，藉此節省空間及減少由ESD保護電路需要的晶片面積。
在又一實施例中，建構一具有至少一矽穿孔(TSV)之半導體晶粒。該TSV含有至少一主動電路。該半導體晶粒與一第二半導體晶粒以一平行組合堆疊，且該TSV垂直地定位於該等堆疊晶粒之作用層之間。
在又一實施例中，一種用於建構靜電放電(ESD)保護電路之方法包括配置一堆疊半導體裝置使得來自該裝置之一半導體晶粒之矽穿孔(TSV)耦接至一鄰近半導體晶粒。藉由使用此配置，來自該等半導體晶粒中之至少一者之I/O襯墊可耦接至至少部分地建構於該等TSV中的至少一者內之靜電放電(ESD)保護電路。
在再一實施例中，一種堆疊半導體裝置包括彼此以平行關係定位之第一半導體晶粒及第二半導體晶粒。該裝置亦包括用於耦接該等經定位之晶粒之作用層的構件。該耦接構件包括主動元件。
前文已相當廣泛地概述了本發明之特徵及技術優勢，以便可更好地理解以下之[實施方式]。在下文中將描述本發明之額外特徵及優勢，其形成本發明之申請專利範圍的主題。熟習此項技術者應瞭解，所揭示之概念及特定實施例可易於用作修改或設計其他用於執行本發明之相同目的之結構的基礎。熟習此項技術者亦應認識到，此等等效構造並不偏離如在隨附之申請專利範圍中陳述之本發明之精神及範疇。當結合附圖考慮時，自以下描述將更好地理解咸信為本發明所特有之新穎特徵(關於其組織及操作方法兩者)以及其他目的及優勢。然而，應明確理解，僅為說明及描述之目的而提供該等圖中之每一者，且並不意欲作為本發明之限制的定義。
為獲得對本發明之更完整的理解，現結合隨附圖式參考以下描述。
圖1A及圖1B說明習知ESD保護電路。圖1A展示裝置10之一部分，其中I/O襯墊11接受(諸如)可隨ESD事件發生之高電壓或高電流放電。為保護電路14免受ESD事件之消極影響，湧浪二極體(surge diode)12將過量電壓放電至Vdd。在一些狀況下，(例如)當負的高電壓(或電流)事件發生時，二極體100將過量電壓放電至Vss或地面。通常，二極體12、100極大。
圖1B展示具有P區102及N區101之典型二極體結構100。此等二極體結構100為大的以便處置ESD事件所涉及之相對大的電壓。此等二極體中之一者通常與每個I/O襯墊相關聯。
圖2A及圖2B展示本發明之一實施例。圖2A展示裝置20，該裝置20具有彼此呈堆疊之平行關係之晶粒21及22且具有ESD保護裝置200。頂部晶粒21之背面層21-1定位於其表面層(作用層)21-2之上。底部晶粒22係以相同定向定位，其中其背面層22-1位於其表面層(作用層)22-2之上。注意，每一晶粒可具有任何所要定向且仍可應用本文中所教示之概念。
矽穿孔(TSV)23建構於晶粒21之作用表面21-2與晶粒22之作用表面22-2之間的背面層22-1中以視需要載運晶粒間通信。此等介層孔23中之一或多者經建構為具有一或多個二極體之垂直ESD保護裝置(諸如，裝置200)。在此上下文中，垂直意謂垂直於ESD保護裝置200經設計以保護之晶粒的平面。垂直ESD保護裝置200可完全建構於一個晶片上，或部分地建構於兩個鄰近堆疊晶片中之每一晶片上。又，垂直裝置200無需精確地垂直於晶片21、22之縱向區域，而是可傾斜，或甚至部分地平行於該區域中之堆疊晶片21、22。
圖2B說明具有一對二極體201及202之一個此種垂直建構之裝置200。圖中展示二極體201具有圍繞N材料24之P材料27且圖中展示二極體202具有圍繞P材料27之N材料26。絕緣體25將每一二極體201、202與半導體基板28分離。圖中展示電極連接件29致能對N及P區之接達。注意，雖然此實施例中正論述二極體，但是可視需要建構電晶體或其他主動元件。
在一實施例中，形成此等二極體201、202之矽的厚度在20微米與100微米之間，藉此使得二極體201、202相對大，且能夠耐受靜電放電(ESD)事件之電壓。有效二極體區域係藉由使用圍繞介層孔之圓周之表面區域來增加，該表面區域在一實施例中可大體上為圓柱形的。換言之，在使用相同量之晶片「面積」時，使用三維構造而非標準二維二極體構造可增加總體作用區域。注意，當如圖2A中所展示堆疊晶粒21、22時，兩個晶粒21、22可共用ESD二極體201、202之共同集合。又，一個二極體可建構於一個晶片上，而另一個二極體(或一或多個二極體之其他部分)可建構於另一個晶片上。
圖3A至圖3G展示關於圖2A及圖2B中所展示之實施例的用於在矽穿孔(TSV)內建構二極體之方法的實施例。
圖3A展示藉由蝕刻建構之介層孔。接著，將絕緣體材料25沈積於矽30(或其他半導體材料)上方。
圖3B展示將N材料26沈積至兩個二極體空間中的在絕緣體材料25之上。
圖3C展示自左側二極體或空間選擇性地蝕刻掉(在此實例中)N材料26。N材料26保留於右側二極體空間內。
圖3D展示將P材料27沈積於左側二極體空間內且P材料27亦沈積於右側二極體空間內。
圖3E展示將N材料24沈積於左側二極體空間及右側二極體空間兩者內。
圖3F展示拋光或以其他方式移除過量材料以產生PN二極體及NP二極體。在另一實施例中，替代以上所述之NP二極體及PN二極體，NP電晶體及PN電晶體(或其他主動元件)產生於「二極體空間」中。
接著可以眾所熟知之方式製造作用層31之常規電路。氧化物沈積(未圖示)使所製造之電路絕緣。接著可形成接觸件301、302、303及304使得二極體為可接達的。可以許多方式形成此等接觸件且若需要，此等接觸件可為導線、襯墊或其組合。舉例而言，襯墊302、303可為I/O襯墊，接觸件301可耦接至Vdd且接觸件304可耦接至Vss，如圖4中所見。
根據一實施例，PN二極體或NP二極體之面積足以安全地處置(耗散)靜電放電。此等放電可為大約100伏特至數千伏特。
圖3G展示藉由背面研磨自背面(底部)曝露之TSV。接著沈積絕緣層(未圖示)且蝕刻介層孔使得至二極體之背側之連接藉由使用晶粒間連接件405(圖4)係可能的。藉由使用此背側連接，另一堆疊之晶粒400(圖4)之作用層上之常規電路可耦接至TSV且可受益於另一晶粒上的ESD保護。在另一實施例中，來自背側之連接使二極體能夠耦接至一接地。此實施例在類比電路存在於三維裝置中且應減少雜訊影響時可為有用的。
參看圖4，現解釋藉由介層孔內之二極體201、202對內部電路410的保護。內部電路410接收來自PAD 420之信號。若所接收信號之電壓過低，則連接至Vss的右側二極體201接通且電流將自PAD 420流至Vss。若電壓過高，則二極體202接通且電流自PAD 420流至Vdd。若電壓為可接受的(例如，未發生ESD事件)，則內部電路410接收來自PAD 420之信號。
注意，所說明之製程為半導體製造中之典型製程且任何眾所熟知之技術可用以在垂直方向上在半導體裝置之作用層之間形成ESD保護裝置。亦注意，雖然本文中之論述已集中於建構於介層孔中之ESD保護裝置中，但亦可如此建構其他裝置類型。功率管理裝置及電路僅為可使用本發明之教示建構之裝置的多種類型中之一種。進一步注意，在一些情形下，主動裝置之一部分可建構於建構有介層孔之晶粒上。
雖然已詳細描述本發明及其優勢，但應理解在不背離如由隨附申請專利範圍所界定之本發明之精神及範疇的情況下可對本文進行各種改變、替換及更改。此外，本申請案之範疇不意欲限制於說明書中所描述之過程、機器、製造、物質組成、手段、方法及步驟之特定實施例。如一般熟習此項技術者將易於自本發明之揭示內容瞭解，根據本發明，可利用當前存在或日後將開發之執行與本文中描述之相應實施例大體上相同功能或達成大體上相同結果之過程、機器、製造、物質組成、構件、方法或步驟。因此，隨附申請專利範圍意欲在其範疇中包括此等過程、機器、製造、物質組成、構件、方法或步驟。
10．．．裝置
11．．．I/O襯墊
12．．．湧浪二極體
14．．．電路
20．．．裝置
21．．．晶粒
21-1．．．背面層
21-2．．．表面層
22．．．晶粒
22-1．．．背面層
22-2．．．表面層
23．．．矽穿孔(TSV)
24．．．N材料
25．．．絕緣體/絕緣體材料
26．．．N材料
27．．．P材料
28．．．半導體基板
29．．．電極連接件
30．．．矽
31．．．作用層
100．．．二極體
101．．．N區
102．．．P區
200．．．ESD保護裝置
201．．．二極體
202．．．二極體
301．．．接觸件
302．．．接觸件
303．．．接觸件
304．．．接觸件
400．．．堆疊晶粒
405．．．晶粒間連接件
410．．．內部電路
420．．．PAD
圖1A及圖1B說明習知ESD保護電路。
圖2A及圖2B為展示一實施例之橫截面視圖。
圖3A至圖3G為展示用於建構圖2A及圖2B中所展示之裝置之方法的實施例之橫截面視圖。
圖4為展示又一實施例之橫截面視圖。
20．．．裝置
21．．．晶粒
21-1．．．背面層
21-2．．．表面層
22．．．晶粒
22-1．．．背面層
22-2．．．表面層
23．．．矽穿孔(TSV)
200．．．ESD保護裝置

Claims (11)

  1. 一種三維(3-D)堆疊積體電路裝置，其包含：第一及第二半導體晶粒，其相對於彼此堆疊且整合於一單一電路裝置中；複數個穿孔，其每一者經建構以實質上在該第一半導體晶粒之作用層與該第二半導體晶粒之作用層之間延伸且經組態以在該第一半導體晶粒與該第二半導體晶粒之間提供通信；及主動電路，其至少部分地建構於該複數個穿孔中之至少一者內，該第一半導體晶粒與該第二半導體晶粒共用該主動電路。
  2. 如請求項1之裝置，其中該主動電路包含半導體裝置。
  3. 如請求項1之裝置，其中該主動電路包含至少一靜電放電(ESD)保護裝置。
  4. 如請求項1之裝置，其中該主動電路包含P/N接面裝置。
  5. 如請求項1之裝置，其中該主動電路係建構於該第一及該第二半導體晶粒之兩者中。
  6. 一種用於建構一三維(3-D)堆疊積體電路裝置之方法，該方法包含：將一第一半導體晶粒相關於一第二半導體晶粒作堆疊，且將該第一及該第二半導體晶粒整合於一單一電路裝置中；實質上在該第一半導體晶粒之作用層與該第二半導體晶粒之作用層之間製造複數個穿孔，該複數個穿孔經組 態以在該第一半導體晶粒與該第二半導體晶粒之間提供通信；及至少部分地在該複數個穿孔中之至少一者內建構主動電路，且該第一半導體晶粒與該第二半導體晶粒共用該主動電路。
  7. 如請求項6之方法，其中該主動電路包含P/N接面裝置。
  8. 如請求項6之方法，其中該主動電路包含：一靜電放電(ESD)保護電路。
  9. 如請求項8之方法，其中該ESD保護電路包含一二極體。
  10. 一種用於三維(3-D)堆疊半導體裝置中之靜電放電保護之方法，該方法包含：將一第一半導體晶粒相關於一第二半導體晶粒作堆疊，且將該第一及該第二半導體晶粒整合於一單一電路中；將穿孔自一半導體裝置之該第一半導體晶粒之一部分耦接至該第二半導體晶粒之一部分，該耦接包含：將來自該第一及該第二半導體晶粒中之至少一者之I/O襯墊耦接至至少部分地建構於該等穿孔中的至少一者內之靜電放電(ESD)保護電路，該第一半導體晶粒與該第二半導體晶粒共用該ESD保護電路。
  11. 如請求項10之方法，其中該ESD保護電路包含：一二極體。
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US20120061804A1 (en) 2012-03-15
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