RU2011113741A - Системы и способы для обеспечения защиты от электростатического разряда в трехмерных многоуровневых устройствах - Google Patents
Системы и способы для обеспечения защиты от электростатического разряда в трехмерных многоуровневых устройствах Download PDFInfo
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- RU2011113741A RU2011113741A RU2011113741/28A RU2011113741A RU2011113741A RU 2011113741 A RU2011113741 A RU 2011113741A RU 2011113741/28 A RU2011113741/28 A RU 2011113741/28A RU 2011113741 A RU2011113741 A RU 2011113741A RU 2011113741 A RU2011113741 A RU 2011113741A
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- 238000000034 method Methods 0.000 title claims 9
- 239000004065 semiconductor Substances 0.000 claims abstract 45
- 239000013078 crystal Substances 0.000 claims abstract 30
- 229910052710 silicon Inorganic materials 0.000 claims abstract 8
- 239000010703 silicon Substances 0.000 claims abstract 8
- 239000000758 substrate Substances 0.000 claims abstract 4
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 claims 7
- 230000007704 transition Effects 0.000 claims 6
- 230000008878 coupling Effects 0.000 claims 2
- 238000010168 coupling process Methods 0.000 claims 2
- 238000005859 coupling reaction Methods 0.000 claims 2
- 238000004519 manufacturing process Methods 0.000 claims 1
- 230000001012 protector Effects 0.000 abstract 1
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Abstract
1. Полупроводниковый кристалл, содержащий: ! по меньшей мере, одну активную схему в, по меньшей мере, одном переходном отверстии, сформированном в подложке на первом полупроводником кристалле. ! 2. Полупроводниковый кристалл по п.1, в котором упомянутый первый полупроводниковый кристалл образует многоуровневую структуру в комбинации с еще одним полупроводниковым кристаллом, причем упомянутая активная схема располагается между активными слоями упомянутых наложенных друг на друга кристаллов. ! 3. Полупроводниковый кристалл по п.2, в котором упомянутая активная схема соединена с контактными подложками ввода/вывода от обоих наложенных друг на друга полупроводниковых кристаллов. ! 4. Полупроводниковый кристалл по п.1, в котором упомянутая активная схема является частью устройства защиты от Электростатического Разряда (ESD). ! 5. Полупроводниковый кристалл по п.4, в котором упомянутое устройство ESD-защиты содержит P/N-переходы, имеющие достаточную площадь для надежного рассеивания электростатических разрядов. ! 6. Трехмерное многоуровневое полупроводниковое устройство, содержащее: ! первый и второй полупроводниковые кристаллы, наложенные друг на друга; ! по меньшей мере, одно сквозное кремниевое переходное отверстие (TSV), сформированное, чтобы проходить, по существу, между активными слоями первого и второго полупроводниковых кристаллов; и ! активную схему, сформированную, по меньшей мере, частично в упомянутом, по меньшей мере, одном сквозном кремниевом переходном отверстии. ! 7. Устройство по п.6, в котором упомянутая активная схема содержит полупроводниковые устройства. ! 8. Устройство по п.6, в котором упомянутая акт�
Claims (22)
1. Полупроводниковый кристалл, содержащий:
по меньшей мере, одну активную схему в, по меньшей мере, одном переходном отверстии, сформированном в подложке на первом полупроводником кристалле.
2. Полупроводниковый кристалл по п.1, в котором упомянутый первый полупроводниковый кристалл образует многоуровневую структуру в комбинации с еще одним полупроводниковым кристаллом, причем упомянутая активная схема располагается между активными слоями упомянутых наложенных друг на друга кристаллов.
3. Полупроводниковый кристалл по п.2, в котором упомянутая активная схема соединена с контактными подложками ввода/вывода от обоих наложенных друг на друга полупроводниковых кристаллов.
4. Полупроводниковый кристалл по п.1, в котором упомянутая активная схема является частью устройства защиты от Электростатического Разряда (ESD).
5. Полупроводниковый кристалл по п.4, в котором упомянутое устройство ESD-защиты содержит P/N-переходы, имеющие достаточную площадь для надежного рассеивания электростатических разрядов.
6. Трехмерное многоуровневое полупроводниковое устройство, содержащее:
первый и второй полупроводниковые кристаллы, наложенные друг на друга;
по меньшей мере, одно сквозное кремниевое переходное отверстие (TSV), сформированное, чтобы проходить, по существу, между активными слоями первого и второго полупроводниковых кристаллов; и
активную схему, сформированную, по меньшей мере, частично в упомянутом, по меньшей мере, одном сквозном кремниевом переходном отверстии.
7. Устройство по п.6, в котором упомянутая активная схема содержит полупроводниковые устройства.
8. Устройство по п.6, в котором упомянутая активная схема содержит, по меньшей мере, одно устройство защиты от Электростатического Разряда (ESD).
9. Устройство по п.6, в котором упомянутая активная схема содержит устройства с P/N-переходом.
10. Устройство по п.6, в котором упомянутая активная схема сформирована в обоих полупроводниковых кристаллах.
11. Способ изготовления полупроводникового устройства, содержащий этапы, на которых:
формируют первый полупроводниковый кристалл, содержащий, по меньшей мере, одно сквозное кремниевое переходное отверстие (TSV), причем упомянутое сквозное кремниевое переходное отверстие содержит, по меньшей мере, одну активную схему; и
компонуют первый полупроводниковый кристалл и второй полупроводниковый кристалл в многоуровневую структуру таким образом, чтобы упомянутое сквозное кремниевое переходное отверстие проходило между активными слоями упомянутых первого и второго полупроводниковых кристаллов.
12. Способ по п.11, дополнительно содержащий этап, на котором:
связывают схему, изготовленную в упомянутом первом полупроводниковом кристалле, с упомянутой, по меньшей мере, одной активной схемой.
13. Способ по п.12, дополнительно содержащий этап, на котором:
связывают схему, изготовленную в упомянутом втором полупроводниковом кристалле, с упомянутой, по меньшей мере, одной активной схемой.
14. Способ по п.13, в котором связь от второго полупроводникового кристалла дополняет связь от первого полупроводникового кристалла.
15. Способ по п.11, в котором упомянутая активная схема содержит:
устройство защиты от Электростатического Разряда (ESD).
16. Способ по п.15, в котором упомянутая схема ESD-защиты содержит диод.
17. Способ защиты от электростатического разряда в многоуровневых полупроводниковых устройствах, содержащий этапы, на которых:
соединяют сквозные кремниевые переходные отверстия (TSV) от части одного полупроводникового кристалла упомянутого полупроводникового устройства к части смежного полупроводникового кристалла, причем на этом этапе:
соединяют контактные площадки ввода/вывода, по меньшей мере, одного из упомянутых полупроводниковых кристаллов со схемой защиты от Электростатического Разряда (ESD), сформированной, по меньшей мере, частично внутри, по меньшей мере, одного из упомянутых TSV.
18. Способ по п.17, дополнительно содержащий этап, на котором:
соединяют контактные площадки ввода/вывода от второго полупроводникового кристалла со схемой ESD-защиты.
19. Способ по п.18, в котором упомянутая схема ESD-защиты содержит диод.
20. Полупроводниковое многоуровневое устройство, содержащее:
первый и второй полупроводниковые кристаллы, расположенные параллельно друг другу; и
средство для соединения активных слоев упомянутых кристаллов, причем упомянутое средство соединения включает в себя активные элементы.
21. Устройство по п.20, в котором упомянутое средство соединения содержит:
по меньшей мере, одно сквозное кремниевое переходное отверстие (TSV), содержащее в себе активные элементы.
22. Устройство по п.21, в котором упомянутые активные элементы имеют достаточную площадь для того, чтобы надежно рассеивать электростатические разряды, возникающие в каком-либо из упомянутых полупроводниковых кристаллов.
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US12/206,914 | 2008-09-09 | ||
US12/206,914 US8080862B2 (en) | 2008-09-09 | 2008-09-09 | Systems and methods for enabling ESD protection on 3-D stacked devices |
PCT/US2009/055620 WO2010030532A1 (en) | 2008-09-09 | 2009-09-01 | Systems and methods for enabling esd protection on 3-d stacked devices |
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US (2) | US8080862B2 (ru) |
EP (1) | EP2335282A1 (ru) |
JP (2) | JP2012502477A (ru) |
KR (1) | KR101267862B1 (ru) |
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BR (1) | BRPI0918915A2 (ru) |
CA (1) | CA2735689C (ru) |
MX (1) | MX2011002564A (ru) |
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Also Published As
Publication number | Publication date |
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US20120061804A1 (en) | 2012-03-15 |
CN102150266B (zh) | 2016-01-20 |
US20100059869A1 (en) | 2010-03-11 |
RU2469434C1 (ru) | 2012-12-10 |
KR20110069064A (ko) | 2011-06-22 |
TW201027705A (en) | 2010-07-16 |
JP2015179848A (ja) | 2015-10-08 |
JP2012502477A (ja) | 2012-01-26 |
CA2735689A1 (en) | 2010-03-18 |
WO2010030532A1 (en) | 2010-03-18 |
KR101267862B1 (ko) | 2013-05-27 |
CA2735689C (en) | 2016-06-21 |
TWI408791B (zh) | 2013-09-11 |
BRPI0918915A2 (pt) | 2018-02-14 |
EP2335282A1 (en) | 2011-06-22 |
JP6104976B2 (ja) | 2017-03-29 |
US8080862B2 (en) | 2011-12-20 |
US8847360B2 (en) | 2014-09-30 |
CN102150266A (zh) | 2011-08-10 |
MX2011002564A (es) | 2011-07-28 |
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