CN102150266A - 用于实现三维堆叠装置上的静电放电保护的系统及方法 - Google Patents

用于实现三维堆叠装置上的静电放电保护的系统及方法 Download PDF

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CN102150266A
CN102150266A CN2009801353309A CN200980135330A CN102150266A CN 102150266 A CN102150266 A CN 102150266A CN 2009801353309 A CN2009801353309 A CN 2009801353309A CN 200980135330 A CN200980135330 A CN 200980135330A CN 102150266 A CN102150266 A CN 102150266A
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semiconductor die
active
circuit
semiconductor
hole
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CN102150266B (zh
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肯尼斯·卡斯考恩
顾时群
马修·诺瓦克
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Abstract

本发明提供一种静电放电(ESD)保护装置，其制造于位于堆叠半导体裸片的有源层之间的垂直空间中，因此利用原本将仅用于通信目的的空间。穿硅通孔(TSV)的垂直表面区域用于吸收由ESD事件引起的大电压。在一个实施例中，ESD二极管形成于位于堆叠装置的所述半导体裸片的有源层之间的垂直TSV中。此ESD二极管可由所述堆叠的两个半导体裸片上的电路共享，因此节省空间并减少ESD保护电路所需的裸片面积。

Description

用于实现三维堆叠装置上的静电放电保护的系统及方法
技术领域
本发明大体上涉及用于半导体装置的静电放电(ESD)保护，且更明确地说，涉及用于实现三维堆叠半导体装置中的ESD保护的系统及方法。
背景技术
在穿硅堆叠(through silicon stacking，TSS)中，硅芯片经堆叠以形成三维电子装置。在此类装置中，构造芯片之间的互连件。这些互连件常包括穿硅通孔(through silicon via，TSV)。
经堆叠的芯片中的每一者上的每一电路需要电路的I/O端口上的ESD保护。不幸的是，ESD保护电路在硅上具有相对大的占据面积。当现存电路在三维装置的多个芯片间分割时，可分离所述电路(及其相应ESD保护)。因此，在每一芯片上提供ESD保护以保护在不同芯片间分割的电路的每一部分。结果，ESD保护电路需要三维堆叠芯片上的甚至更多的空间。
发明内容
ESD保护电路构造于三维堆叠装置的不同芯片上的有源层之间的垂直空间(例如，穿硅通孔(TSV))中，因此利用原本将仅用于通信目的的空间。穿硅通孔的垂直表面区域吸收大的ESD事件。
在一个实施例中，半导体裸片包括在构造于衬底中的至少一个通孔内的至少一个有源电路。
在另一实施例中，ESD保护二极管在垂直维度上形成于堆叠裸片的有源层之间。此ESD保护二极管可由所述堆叠的两个半导体裸片上的电路共享，因此节省空间并减少由ESD保护电路需要的芯片面积。
在又一实施例中，构造具有至少一个穿硅通孔(TSV)的半导体裸片。所述TSV含有至少一个有源电路。所述半导体裸片与第二半导体裸片以平行组合堆叠，且所述TSV垂直地定位于所述堆叠裸片的有源层之间。
在又一实施例中，用于构造静电放电(ESD)保护电路的方法包括布置堆叠半导体装置使得来自所述装置的一个半导体裸片的穿硅通孔(TSV)耦合到邻近半导体裸片。通过使用此布置，来自所述半导体裸片中的至少一者的I/O衬垫可耦合到至少部分地构造于所述TSV中的至少一者内的静电放电(ESD)保护电路。
在再一实施例中，堆叠半导体装置包括彼此以平行关系定位的第一及第二半导体裸片。所述装置还包括用于耦合所述经定位裸片的有源层的装置。所述耦合装置包括有源元件。
前文已相当广泛地概述了本发明的特征及技术优势，以便可更好地理解以下的详细描述。在下文中将描述本发明的额外特征及优势，其形成本发明的权利要求书的主题。所属领域的技术人员应了解，所揭示的概念及特定实施例可易于用作修改或设计其它用于执行本发明的相同目的的结构的基础。所属领域的技术人员还应认识到，所述等效构造并不脱离如在所附权利要求书中陈述的本发明的精神及范围。当结合附图考虑时，从以下描述将更好地理解据信为本发明所特有的新颖特征(关于其组织及操作方法两者)以及其它目的及优势。然而，应明确理解，仅为说明及描述的目的而提供所述图中的每一者，且并不希望将其作为本发明的限制的定义。
附图说明
为获得对本发明的更完整的理解，现结合附图参考以下描述。
图1A及图1B说明常规ESD保护电路。
图2A及图2B为展示一个实施例的横截面视图。
图3A到图3G为展示用于构造图2A及图2B中所展示的装置的方法的实施例的横截面视图。
图4为展示又一实施例的横截面视图。
具体实施方式
图1A及图1B说明常规ESD保护电路。图1A展示装置10的一部分，其中I/O衬垫11接受(例如)可随ESD事件发生的高电压或高电流放电。为保护电路14免受ESD事件的不利影响，浪涌二极管(surge diode)12将过量电压放电到Vdd。在一些状况下，(例如)当不利的高电压(或电流)事件发生时，二极管100将过量电压放电到Vss或接地。通常，二极管12、100极大。
图1B展示具有P区段102及N区段101的典型二极管结构100。这些二极管结构100是大的，以便处置ESD事件所涉及的相对大的电压。这些二极管中的一者通常与每个I/O衬垫相关联。
图2A及图2B展示本发明的一个实施例。图2A展示装置20，所述装置20具有彼此呈堆叠的平行关系的裸片21及22，且具有ESD保护装置200。顶部裸片21的背面层21-1定位于其表面层(有源层)21-2的顶部上。底部裸片22是以相同定向定位，其中其背面层22-1位于其表面层(有源层)22-2的顶部上。注意，每一裸片可具有任何所要定向且仍可应用本文中所教示的概念。
穿硅通孔(TSV)23构造于裸片21的有源表面21-2与裸片22的有源表面22-2之间的背面层22-1中以视需要携载裸片间通信。这些通孔23中的一或一者以上经构造为具有一个或一个以上二极管的垂直ESD保护装置(例如，装置200)。在此上下文中，垂直意味着垂直于ESD保护装置200经设计用于保护的裸片的平面。垂直ESD保护装置200可完全构造于一个芯片上，或部分地构造于两个邻近堆叠芯片中的每一芯片上。又，垂直装置200无需精确地垂直于芯片21、22的纵向区域，而是可倾斜，或甚至部分地平行于所述区域中的堆叠芯片21、22。
图2B说明具有一对二极管201及202的一个此种垂直构造的装置200。图中展示二极管201具有围绕N材料24的P材料27且图中展示二极管202具有围绕P材料27的N材料26。绝缘体25将每一二极管201、202与半导体衬底28分离。图中展示电极连接件29实现对N及P区段的接达。注意，虽然此实施例中正论述二极管，但是可视需要构造晶体管或其它有源元件。
在一个实施例中，形成这些二极管201、202的硅的厚度在20微米与100微米之间，因此使得二极管201、202相对大，且能够耐受静电放电(ESD)事件的电压。有效二极管区域是通过使用围绕通孔的圆周的表面区域来增加，所述表面区域在一个实施例中可大体上为圆柱形的。换句话说，在使用相同量的芯片“实际使用面积(real estate)”时，使用三维构造而非标准二维二极管构造可增加总体有源区域。注意，当如图2A中所展示堆叠裸片21、22时，两个裸片21、22可共享ESD二极管201、202的共同集合。并且，一个二极管可构造于一个芯片上，而另一个二极管(或一个或一个以上二极管的其它部分)可构造于另一个芯片上。
图3A到图3G展示关于图2A及图2B中所展示的实施例的用于在穿硅通孔(TSV)内构造二极管的方法的实施例。
图3A展示通过蚀刻构造的通孔。接着，将绝缘体材料25沉积于硅30(或其它半导体材料)上方。
图3B展示将N材料26沉积到两个二极管空间中在绝缘体材料25的顶部上。
图3C展示从左侧二极管或空间选择性地蚀刻掉(在此实例中)N材料26。N材料26保留于右侧二极管空间内。
图3D展示将P材料27沉积于左侧二极管空间内且还将P材料27沉积于右侧二极管空间内。
图3E展示将N材料24沉积于左侧二极管空间及右侧二极管空间两者内。
图3F展示抛光或以其它方式移除过量材料以产生PN二极管及NP二极管。在另一实施例中，替代以上所述的NP二极管及PN二极管，NP晶体管及PN晶体管(或其它有源元件)产生于“二极管空间”中。
接着可以众所周知的方式制造有源层31的正常电路。氧化物沉积(未图示)使所制造的电路绝缘。接着可形成接触件301、302、303及304使得二极管为可接达的。可以许多方式形成这些接触件且如果需要，这些接触件可为导线、衬垫或其组合。举例来说，衬垫302、303可为I/O衬垫，接触件301可耦合到Vdd且接触件304可耦合到Vss，如图4中所见。
根据一实施例，PN二极管或NP二极管的面积足以安全地处置(耗散)静电放电。这些放电可为大约100伏到数千伏。
图3G展示通过背面研磨从背面(底部)暴露的TSV。接着沉积绝缘层(未图示)且蚀刻通孔使得到二极管的背侧的连接通过使用裸片到裸片连接件405(图4)是可能的。通过使用此背侧连接，另一堆叠的裸片400(图4)的有源层上的正常电路可耦合到TSV且可受益于另一裸片上的ESD保护。在另一实施例中，来自背侧的连接使二极管能够耦合到接地。此实施例在模拟电路存在于三维装置中且应减少噪声影响时可为有用的。
参看图4，现解释通过通孔内的二极管201、202对内部电路410的保护。内部电路410接收来自PAD 420的信号。如果所接收信号的电压过低，则连接到Vss的右侧二极管201接通且电流将从PAD 420流到Vss。如果电压过高，则二极管202接通且电流从PAD 420流到Vdd。如果电压为可接受的(例如，未发生ESD事件)，则内部电路410接收来自PAD 420的信号。
注意，所说明的工艺为半导体制造中的典型工艺且任何众所周知的技术可用以在垂直方向上在半导体装置的有源层之间形成ESD保护装置。还注意，虽然本文中的论述已集中于构造于通孔中的ESD保护装置中，但还可如此构造其它装置类型。功率管理装置及电路仅为可使用本发明的教示构造的装置的类型中的一种。另外注意，在一些情形下，有源装置的一部分可构造于构造有通孔的裸片上。
虽然已详细描述本发明及其优势，但应理解在不脱离如由所附权利要求书所界定的本发明的精神及范围的情况下可在本文中进行各种改变、替换及更改。此外，不希望将本申请案的范围限制于说明书中所描述的工艺、机器、制造、物质组成、手段、方法及步骤的特定实施例。如所属领域的技术人员将易于从本发明的揭示内容了解，根据本发明，可利用当前存在或日后将开发的执行与本文中描述的对应实施例大体上相同功能或实现大体上相同结果的过程、机器、制造、物质组成、装置、方法或步骤。因此，希望所附权利要求书在其范围内包括此类过程、机器、制造、物质组成、装置、方法或步骤。

Claims (22)

1.一种半导体裸片，其包含：
至少一个有源电路，其位于构造于第一半导体裸片上的衬底中的至少一个通孔内。
2.根据权利要求1所述的半导体裸片，其中所述第一半导体裸片是与另一半导体裸片组合堆叠，且其中所述有源电路定位于所述堆叠裸片的有源层之间。
3.根据权利要求2所述的半导体裸片，其中所述有源电路耦合到来自所述堆叠半导体裸片的两者的I/O衬垫。
4.根据权利要求1所述的半导体裸片，其中所述有源电路是静电放电(ESD)保护装置的一部分。
5.根据权利要求4所述的半导体裸片，其中所述ESD保护装置含有P/N结，所述P/N结具有用以安全地耗散静电放电的足够面积。
6.一种三维堆叠半导体装置，其包含：
第一及第二半导体裸片，其相对于彼此堆叠；
至少一个穿硅通孔(TSV)，其经构造以大体上在所述第一半导体裸片的有源层与第二半导体裸片的有源层之间延伸；以及
有源电路，其至少部分地构造于所述至少一个穿硅通孔内。
7.根据权利要求6所述的装置，其中所述有源电路包含半导体装置。
8.根据权利要求6所述的装置，其中所述有源电路包含至少一个静电放电(ESD)保护装置。
9.根据权利要求6所述的装置，其中所述有源电路包含P/N结装置。
10.根据权利要求6所述的装置，其中所述有源电路构造于所述半导体裸片的两者中。
11.一种用于构造半导体装置的方法，所述方法包含：
构造第一半导体裸片，所述第一半导体裸片中具有至少一个穿硅通孔(TSV)，所述穿硅通孔含有至少一个有源电路；以及
将所述第一半导体裸片与第二半导体裸片堆叠，使得所述穿硅通孔在所述第一半导体裸片的有源层与第二半导体裸片的有源层之间延伸。
12.根据权利要求11所述的方法，其进一步包含：
将制造于所述第一半导体裸片中的电路耦合到所述至少一个有源电路。
13.根据权利要求12所述的方法，其进一步包含：
将制造于所述第二半导体裸片中的电路耦合到所述至少一个有源电路。
14.根据权利要求13所述的方法，其中所述从所述第二半导体裸片耦合是对所述从所述第一半导体裸片耦合的添加。
15.根据权利要求11所述的方法，其中所述有源电路包含：
静电放电(ESD)保护电路。
16.根据权利要求15所述的方法，其中所述ESD保护电路包含二极管。
17.一种用于堆叠半导体装置中的静电放电保护的方法，所述方法包含：
将穿硅通孔(TSV)从所述半导体装置的一个半导体裸片的一部分耦合到邻近半导体裸片的一部分，所述耦合包含：
将来自所述半导体裸片中的至少一者的I/O衬垫耦合到至少部分地构造于所述TSV中的至少一者内的静电放电(ESD)保护电路。
18.根据权利要求17所述的方法，其进一步包含：
将来自所述半导体裸片中的第二者的I/O衬垫耦合到所述ESD保护电路。
19.根据权利要求18所述的方法，其中所述ESD保护电路包含：
二极管。
20.一种堆叠半导体装置，其包含：
第一及第二半导体裸片，其相对于彼此以平行关系定位；以及
用于耦合所述经定位裸片的有源层的装置，所述耦合装置包括有源元件。
21.根据权利要求20所述的装置，其中所述耦合装置包含：
至少一个穿硅通孔(TSV)，其具有含于其中的所述有源元件。
22.根据权利要求21所述的装置，其中所述有源元件具有用以安全地耗散发生于所述半导体裸片中的任一者上的静电放电的足够面积。
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US20100059869A1 (en) 2010-03-11
RU2469434C1 (ru) 2012-12-10
KR20110069064A (ko) 2011-06-22
TW201027705A (en) 2010-07-16
JP2015179848A (ja) 2015-10-08
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CA2735689A1 (en) 2010-03-18
WO2010030532A1 (en) 2010-03-18
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CA2735689C (en) 2016-06-21
TWI408791B (zh) 2013-09-11
BRPI0918915A2 (pt) 2018-02-14
EP2335282A1 (en) 2011-06-22
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US8080862B2 (en) 2011-12-20
US8847360B2 (en) 2014-09-30
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