JP6104976B2 - 3−d積層型デバイスのesd保護を可能にするシステム及び方法 - Google Patents
3−d積層型デバイスのesd保護を可能にするシステム及び方法 Download PDFInfo
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Description
以下に本願発明の当初の特許請求の範囲に記載された発明を付記する。
[C1]
第1半導体ダイ(die)上の基板内に形成された少なくとも1つのビア内部に少なくとも1つのアクティブ回路(active circuit)を備える半導体ダイ。
[C2]
前記第1半導体ダイは、別の半導体ダイと共に積層され、
前記アクティブ回路は、前記積層されたダイのアクティブレイヤ(active layer)間に位置される、C1の半導体ダイ。
[C3]
前記アクティブ回路は、前記積層された半導体ダイの両方からI/Oパッドに結合される、C2の半導体ダイ。
[C4]
前記アクティブ回路は、静電気放電(ESD)保護デバイスの一部である、C1の半導体ダイ。
[C5]
前記ESD保護デバイスは、静電気放電を安全に消散(dissipate)させるのに十分な面積を有するP/N接合を含む、C4の半導体ダイ。
[C6]
互いに積層された第1及び第2半導体ダイ(die)と、
前記第1及び第2半導体ダイのアクティブレイヤ(active layer)間に実質的に延びるように形成された少なくとも1つのシリコン貫通ビア(TSV:through silicon via)と、
前記少なくとも1つのシリコン貫通ビア内部に少なくとも部分的に形成されたアクティブ回路(active circuitry)と
を備える3−D積層型半導体デバイス。
[C7]
前記アクティブ回路は、半導体デバイスを備える、C6のデバイス。
[C8]
前記アクティブ回路は、少なくとも1つの静電気放電(ESD)保護デバイスを備える、C6のデバイス。
[C9]
前記アクティブ回路は、P/N接合デバイスを備える、C6のデバイス。
[C10]
前記アクティブ回路は、両方の前記半導体ダイ内に形成される、C6のデバイス。
[C11]
半導体デバイスを形成する方法であって、前記方法は、
少なくとも1つのアクティブ回路(active circuit)を含む少なくとも1つのシリコン貫通ビア(TSV:through silicon via)、を内部に有する第1半導体ダイ(die)を形成することと、
前記第1半導体ダイと第2半導体ダイのアクティブレイヤ(active layer)間に前記シリコン貫通ビアが延びるように、前記第1半導体ダイを前記第2半導体ダイと積層することと
を備える方法。
[C12]
前記第1半導体ダイ内に形成された回路を、前記少なくとも1つのアクティブ回路に結合すること
を更に備えるC11の方法。
[C13]
前記第2半導体ダイ内に形成された回路を、前記少なくとも1つのアクティブ回路に結合すること
を更に備えるC12の方法。
[C14]
前記第2半導体ダイからの結合は、前記第1半導体ダイからの結合に付加的である、C13の方法。
[C15]
前記アクティブ回路は、静電気放電(ESD)保護回路を備える、C11の方法。
[C16]
前記ESD保護回路は、ダイオードを備える、C15の方法。
[C17]
積層型半導体デバイスにおける静電気放電保護方法であって、前記方法は、
前記半導体デバイスの1つの半導体ダイの一部分から、隣接する半導体ダイの一部分に、シリコン貫通ビア(TSV:through silicon via)を結合すること、を備え、
前記結合することは、少なくとも1つの前記半導体ダイから、前記TSVの少なくとも1つの内部に少なくとも部分的に形成された静電気放電(ESD)保護回路に、I/Oパッドを結合すること、を備える方法。
[C18]
第2の前記半導体ダイから、前記ESD保護回路に、I/Oパッドを結合すること、を更に備えるC17の方法。
[C19]
前記ESD保護回路は、ダイオードを備える、C18の方法。
[C20]
互いに平行な関係で配置された第1及び第2半導体ダイと、
前記配置されたダイのアクティブレイヤ(active layer)を結合する手段と
を備え、前記結合する手段は、アクティブ素子(能動素子:active elements)を含む、積層型半導体デバイス。
[C21]
前記形成する手段は、そこに前記アクティブ素子を含む少なくとも1つのシリコン貫通ビア(TSV:through silicon via)を備える、C20のデバイス。
[C22]
前記アクティブ素子は、前記半導体ダイのいずれかで生じる静電気放電を安全に消散(dissipate)させるのに十分な面積を有する、C21のデバイス。
Claims (14)
- 半導体デバイスであって、
半導体基板およびアクティブレイヤを備える第1の半導体ダイと、
半導体基板およびアクティブレイヤを備える第2の半導体ダイと、前記第1の半導体ダイおよび前記第2の半導体ダイは、前記第1の半導体ダイの前記半導体基板が前記第2の半導体ダイの前記アクティブレイヤに隣接するように電気的に結合され、
前記第1の半導体ダイの前記半導体基板内に形成された少なくとも1つのビア内部の少なくとも1つのアクティブ回路と、前記少なくとも1つのビアは、前記第2の半導体ダイと前記第1の半導体ダイの前記アクティブレイヤの間に配設され、前記少なくとも1つのビアは、前記第2の半導体ダイと、前記第1の半導体ダイの前記アクティブレイヤとに電気的に結合され、
を備え、
前記少なくとも1つのアクティブ回路は、静電気放電(ESD)保護デバイスを備え、前記ESD保護デバイスは、前記第1の半導体ダイの前記アクティブレイヤ内に形成された回路、および前記第2の半導体ダイの前記アクティブレイヤ内に形成された回路を、ESDイベントから保護するように構成される、半導体デバイス。 - 前記少なくとも1つのアクティブ回路は、前記第1の半導体ダイおよび前記第2の半導体ダイのうちの少なくとも1つからの入力/出力(I/O)パッドに結合される、請求項1の半導体デバイス。
- 前記少なくとも1つのアクティブ回路は、前記第1の半導体ダイと前記第2の半導体ダイの両方のビア内に形成される、請求項1の半導体デバイス。
- 前記少なくとも1つのアクティブ回路は、前記第2の半導体ダイ内に形成された回路に結合される、請求項1の半導体デバイス。
- 前記少なくとも1つのアクティブ回路はダイオードを備える、請求項1の半導体デバイス。
- 前記少なくとも1つのアクティブ回路は、前記第1の半導体ダイ内に形成された回路に結合される、請求項1の半導体デバイス。
- 前記ESD保護デバイスは、静電気放電を消散(dissipate)するように動作可能な所定の面積を有するP/N接合を備える、請求項1の半導体デバイス。
- 前記第1の半導体ダイおよび前記第2の半導体ダイのうちの少なくとも1つからの入力/出力(I/O)パッドは、前記ESD保護デバイスに結合される、請求項1の半導体デバイス。
- 半導体デバイスを形成するための方法であって、前記方法は、
半導体基板およびアクティブレイヤを備える第1の半導体ダイを設けることと、前記第1の半導体ダイの前記半導体基板を設けることは、少なくとも1つのアクティブ回路を備える少なくとも1つの基板貫通ビア(through substrate via)を設けることを含み、
半導体基板およびアクティブレイヤを備える第2の半導体ダイを設けることと、
前記第1の半導体ダイの前記半導体基板が前記第2の半導体ダイの前記アクティブレイヤに隣接するように、前記第1の半導体ダイを前記第2の半導体ダイと結合することと、前記少なくとも1つの基板貫通ビアは、前記第2の半導体ダイの前記アクティブレイヤと前記第1の半導体ダイの前記アクティブレイヤとの間に延び、前記第2の半導体ダイの前記アクティブレイヤを前記第1の半導体ダイの前記アクティブレイヤに電気的に結合し、
前記第1の半導体ダイ内に形成された回路を、前記少なくとも1つのアクティブ回路に結合することと
を備え、
前記少なくとも1つのアクティブ回路は、静電気放電(ESD)保護デバイスを備え、前記ESD保護デバイスは、前記第1の半導体ダイの前記アクティブレイヤ内に形成された回路、および前記第2の半導体ダイの前記アクティブレイヤ内に形成された回路を、ESDイベントから保護するように構成される、方法。 - 前記少なくとも1つのアクティブ回路は、ダイオードを備える、請求項9の方法。
- 前記第2の半導体ダイ内に形成された回路を、前記少なくとも1つのアクティブ回路に結合することをさらに備える、請求項9の方法。
- 積層型半導体デバイスであって、
半導体基板およびアクティブレイヤを備える第1の半導体ダイと、
半導体基板およびアクティブレイヤを備える第2の半導体ダイと、前記第1の半導体ダイおよび前記第2の半導体ダイは、前記第1の半導体ダイの前記半導体基板が前記第2の半導体ダイの前記アクティブレイヤに隣接するように電気的に結合され、
前記第1の半導体ダイの前記半導体基板内に形成された少なくとも1つのビア内部の電圧を放電するための手段と、前記少なくとも1つのビアは、前記第2の半導体ダイの前記アクティブレイヤと前記第1の半導体ダイの前記アクティブレイヤの間に配設され、前記第2の半導体ダイの前記アクティブレイヤと前記第1の半導体ダイの前記アクティブレイヤとに電気的に結合され、
を備え、
前記電圧を放電するための手段は、静電気放電(ESD)保護デバイスを備え、前記ESD保護デバイスは、前記第1の半導体ダイの前記アクティブレイヤ内に形成された回路、および前記第2の半導体ダイの前記アクティブレイヤ内に形成された回路を、ESDイベントから保護するように構成される、積層型半導体デバイス。 - 前記ESD保護デバイスは、前記半導体ダイのうちのいずれかで生じる静電気放電を安全に消散させるのに十分な面積を有する、請求項12の積層型半導体デバイス。
- 半導体デバイスであって、
第1の半導体ダイの半導体基板内の少なくとも1つのビア内部の少なくとも1つのアクティブ回路、前記少なくとも1つのビアは、前記第1の半導体ダイの前記半導体基板に隣接した第2の半導体ダイのアクティブレイヤと、前記第1の半導体ダイのアクティブレイヤとの間に配設され、かつ、前記第2の半導体ダイの前記アクティブレイヤと前記第1の半導体ダイの前記アクティブレイヤとに電気的に結合され、
を備え、
前記少なくとも1つのアクティブ回路は、静電気放電(ESD)保護デバイスを備え、前記ESD保護デバイスは、前記第1の半導体ダイの前記アクティブレイヤ内に形成された回路、および前記第2の半導体ダイの前記アクティブレイヤ内に形成された回路を、ESDイベントから保護するように構成される、半導体デバイス。
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