TWI406342B - 具有非阻焊限定型防焊層之半導體封裝及其製造方法 - Google Patents

具有非阻焊限定型防焊層之半導體封裝及其製造方法 Download PDF

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TWI406342B
TWI406342B TW099113894A TW99113894A TWI406342B TW I406342 B TWI406342 B TW I406342B TW 099113894 A TW099113894 A TW 099113894A TW 99113894 A TW99113894 A TW 99113894A TW I406342 B TWI406342 B TW I406342B
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Taiwan
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solder
metal ball
solder paste
semiconductor package
metal
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TW099113894A
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English (en)
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TW201104767A (en
Inventor
Seong Bo Shim
Young Jae Lee
Sung Wuk Ryu
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Lg Innotek Co Ltd
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Publication of TW201104767A publication Critical patent/TW201104767A/zh
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Description

具有非阻焊限定型防焊層之半導體封裝及其製造方法
本發明主張關於2009年4月30日所申請的南韓專利案號10-2009-0038392的優先權，並在此以引用的方式併入本文中，以作為參考。
本發明是有關於一種半導體封裝的製造方法，其能克服在印刷電路板(Printed Circuit Board，PCB)的覆晶裝設方法(flip chip mounting method)中之焊上墊(solder-on-pad，SOP)技術問題，且特別是有關於一種藉由形成於走線(trace)上之非阻焊限定型(Non Solder Mask Defined，NSMD)結構或阻焊限定型(Solder Mask Defined，SMD)結構內的防焊開口，而能大幅增加基板電路密度之製程，以直接在防焊層(solder mask)上印刷(print)焊膏(solder paste)，並能防止凸塊架橋(bump bridge)的產生，適合精細圖案(fine pattern)。
隨著電子產業的迅速發展，其著重於微型化(miniaturization)、多功能(multi-function)、高效能(high performance)、高集成度(high integration)以及大體積，特別是在半導體晶片方面，封裝技術已增加其本身的重要性而成為一種能最終決定電子系統之電性效能(electrical performance)、可靠度(reliability)、生產率(productivity)以及微型化的核心技術。封裝技術定義出一系列的流程，其能使最後在晶圓製程中製造完成的每一個晶片能被銷售。
近來，為了增加每單位體積的裝設效率(Mounting efficiency)，多種封裝技術已問世，例如球柵陣列(Ball Grid Array，BGA)、晶片尺寸封裝(Chip Size Package，CSP)以及多晶片模組(Multi Chip Module，MCM)半導體封裝結構，其中透過二個或多個晶片結合於單一封裝結構中，二個或多個晶片通常會配置於共用基板上的一多晶片模組(multi-chip module)的半導體封裝中。
最近，用於保護半導體元件免於外部環境傷害的封裝技術，其為了因應電子裝置(electronic device)微型化與高集成度之發展趨勢，而要求製造出的產品需輕薄短小、速率高、多功能、效能高以及高密度裝設。
依據以上這些產品要求，已出現一種能將從晶圓(wafer)而得的裸晶(bare chip)直接結合在基板上的覆晶裝設技術。亦即，以覆晶接合(flip chip bonding，FCB)為基礎的封裝被認為是其中一種典型的晶片尺寸封裝(chip size package)，其中半導體晶片不需要使用打線(wire)，即能電性連接於印刷電路板(Printed Circuit Board，PCB)，因此相較於具有打線的封裝，在外型上可以縮小，且因為晶片本身被當作成包圍體(enclosure)，所以包圍體的尺寸與晶片的尺寸相等，而得以降低尺寸大小。
在覆晶接合封裝中，形成一液態底部填充層(underfill layer)，以確保黏著力(cohering power)足夠應付貼附在半導體晶片接墊上的焊料凸塊(solder bump)高度，進而強化接合效果以及熱傳輸能力(heat transmission capacity)，同時防止熱應力。以覆晶接合為基礎的封裝能縮短半導體晶片與連接接墊(connection pad)之間的連接距離，而有利於電氣特性(electrical properties)。此外，由於焊球的自我對準效應(self-alignment effect)有利於微型化與薄型化，所以接合方法會變的簡單。另外還有一個優點：由於輸入與輸出端子(terminal)配置在晶片底下，所以訊號的傳輸速率大約比傳統打線方法的封裝快20倍。
現在，請參閱圖1與圖2，其說明一種根據焊上墊(SOP)流程，並透過傳統封裝技術，將一晶片經由焊料而裝設在接墊上的封裝製程，其中圖1是傳統焊上墊製程的流程圖，圖2是圖1中詳細的製程示意圖，而圖3是說明在圖2的步驟S3中發生問題時的放大示意圖。
首先，載入一已形成並具有阻焊限定型凸塊接墊的基板(步驟S1)。在這個步驟S1中，形成一防焊層20在一絕緣基板10，其中防焊層20是以阻焊限定型結構而形成，並且覆蓋接墊30的預定外部位(external portion)。部分接墊30可以形成於連接貫孔(via) 40的結構，而貫孔40貫穿絕緣基板10。
接續地，在步驟S2中，防焊層20的上表面上形成一金屬遮罩(metal mask)50，而金屬遮罩50能做為一種用於印刷焊膏(solder paste)60的遮罩圖案(mask pattern)。上述印刷的方法可以是刻板印花法(stencil printing method)或其相似的方法。
在步驟S3中，金屬遮罩50是透過剝離(exfoliation)而移除。印刷焊膏，步驟進展至回焊(reflow)製程(步驟S4)以進行壓印製程(coining process，即步驟S5)，以及黏合半導體晶圓80之步驟S6。半導體晶圓80與焊膏60的上表面之間的黏合物是藉由形成在半導體晶圓80底面之部分的晶片凸塊90而形成，其中被黏合的半導體晶圓可以透過回焊製程(步驟S7)而穩固裝設(步驟S8)。
然而，傳統的焊上墊(SOP)製程卻遭遇到缺點，其起因於傳統的焊上墊製程本身在製造步驟S2中不能應用於凸塊間距(bump pitch)過小的製程，其中焊膏是印刷在金屬遮罩上。關於以上缺點的詳細說明，以下將配合圖3來敘述。
隨著凸塊間距變的越小越窄，金屬遮罩的厚度及材質與焊膏的厚度扮演著重要的變數。亦即換句話說，如圖3所示，在金屬遮罩50形成在防焊層20的上表面之情況下中，塗上焊膏60、進行步驟S3中剝離金屬遮罩的製程。在移除金屬遮罩後，會有焊料留在一些的小區域中，其將造成焊膏60隨著金屬遮罩剝離而破碎(crumble)，進而堆積焊料61於焊膏圖案的間隙表面(gap surface)上，繼而使相鄰的焊膏連結造成凸塊架橋B而導致在產品的不良率(defect rate)上出現重大缺點。
上述缺點在凸塊間距小於140微米(μm)會更加惡化，而且在精細間距(fine pitch)的環境下，使用金屬遮罩的焊上墊技術會使問題如滾雪球般的加大。
此外，隨著間距的窄縮，金屬遮罩的製程成本以及處理細微顆粒(finer particle)之焊膏的所需材料之價格會使焊上墊技術的缺點以指數方式(exponentially)增加。
本發明的構想是要解決上述問題，並且提供一種半導體封裝的製造方法，其藉由走線上的非阻焊限定型或阻焊限定型結構，以直接在防焊層上印刷一焊膏，而能大幅增加基板的電路密度，並且適用於精細圖案，以防止凸塊架橋的產生。
根據本發明的一考量面，本發明提出一種半導體封裝的製造方法，包括：在一絕緣基板上形成一具有一開口之一防焊層的一第一步驟；以及在防焊層上穩固黏合一焊膏與一金屬球，以將晶片裝設在其中的一第二步驟。
在本發明的一些實施例中，第一步驟包括：(a)在絕緣基板上形成一走線；以及(b)形成具有一個或多個開口的防焊層，其中走線的相鄰基板的表面被暴露。
在本發明的一些實施例中，第二步驟包括：(c)在防焊層上印刷焊膏；(d)在開口的焊膏之表面上黏合一金屬球；(d)在開口的焊膏之表面上黏合一金屬球；以及(e)在金屬球上黏合一晶圓級的晶片。
使用於穩固黏合的金屬球以及在製造方法中黏合的金屬球可以是選自於由銅、鎳、錫、鋁、金、氮化鈦、銦或其他由這些金屬的一種或多種結合而成的合金所構成的一群組，其中穩固黏合的手段為透過回焊接續黏合後的金屬球來達成。
金屬球的材料由複合層(composite layer)所構成，其具有一核心，而核心的詳細介紹在於核心是由金屬或塑膠所製成，而外圍包覆核心的部分是選自於由銅、鎳、錫、鋁、金、氮化鈦、鉛或銦所構成之一群組而形成的單一或多層膜層，且金屬球可以透過回焊製程而被結合。
金屬球可以淺薄地進行有機材料塗覆(organic material coating)或金屬電鍍(metal plating)的表面處理(surface treatment)，其中有機材料是有機保焊劑(Organic Solder Preservation，OSP)塗層，而金屬電鍍可以採用金、錫、鎳、鉛、銀、銦或其他由這些金屬的一種或多種結合而成的合金所構成的一群組來實現。
透過以上的方法，半導體封裝製造包括以下步驟：一防焊層設置有一開口，其中絕緣基板上之走線的相鄰基板之表面被暴露，且焊膏填入開口；以及一金屬球連接於焊膏以及一晶圓級的一晶片之一晶片凸塊，其中金屬球的直徑介於20微米~200微米之間。依據金屬球的一凸塊間距介於50微米~200微米之間。
其中一有利的功效在於：藉由將焊膏直接印刷在走線上已形成防焊層開口的防焊層上，基板的電路密度故能大幅增加，並且因為沒有凸塊架橋的存在，所以能應用於少於100微米的精細凸塊間距。
另一有利的功效在於：透過使用金屬球來作為基板與晶片之間的內連線媒介，能解決習知凸塊裂縫的問題，因而達到物理光學與電性上的優異性能。
又一有利的功效在於：高間隙高度能達到強化可靠度的功效，且能減少組裝中未填滿(underfill)以及助焊劑去除程序(flux removing processes)的缺點。
實施例之具有非阻焊限定型防焊層的半導體封裝以及其製造方法之詳細描述將參照所附之圖式來進行詳細的說明，其中整篇發明內容中的相似元件符號會參照相似元件，並且省略對這些元件所作的多餘說明。在以下實施例的描述中，可以了解，當提及：一元件(element)或一膜層(film)是位在另一元件或膜層”上(on)”；或是”連接於(connected to)”或”耦接於(coupled to)”另一元件或膜層時，表示元件或膜層是直接位在其他元件或膜層上；或是，連接或耦接於其他元件或膜層；或者，可以是位在元件或膜層之間。
在此表示的基板指的是含括所有能在電子元件(electronic element)之間傳遞電訊號(electrical signal)的基板之概念。舉例而言，本發明的基板可適用於所有使用覆晶的產品群，例如硬式基板(rigid substrate)、軟式基板(flex substrate)、LCTT基板、單面(single surface)/多面(multi-surface)/多層(multilayer)基板以及半導體封裝基板(例如：球柵陣列(BGA)、細間距球柵陣列(Fine pitch BGA，FBGA)、帶式球柵陣列(Tape BGA，TBGA)、晶片尺寸封裝以及其他相似的基板)。以下將以覆晶半導體封裝基板作為舉例說明。
為了釐清目的，與本發明相關之技術領域中的已知技術材料不會進行詳細的描述，以使本發明不會有不必要的混淆。因此，用語(term)與片語(phrase)應由整個專利說明書的內容為基礎來定義。
圖4是一種本發明一實施例之半導體封裝製程的流程圖。
本發明適用於各種類型之基板內的一電路圖案，例如阻焊限定型類型(SMD)或非阻焊限定型類型(NSMD)。本實施例的內容集中於非阻焊限定型類型。
在本實施例的非阻焊限定型類型中，最適合於實施製程中依序在防焊層形成一開口(opening)，以使一走線(trace)與該走線周圍的基板能被暴露出來，一焊膏覆蓋在防焊層的開口上，一金屬球被黏合以及一晶片被裝設。
請參閱圖5，根據本發明的一種製程將將被更進一步地詳細說明。
本發明的半導體封裝製程包括：在一絕緣基板(步驟P1)上形成一非阻焊限定型防焊層；在防焊層上穩固黏合一焊膏與一金屬球；以及裝設一晶片(步驟P2~P4)。
步驟P1是在一絕緣基板110上形成非阻焊限定型的一防焊層120，更具體而言，在絕緣基板110上最好設計出一走線130區域，以及一防焊層120具有至少一個或多個開口區域(opening area)OP，透過該些區域以暴露出走線130區域的鄰近基板之表面，其中非阻焊限定型類型涉及一種當中有一開口區域OP形成在防焊層上的結構，以使一走線與該走線周圍的一基板被暴露出來。
在步驟P2中，在防焊層120上覆蓋一層焊膏140，以使焊膏140可以填入一個或多個開口區域。
亦即，在沒有金屬遮罩下，直接在防焊層上印刷一層焊膏，而防焊層以非阻焊限定型類型形成在走線上，以增加電路密度以及實現焊膏的印刷製程。
不同於習知的方法，因為是在沒有金屬遮罩下直接在防焊層上進行印刷，所以不會有凸塊架橋產生，進而允許塗上具有大顆粒尺寸的焊膏，藉以能大幅降低製造成本以及獲得穩定的產品品質。還有應注意的是，除了上述直接印刷方法之外，可以貼合一層分離式乾膜(separate dry film)在防焊層上，以更逐漸堆積(accumulate)防焊層。
在後續的步驟P3中，更佳地，在一個或多個開口區域OP內的焊膏140之表面上黏合一金屬球150，並且在步驟P4中，在金屬球150上黏合一晶圓級的半導體晶片160。步驟P3中的金屬球可以是選自於由金、錫、鎳、鉛、銀、銦或其他由這些金屬的一種或多種結合而成的合金所構成的一群組，其中金屬球的外表面可以進行有機材料塗覆(organic material coating)或金屬電鍍(metal plating)的表面處理(surface treatment)，以防止金屬表面的氧化(oxidation)。有機材料可以是有機保焊劑(Organic Solder Preservation，OSP)塗層，而金屬電鍍可以採用金、錫、鎳、鉛、銀與銦來電鍍。
當然，金屬球的黏合可以是藉由額外的回焊或壓印製程來接續進行。特別是，壓印製程為選擇性製程，因此，有鑑於特性變化甚小的金屬球，例如銅球，本發明可以是省略壓印製程來實現。
圖6繪示在圖5中增加壓印的一種步驟。所有圖6中的步驟均與圖5相同，除了壓印金屬球150的上表面的步驟P32是跟隨在步驟P3之後，同時增加二個步驟，其中步驟P31是黏合金屬球之後的回焊製程，而步驟P41是經由黏合一晶片凸塊161與一金屬球150的回焊製程。
在不同的實施例中，金屬球的核心可以是由金屬或塑膠而製成，其中外圍包覆核心的部分是選自於由銅、鎳、錫、鋁、金、氮化鈦、鉛或銦所構成之一群組而形成的單一或多層膜層。
步驟P4定義裝設一晶圓級的半導體晶片160的製程，而更具體而言，金屬球150能適應通過回焊製程，並透過回焊製程而與半導體晶片160的一晶片凸塊161結合而穩固設置。
特別地，在本發明的一實施例中，其中鋼球用來作為金屬球，而銅被用來作為基板與晶片之間的一種內連線(interconnection)材料，以獲得相對高的間隙高度(stand-off height)，藉此，一種在電性與物理性上具備優異特性的可靠結構能更佳穩固。
為了此目的，金屬球最佳的直徑介於20微米~200微米，而金屬球的凸塊間距位在50微米~200微米的範圍內。
亦即，在本發明的此實施例中，其中銅球用來作為金屬球，而經常發生在一般Sn37Pb、或SAC305、SAC305、Sn0.7Cu凸塊中的凸塊裂縫(bump crack)不會產生，進而強化產品的可靠度(reliability)以及在電性觀點上能具備優異的特性。
此外，少量的焊料也可以塗覆在基板以及晶圓凸塊上，解決難以處理的凸塊架橋產生之問題，並能使習知印刷技術達到精細間距小於100微米以及焊上墊技術的凸塊結構。
圖7是根據本發明所繪示的半導體封裝的剖面示意圖。
更具體而言，絕緣基板110具備配置有開口區域OP的一防焊層120，走線130之相鄰基板的一表面從開口區域OP暴露出，焊膏140填入開口區域OP，並且配置連接於焊膏140以及晶圓級之半導體晶片160的晶片凸塊161的一金屬球150。特別地，金屬球最好是銅球，而且如上所述，金屬球可以由各種不同的材料所形成。金屬球的直徑最好是在20微米~200微米之間。
本發明的概念以前述實施例呈現及說明如上，而本發明所屬技術領域中具有通常知識者所作更動與潤飾之等效替換，在不脫離本發明之精神和範圍內，仍為本發明之專利保護範圍內。
「產業利用性」
藉由直接在防焊層上印刷一已在走線上形成防焊層開口之後的焊膏，一基板的一電路密度能而大幅地增加，並且因為沒有凸塊架橋的存在，所以能應用於少於100微米的精細凸塊間距，透過使用金屬球來作為基板與晶片之間的內連線媒介，能解決習知凸塊裂縫的問題，因而達到物理光學與電性上的優異性能，而高間隙高度能達到強化可靠度的功效，且能減少組裝製程中未填滿以及助焊劑去除程序的缺點。
10、110．．．絕緣基板
20、120．．．防焊層
30．．．接墊
40．．．貫孔
50．．．金屬遮罩
60、140．．．焊膏
61．．．焊料
80．．．半導體晶圓
90、161．．．晶片凸塊
130．．．走線
150．．．金屬球
160．．．半導體晶片
B．．．凸塊架橋
OP．．．開口區域
P1~P4、P31、P32、P41、S1~S8．．．步驟
圖1、2與3繪示一流程圖與一示意圖用於說明習知技術中的焊上墊製程以及其缺點。
圖4、5與6說明本發明之一流程圖以及一半導體封裝製程的示意圖。
圖7是本發明之一半導體封裝的剖面示意圖。
10．．．絕緣基板
20．．．防焊層
30．．．接墊
40．．．貫孔
50．．．金屬遮罩
60．．．焊膏
80．．．半導體晶圓
90．．．晶片凸塊
S1~S7．．．步驟

Claims (9)

  1. 一種半導體封裝的製造方法，包括：在一絕緣基板上形成具有一或多個開口之一防焊層；以及在該一或多個開口中黏合一焊膏與一金屬球，以裝設一晶片在其上，其中形成該防焊層之方法，包括：在該絕緣基板上形成一走線；以及形成具有該些開口的該防焊層，其中該走線的一相鄰基板的一表面從該開口暴露出。
  2. 如申請專利範圍第1項所述之半導體封裝的製造方法，其中黏合該焊膏與該金屬球之方法，包括：在該防焊層之該些開口中印刷該焊膏；在該開口中之一開口的該焊膏之一表面上黏合該金屬球；以及在該金屬球上黏合晶圓級的該晶片。
  3. 如申請專利範圍第2項所述之半導體封裝的製造方法，其中印刷該焊膏之方法包括使用一乾膜或直接印刷該焊膏，以在該防焊層之該些開口上形成一焊膏。
  4. 如申請專利範圍第1至3項中的任一項所述之半導體封裝的製造方法，其中黏合該焊膏與該金屬球之方法包括回焊該金屬球，而該金屬球選自於由銅、鎳、錫、鋁、金、氮化鈦、銦其中之一者，或其他由這些金屬 的兩種或多種結合而成的一合金。
  5. 如申請專利範圍第1至3項中的任一項所述之半導體封裝的製造方法，其中黏合該焊膏與該金屬球之方法包括回焊該金屬球，而該金屬球選自於由銅、鎳、錫、鋁、金、氮化鈦、鉛其中之一者，其中該金屬球具有一核心，其是由金屬或塑膠而製成。
  6. 如申請專利範圍第4項所述之半導體封裝的製造方法，其中該金屬球進行一有機材料塗覆或一金屬電鍍的表面處理。
  7. 如申請專利範圍第6項所述之半導體封裝的製造方法，其中該有機材料是用於有機保焊劑塗覆，而該金屬電鍍採用金、錫、鎳、鉛、銀、銦其中之一者，或其他由這些金屬的一種或多種結合而成的合金來實現。
  8. 一種半導體封裝，包括：一防焊層配置有一或多個開口，在一絕緣基板上的一走線之一相鄰基板的一表面從該開口暴露出，而一焊膏填入該一或多個開口；以及一金屬球，連接於該焊膏以及一晶圓級的一晶片之一晶片凸塊，其中該金屬球的直徑是在20微米至200微米之間。
  9. 如申請專利範圍第8項所述之半導體封裝，其中根據該金屬球，一凸塊間距是在50微米至200微米之間。
TW099113894A 2009-04-30 2010-04-30 具有非阻焊限定型防焊層之半導體封裝及其製造方法 TWI406342B (zh)

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9238278B2 (en) * 2011-03-29 2016-01-19 Panasonic Intellectual Property Management Co., Ltd. Solder transfer substrate, manufacturing method of solder transfer substrate, and solder transfer method
DE102012111358A1 (de) * 2012-11-23 2014-05-28 Osram Opto Semiconductors Gmbh Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip
CN105093853B (zh) * 2015-09-02 2017-06-23 广东海圣科技有限公司 自动防焊曝光台框模组及曝光机
KR101800367B1 (ko) * 2016-08-24 2017-11-28 한국기계연구원 마이크로 소자 전사방법 및 마이크로 소자 전사방법으로 제조된 마이크로 소자 기판
KR102094014B1 (ko) 2018-09-20 2020-03-27 주식회사 지엔테크 인쇄회로기판의 솔더링 장치 및 이를 이용한 공정방법

Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200428605A (en) * 2003-06-11 2004-12-16 Phoenix Prec Technology Corp Method for fabricating substrate with plated metal layer over pads thereon
TWI234258B (en) * 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
TW200726353A (en) * 2005-12-20 2007-07-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US20080023829A1 (en) * 2006-07-31 2008-01-31 Promax Technology (Hong Kong) Limited Substrate and process for semiconductor flip chip package

Family Cites Families (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100336575B1 (ko) * 2000-06-28 2002-05-16 박종섭 반도체 패키지의 솔더 볼과 그의 제조 방법
US7377032B2 (en) * 2003-11-21 2008-05-27 Mitsui Mining & Smelting Co., Ltd. Process for producing a printed wiring board for mounting electronic components
TWI375307B (en) * 2007-07-26 2012-10-21 Flip chip package structure and method for manufacturing the same

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
TW200428605A (en) * 2003-06-11 2004-12-16 Phoenix Prec Technology Corp Method for fabricating substrate with plated metal layer over pads thereon
TWI234258B (en) * 2003-08-01 2005-06-11 Advanced Semiconductor Eng Substrate with reinforced structure of contact pad
TW200726353A (en) * 2005-12-20 2007-07-01 Phoenix Prec Technology Corp Structure of circuit board and method for fabricating the same
US20080023829A1 (en) * 2006-07-31 2008-01-31 Promax Technology (Hong Kong) Limited Substrate and process for semiconductor flip chip package

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