WO2010126302A2 - Semiconductor package with nsmd type solder mask and method for manufacturing the same - Google Patents

Semiconductor package with nsmd type solder mask and method for manufacturing the same Download PDF

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Publication number
WO2010126302A2
WO2010126302A2 PCT/KR2010/002683 KR2010002683W WO2010126302A2 WO 2010126302 A2 WO2010126302 A2 WO 2010126302A2 KR 2010002683 W KR2010002683 W KR 2010002683W WO 2010126302 A2 WO2010126302 A2 WO 2010126302A2
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WO
WIPO (PCT)
Prior art keywords
metal ball
solder mask
solder
metal
solder paste
Prior art date
Application number
PCT/KR2010/002683
Other languages
French (fr)
Other versions
WO2010126302A3 (en
Inventor
Seong Bo Shim
Young Jae Lee
Sung Wuk Ryu
Original Assignee
Lg Innotek Co., Ltd.
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Publication date
Application filed by Lg Innotek Co., Ltd. filed Critical Lg Innotek Co., Ltd.
Publication of WO2010126302A2 publication Critical patent/WO2010126302A2/en
Publication of WO2010126302A3 publication Critical patent/WO2010126302A3/en

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Definitions

  • the present invention relates to a method for manufacturing semiconductor package capable of overcoming solder-on-pad (SOP) techniques in the flip chip mounting method of printed circuit board (PCB), and more particularly to a manufacturing process capable of greatly increasing a circuit density of a substrate by forming an opening of a solder mask in an NSMD (Non Solder Mask Defined) structure or an SMD (Solder Mask Defined) structure on a trace to directly print a solder paste on the solder mask, and capable of being applicable to fine patterns by preventing generation of bump bridges.
  • SOP solder-on-pad
  • a packaging technology has increased its importance as a core technology that finally determines electrical performance, reliability, productivity and miniaturization of electronic system.
  • the packaging technology defines a series of processes that finally makes each chip manufactured in a wafer process merchantable.
  • packaging technologies have come up such as a BGA (Ball Grid Array), a CSP (Chip Size Package) and a Multi Chip Module (MCM) semiconductor package structure in which two or more chips are typically disposed in a multi-chip module semiconductor package on a common substrate by combining two or more chips in a single package structure.
  • BGA Bit Grid Array
  • CSP Chip Size Package
  • MCM Multi Chip Module
  • the packaging technology for protecting semiconductor elements from outside environment in response to trends of miniaturization and high integration of electronic devices requires to manufacture products light weight, slimness, compactness, high speed, multi-function, high performance and high density mounting.
  • FCB flip chip bonding
  • a liquid-state underfill layer is formed for stably securing a cohering power in response to a height of solder bump attached to a semiconductor chip pad to enhance the bonding performance and heat transmission capacity while guarding against heat stress.
  • the package based on the FCB facilitates to shorten a connection distance between the semiconductor chip and the connection pad to the advantage of electrical properties. Furthermore, bonding is easy due to self-alignment effect of solder ball to be conducive to miniaturization and slimness.
  • input and output terminals are disposed underneath the chip to allow a transmission speed of a signal approximately 20 times faster than that of conventional package of wire method.
  • FIGS. 1 and 2 that explain a package manufacturing process according to an SOP (Solder On Pad) process mounting a chip on a pad through soldering according to the conventional packaging technique
  • FIG.1 is a process flowchart of the conventional SOP process
  • FIG.2 is a detailed conceptual process drawing of FIG.1
  • FIG.3 is an enlarged view illustrating a problem that occurs in step (S3) of FIG.2.
  • solder Mask Defined bump pad is loaded (S1).
  • a solder mask (20) is formed on an insulation substrate (10), where the solder mask is formed in the SMD structure that covers a predetermined external portion of a pad (30). Part of the pad may be formed in a structure connected to a via (40) that penetrates the substrate.
  • an upper surface of the solder mask (20) is formed with a metal mask (50) which is used as a mask pattern to print a solder paste (60).
  • the printing method may be a stencil printing method or the like.
  • step S3 the metal mask (50) is removed by exfoliation.
  • the solder paste is printed, flow advances to reflow process (S4) to perform a coining process (S5), and a semiconductor wafer (80) is attached (S6).
  • the attachment between the semiconductor wafer and an upper surface of the solder paste is formed by a chip bump portion (90) formed at a bottom surface of the semiconductor wafer, where the attached semiconductor wafer may be stably mounted through the reflow process (S7).
  • the conventional SOP process suffers from a disadvantage in that its incapability of being applied to processes with a bump pitch being smaller in the manufacturing step (S2) in which the solder paste is printed on the metal mask. Detailed explanation about this disadvantage will be made with reference to FIG.3.
  • the thickness and material of the metal mask and the material of the solder paste act as an important variation. That is, as illustrated in FIG.3, in a case when the metal mask (50) is formed on the upper surface pf the solder mask (20), solder paste (60) is coated and a process of exfoliating the metal mask in the Step S3, a solder volume printing is generated at a small region following the removal of the metal mask, which causes the solder paste (60) to crumble following metal mask exfoliation, and to accumulate on a gap surface of the solder paste patterns. This in turn generates a bump bridge (B) of being connected with adjacent solder pastes to result in a fatal drawback of increasing the defect rates of the product.
  • B bump bridge
  • This drawback deteriorates in a bump pitch less than 140 ⁇ m, and is snowballed to a greater problem in the SOP technology using the metal mask under a fine pitch environment.
  • the present invention is conceived to solve the aforementioned problems and is directed to a method for manufacturing semiconductor package capable of greatly increasing a circuit density of a substrate by forming an opening of a solder mask in an NSMD (Non Solder Mask Defined) structure or an SMD (Solder Mask Defined) structure on a trace to directly print a solder paste on the solder mask, and capable of being applicable to fine patterns by preventing generation of bump bridges.
  • NSMD Non Solder Mask Defined
  • SMD solder Mask Defined
  • a method for manufacturing semiconductor package comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon.
  • the first step includes: (a) forming a trace on the insulation substrate; and (b) forming a solder mask having one or more openings where a surface of an adjacent substrate of the trace is exposed.
  • the second step includes: (c) printing solder paste on the solder mask; (d) attaching a metal ball on a surface of the solder paste of the opening; and (e) attaching a chip of wafer level on the metal ball.
  • the metal ball used in the firming adhering and attaching the metal ball in the manufacturing method may be one selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, In, or an alloy combined with two or more metals thereof, wherein the firmly forming may be performed by means of reflow of the metal ball following the attachment.
  • the material of the metal ball is structured in a composite layer having a core therein, the detail of which is that the core is made of a metal or plastic, an outside encompassing the core is formed with a single layer or a multilayer selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, Pb or In, and the metal ball may be bonded by reflow process.
  • the metal ball may be superficially performed with a surface treatment of an organic material coating or a metal plating, where the organic material is for organic solder preservation coating, and the metal plating may be carried out using a metal selected from a group consisting of Au, Sn, Ni, Pb, Ag, In, or an alloy combined with one or more metals thereof.
  • the semiconductor package manufactured by the aforementioned method comprises: a solder mask layer disposed with an opening where a surface of an adjacent substrate of a trace on an insulation substrate is exposed and a solder paste filled in the opening; and a metal ball connecting the solder paste and a chip bump of a chip of a wafer level, where the metal ball is diametrally 20 ⁇ m ⁇ 200 ⁇ m.
  • a bump pitch according to the metal ball is 50 ⁇ m ⁇ 200 ⁇ m.
  • a circuit density of a substrate can be greatly increased by forthright printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100 ⁇ m due to non-existence of bump bridges.
  • Another advantageous effect is that the conventional bump crack can be solved by using a metal ball as an interconnection medium between the substrate and the chip to thereby obtain excellent performances in light of physical and electrical terms.
  • Still another advantageous effect is that a high stand-off height can be obtained to enhance reliability, and defects can be reduced in the underfill and flux removing processes of assembly process.
  • FIGS. 1, 2 and 3 represent a flowchart and a conceptual drawing for illustrating a POP manufacturing process and drawbacks thereof in the prior art.
  • FIGS. 4, 5 and 6 illustrate a flowchart and a process chart of a manufacturing process of semiconductor package according to the present invention.
  • FIG. 7 is a conceptual drawing schematically illustrating a cross-section of a semiconductor package according to the present invention.
  • the substrate herein expressed refers to a concept encompassing all the substrates capable of transmitting an electrical signal between electronic elements.
  • the substrate according to the present invention may be applicable to all product groups using flip chips such as rigid substrates, flex substrates, LCTT substrates, single surface/multi-surface/multilayer substrates, and semiconductor mounting substrates (BGA, FBGA, TBGA, CSP and the like).
  • a flip chip semiconductor package substrate will be exemplified in the following.
  • FIG. 4 is a flowchart of a manufacturing process of semiconductor package according to an exemplary embodiment of the present invention.
  • the present invention is applicable to various types forming a circuit pattern within a substrate, e.g., to SMD (Solder Mask Defined) type or NSMD (Non-Solder Mask Defined) type.
  • SMD Silicon Mask Defined
  • NSMD Non-Solder Mask Defined
  • the present exemplary embodiment will focus on NSMD type.
  • the manufacturing process of semiconductor package according to the present invention comprises: forming a NSMD type solder mask on an insulation substrate (P1); firmly adhering a solder paste and a metal ball on the solder mask; and mounting a chip (P2 ⁇ P4).
  • the P1 step is a step of forming an NSMD type solder mask (120) on an insulation substrate (110), and to be more specific, it is preferable that a trace (130) region be designed on the insulation substrate (110), and a solder mask (120) having at least one or more opening areas (Ops) through which a surface of an adjacent substrate of the trace region (130) be formed, where the NSMD type refers to a structure where an opening area is formed on the solder mask so that a trace and a substrate around the trace are exposed.
  • a solder paste (140) is coated on the solder mask (120) to allow the solder paste (140) to be filled in the opening area (OP).
  • solder paste is forthright printed on a solder mask without a metal mask, and the solder mask is formed on the trace in the NSMD type to increase the density of circuit and a solder paste printing process is carried out.
  • a direct print is carried out on the solder mask without using a metal mask, no bump bridges are generated to allow being applied with a solder paste having a large particle size, whereby manufacturing cost can be greatly reduced and a product of constant quality can be obtained.
  • a separate dry film may be attached on the solder mask to further accumulate the solder mask.
  • a metal ball (150) is attached on a surface of the solder paste (140) of the opening area (OP), and in P4, a chip (160) of wafer level is attached on the metal ball (150).
  • the metal ball in P3 may be one selected from a group consisting of Au, Sn, Ni, Pb, Ag, In, or an alloy combined with one or more metals thereof, where an outer surface of the metal ball may be performed with a surface treatment of an organic material coating or a metal plating to thereby prevent oxidation of the metal surface.
  • the organic material may be OSP (Organic Solder Preservation) coating, and the metal plating may be carried out by using Au, Sn, Ni, Pb, Ag and In plating.
  • the attachment of the metal ball may be followed by reflow or coining process additionally.
  • the coining process is a selective process, such that the present invention may be carried out by omitting the coining process due to characteristic smaller variation of metal ball, particularly Cu ball.
  • FIG. 6 illustrates a process in which a coining is added in the process of FIG. 5. All the processes in FIG. 6 are the same as those in FIG. 5, except that an upper surface of the metal ball (150) is coined following the P3 step, and two steps are added in which P31 is a reflow process after attachment of a metal ball and P41 is a reflow process by bonding a chip bump (161) and a metal ball (150).
  • a core of the metal ball is made of a metal or plastic, where an outside encompassing the core is formed with a single layer or a multilayer selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, Pb or In.
  • P4 step defines a process of mounting a semiconductor chip (160) of wafer level, and to be more specific, the metal ball (150) is accommodated through reflow process, onto which a chip bump (161) of the semiconductor chip (160) is bonded and the mounting is stably carried out through the reflow process.
  • Cu copper
  • a metal ball a copper (Cu) ball
  • Cu is utilized as an interconnection material between a substrate and a chip to thereby obtain a relatively high stand-off height, whereby a reliable structure equipped with electrically and physically excellent characteristics can be secured.
  • the metal ball be diametrally 20 ⁇ m ⁇ 200 ⁇ m, and a bump pitch of the metal ball be within a scope of 50 ⁇ m ⁇ 200 ⁇ m.
  • a bump crack frequently occurring in the conventional Sn37Pb, or SAC305, SAC305, Sn0.7Cu bumps is not generated to enhance reliability of products and enable equipment of an excellent feature in terms of electrical view point.
  • a low solder volume can be applied to a substrate and wafer bumping as well to solve the problematic generation of bump bridges, which enables the conventional printing technology to achieve a bump structure of fine pitch less than 100 ⁇ m and an SOP technology.
  • FIG. 7 is a conceptual drawing schematically illustrating a cross-section of a semiconductor package according to the present invention.
  • an insulation substrate (110) is equipped with a solder mask layer (120) disposed with an opening area (OP) through which a surface of adjacent substrate of a trace (130) is exposed and a solder paste (140) filled in the opening area (OP), and a metal ball (140) connecting the solder paste (140) and a chip bump (161) of a chip (161) of wafer level is disposed.
  • the metal ball is preferably a copper (Cu) ball, and as mentioned above, the metal ball may be formed with various materials. It is preferable that the metal ball be diametrally 20 ⁇ m ⁇ 200 ⁇ m.
  • a circuit density of a substrate can be greatly increased by directly printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100 ⁇ m due to non-existence of bump bridges, the conventional bump crack can be solved by using a metal ball as an inter- connection medium between the substrate and the chip to thereby obtain excellent performances in light of physical and electrical terms, and a high stand-off height can be obtained to enhance reliability, and defects can be reduced in the underfill and flux removing processes of assembly process.

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Abstract

A method for manufacturing semiconductor package comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon, such that a circuit density of a substrate can be greatly increased by directly printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100µm due to non-existence of bump bridges.

Description

SEMICONDUCTOR PACKAGE WITH NSMD TYPE SOLDER MASK AND METHOD FOR MANUFACTURING THE SAME
The present invention relates to a method for manufacturing semiconductor package capable of overcoming solder-on-pad (SOP) techniques in the flip chip mounting method of printed circuit board (PCB), and more particularly to a manufacturing process capable of greatly increasing a circuit density of a substrate by forming an opening of a solder mask in an NSMD (Non Solder Mask Defined) structure or an SMD (Solder Mask Defined) structure on a trace to directly print a solder paste on the solder mask, and capable of being applicable to fine patterns by preventing generation of bump bridges.
Along with rapid development of electronic industries focused on miniaturization, multi-function, high performance, high integration and larger volume, especially in semiconductor chips, a packaging technology has increased its importance as a core technology that finally determines electrical performance, reliability, productivity and miniaturization of electronic system. The packaging technology defines a series of processes that finally makes each chip manufactured in a wafer process merchantable.
Recently, in order to further increase a mounting efficiency per unit volume, packaging technologies have come up such as a BGA (Ball Grid Array), a CSP (Chip Size Package) and a Multi Chip Module (MCM) semiconductor package structure in which two or more chips are typically disposed in a multi-chip module semiconductor package on a common substrate by combining two or more chips in a single package structure.
Recently, the packaging technology for protecting semiconductor elements from outside environment in response to trends of miniaturization and high integration of electronic devices requires to manufacture products light weight, slimness, compactness, high speed, multi-function, high performance and high density mounting.
Concomitant with these requirements, a flip-chip mounting technique directly bonding bare chips obtained from wafers onto a substrate has emerged. That is, a package based on flip chip bonding (FCB) is known as one of the representative chip size packages in which the semiconductor chip is connected to the printed circuit board (PCB) without using wires, hence allowing reduction in profile as compared with the package having wires, and because the chip itself is used as an enclosure, the enclosure size is equal to the chip size, allowing downsizing.
In the FCB package, a liquid-state underfill layer is formed for stably securing a cohering power in response to a height of solder bump attached to a semiconductor chip pad to enhance the bonding performance and heat transmission capacity while guarding against heat stress. The package based on the FCB facilitates to shorten a connection distance between the semiconductor chip and the connection pad to the advantage of electrical properties. Furthermore, bonding is easy due to self-alignment effect of solder ball to be conducive to miniaturization and slimness. There is another advantage in that input and output terminals are disposed underneath the chip to allow a transmission speed of a signal approximately 20 times faster than that of conventional package of wire method.
Now, referring to FIGS. 1 and 2 that explain a package manufacturing process according to an SOP (Solder On Pad) process mounting a chip on a pad through soldering according to the conventional packaging technique, where FIG.1 is a process flowchart of the conventional SOP process and FIG.2 is a detailed conceptual process drawing of FIG.1, FIG.3 is an enlarged view illustrating a problem that occurs in step (S3) of FIG.2.
First, a substrate formed with SMD (Solder Mask Defined) bump pad is loaded (S1). In this step, a solder mask (20) is formed on an insulation substrate (10), where the solder mask is formed in the SMD structure that covers a predetermined external portion of a pad (30). Part of the pad may be formed in a structure connected to a via (40) that penetrates the substrate.
Successively, in step S2, an upper surface of the solder mask (20) is formed with a metal mask (50) which is used as a mask pattern to print a solder paste (60). The printing method may be a stencil printing method or the like.
In step S3, the metal mask (50) is removed by exfoliation. The solder paste is printed, flow advances to reflow process (S4) to perform a coining process (S5), and a semiconductor wafer (80) is attached (S6). The attachment between the semiconductor wafer and an upper surface of the solder paste is formed by a chip bump portion (90) formed at a bottom surface of the semiconductor wafer, where the attached semiconductor wafer may be stably mounted through the reflow process (S7).
However, the conventional SOP process suffers from a disadvantage in that its incapability of being applied to processes with a bump pitch being smaller in the manufacturing step (S2) in which the solder paste is printed on the metal mask. Detailed explanation about this disadvantage will be made with reference to FIG.3.
As the bump pitch becomes smaller and narrower, the thickness and material of the metal mask and the material of the solder paste act as an important variation. That is, as illustrated in FIG.3, in a case when the metal mask (50) is formed on the upper surface pf the solder mask (20), solder paste (60) is coated and a process of exfoliating the metal mask in the Step S3, a solder volume printing is generated at a small region following the removal of the metal mask, which causes the solder paste (60) to crumble following metal mask exfoliation, and to accumulate on a gap surface of the solder paste patterns. This in turn generates a bump bridge (B) of being connected with adjacent solder pastes to result in a fatal drawback of increasing the defect rates of the product.
This drawback deteriorates in a bump pitch less than 140μm, and is snowballed to a greater problem in the SOP technology using the metal mask under a fine pitch environment.
Furthermore, as the pitch is narrowed, processing cost of metal mask and price of solder paste requiring materials disposed with finer particles increase exponentially to the disadvantage of the SOP technology.
The present invention is conceived to solve the aforementioned problems and is directed to a method for manufacturing semiconductor package capable of greatly increasing a circuit density of a substrate by forming an opening of a solder mask in an NSMD (Non Solder Mask Defined) structure or an SMD (Solder Mask Defined) structure on a trace to directly print a solder paste on the solder mask, and capable of being applicable to fine patterns by preventing generation of bump bridges.
According to one general aspect of the present invention, there is provided a method for manufacturing semiconductor package, comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon.
In some exemplary embodiment of the present invention, the first step includes: (a) forming a trace on the insulation substrate; and (b) forming a solder mask having one or more openings where a surface of an adjacent substrate of the trace is exposed.
In some exemplary embodiment of the present invention, the second step includes: (c) printing solder paste on the solder mask; (d) attaching a metal ball on a surface of the solder paste of the opening; and (e) attaching a chip of wafer level on the metal ball.
The metal ball used in the firming adhering and attaching the metal ball in the manufacturing method may be one selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, In, or an alloy combined with two or more metals thereof, wherein the firmly forming may be performed by means of reflow of the metal ball following the attachment.
The material of the metal ball is structured in a composite layer having a core therein, the detail of which is that the core is made of a metal or plastic, an outside encompassing the core is formed with a single layer or a multilayer selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, Pb or In, and the metal ball may be bonded by reflow process.
The metal ball may be superficially performed with a surface treatment of an organic material coating or a metal plating, where the organic material is for organic solder preservation coating, and the metal plating may be carried out using a metal selected from a group consisting of Au, Sn, Ni, Pb, Ag, In, or an alloy combined with one or more metals thereof.
The semiconductor package manufactured by the aforementioned method comprises: a solder mask layer disposed with an opening where a surface of an adjacent substrate of a trace on an insulation substrate is exposed and a solder paste filled in the opening; and a metal ball connecting the solder paste and a chip bump of a chip of a wafer level, where the metal ball is diametrally 20μm~200μm. A bump pitch according to the metal ball is 50μm~200μm.
One of the advantageous effects is that a circuit density of a substrate can be greatly increased by forthright printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100μm due to non-existence of bump bridges.
Another advantageous effect is that the conventional bump crack can be solved by using a metal ball as an interconnection medium between the substrate and the chip to thereby obtain excellent performances in light of physical and electrical terms.
Still another advantageous effect is that a high stand-off height can be obtained to enhance reliability, and defects can be reduced in the underfill and flux removing processes of assembly process.
FIGS. 1, 2 and 3 represent a flowchart and a conceptual drawing for illustrating a POP manufacturing process and drawbacks thereof in the prior art.
FIGS. 4, 5 and 6 illustrate a flowchart and a process chart of a manufacturing process of semiconductor package according to the present invention.
FIG. 7 is a conceptual drawing schematically illustrating a cross-section of a semiconductor package according to the present invention.
A detailed description of exemplary embodiments of semiconductor package with NSMD type solder mask and method for manufacturing the same will be described in detail with reference to the accompanying drawings, wherein like reference numerals refer to the like elements throughout and redundant explanation thereto will be omitted. It will be understood that when an element or layer is referred to as being "on", "connected to" or "coupled to" another element or layer, it can be directly on, connected or coupled to the other element or layer or intervening elements or layers may be present.
The substrate herein expressed refers to a concept encompassing all the substrates capable of transmitting an electrical signal between electronic elements. For example, the substrate according to the present invention may be applicable to all product groups using flip chips such as rigid substrates, flex substrates, LCTT substrates, single surface/multi-surface/multilayer substrates, and semiconductor mounting substrates (BGA, FBGA, TBGA, CSP and the like). A flip chip semiconductor package substrate will be exemplified in the following.
For the purpose of clarity, technical material that is known in the technical fields related to the present invention has not been described in detail so that the invention is not unnecessarily obscured. The terms and phrases therefore should be defined based on the content across an entire specification.
FIG. 4 is a flowchart of a manufacturing process of semiconductor package according to an exemplary embodiment of the present invention.
The present invention is applicable to various types forming a circuit pattern within a substrate, e.g., to SMD (Solder Mask Defined) type or NSMD (Non-Solder Mask Defined) type. The present exemplary embodiment will focus on NSMD type.
In the present exemplary embodiment of MSMD type, it is preferable that processes be carried out in the order of a solder mask being formed on an opening so that a trace and a substrate around the trace can be exposed, a solder paste being coated on the opening of the solder mask, a metal ball being attached and a chip being mounted.
Referring to FIG. 5, a manufacturing process according to the present invention will be further explained in detail.
The manufacturing process of semiconductor package according to the present invention comprises: forming a NSMD type solder mask on an insulation substrate (P1); firmly adhering a solder paste and a metal ball on the solder mask; and mounting a chip (P2~P4).
The P1 step is a step of forming an NSMD type solder mask (120) on an insulation substrate (110), and to be more specific, it is preferable that a trace (130) region be designed on the insulation substrate (110), and a solder mask (120) having at least one or more opening areas (Ops) through which a surface of an adjacent substrate of the trace region (130) be formed, where the NSMD type refers to a structure where an opening area is formed on the solder mask so that a trace and a substrate around the trace are exposed.
In P2 step, a solder paste (140) is coated on the solder mask (120) to allow the solder paste (140) to be filled in the opening area (OP).
That is, a solder paste is forthright printed on a solder mask without a metal mask, and the solder mask is formed on the trace in the NSMD type to increase the density of circuit and a solder paste printing process is carried out.
Unlike the conventional method, because a direct print is carried out on the solder mask without using a metal mask, no bump bridges are generated to allow being applied with a solder paste having a large particle size, whereby manufacturing cost can be greatly reduced and a product of constant quality can be obtained. It should be also noted that, in addition to the direct printing method, a separate dry film may be attached on the solder mask to further accumulate the solder mask.
In the subsequent step of P3, preferably, a metal ball (150) is attached on a surface of the solder paste (140) of the opening area (OP), and in P4, a chip (160) of wafer level is attached on the metal ball (150). The metal ball in P3 may be one selected from a group consisting of Au, Sn, Ni, Pb, Ag, In, or an alloy combined with one or more metals thereof, where an outer surface of the metal ball may be performed with a surface treatment of an organic material coating or a metal plating to thereby prevent oxidation of the metal surface. The organic material may be OSP (Organic Solder Preservation) coating, and the metal plating may be carried out by using Au, Sn, Ni, Pb, Ag and In plating.
Of course, the attachment of the metal ball may be followed by reflow or coining process additionally. Particularly, the coining process is a selective process, such that the present invention may be carried out by omitting the coining process due to characteristic smaller variation of metal ball, particularly Cu ball.
FIG. 6 illustrates a process in which a coining is added in the process of FIG. 5. All the processes in FIG. 6 are the same as those in FIG. 5, except that an upper surface of the metal ball (150) is coined following the P3 step, and two steps are added in which P31 is a reflow process after attachment of a metal ball and P41 is a reflow process by bonding a chip bump (161) and a metal ball (150).
In a separate exemplary embodiment, a core of the metal ball is made of a metal or plastic, where an outside encompassing the core is formed with a single layer or a multilayer selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, Pb or In.
P4 step defines a process of mounting a semiconductor chip (160) of wafer level, and to be more specific, the metal ball (150) is accommodated through reflow process, onto which a chip bump (161) of the semiconductor chip (160) is bonded and the mounting is stably carried out through the reflow process.
Particularly, in an exemplary embodiment of the present invention where a copper (Cu) ball is used as a metal ball, Cu is utilized as an interconnection material between a substrate and a chip to thereby obtain a relatively high stand-off height, whereby a reliable structure equipped with electrically and physically excellent characteristics can be secured.
To this end, it is preferable that the metal ball be diametrally 20 μm~200μm, and a bump pitch of the metal ball be within a scope of 50μm~200 μm.
That is, in the exemplary embodiment of the present invention where a copper (Cu) ball is used as a metal ball, a bump crack frequently occurring in the conventional Sn37Pb, or SAC305, SAC305, Sn0.7Cu bumps is not generated to enhance reliability of products and enable equipment of an excellent feature in terms of electrical view point.
Furthermore, a low solder volume can be applied to a substrate and wafer bumping as well to solve the problematic generation of bump bridges, which enables the conventional printing technology to achieve a bump structure of fine pitch less than 100μm and an SOP technology.
FIG. 7 is a conceptual drawing schematically illustrating a cross-section of a semiconductor package according to the present invention.
To be more specific, an insulation substrate (110) is equipped with a solder mask layer (120) disposed with an opening area (OP) through which a surface of adjacent substrate of a trace (130) is exposed and a solder paste (140) filled in the opening area (OP), and a metal ball (140) connecting the solder paste (140) and a chip bump (161) of a chip (161) of wafer level is disposed. Particularly, the metal ball is preferably a copper (Cu) ball, and as mentioned above, the metal ball may be formed with various materials. It is preferable that the metal ball be diametrally 20μm~200μm.
While the present inventive concept has been particularly shown and described with reference to exemplary embodiments thereof, it will be understood by those of ordinary skill in the art that various changes in form and details may be made therein without departing from the spirit and scope of the present inventive concept as defined by the following claims.
A circuit density of a substrate can be greatly increased by directly printing a solder paste on a solder mask following formation of an opening of the solder mask on a trace and can be applied to a fine bump pitch of less than 100μm due to non-existence of bump bridges, the conventional bump crack can be solved by using a metal ball as an inter- connection medium between the substrate and the chip to thereby obtain excellent performances in light of physical and electrical terms, and a high stand-off height can be obtained to enhance reliability, and defects can be reduced in the underfill and flux removing processes of assembly process.

Claims (10)

  1. A method for manufacturing semiconductor package, comprising: a first step of forming a solder mask formed with an opening on an insulation substrate; and a second step of firmly adhering a solder paste and a metal ball on the solder mask to mount chips thereon.
  2. The method of claim 1, wherein the first step includes: (a) forming a trace on the insulation substrate; and (b) forming a solder mask having one or more openings where a surface of an adjacent substrate of the trace is exposed.
  3. The method of claim 2, wherein the second step includes: (c) printing solder paste on the solder mask; (d) attaching a metal ball on a surface of the solder paste of the opening; and (e) attaching a chip of wafer level on the metal ball.
  4. The method of claim 3, wherein the (c) step comprises forming a solder paste on the solder mask using a dry film, or directly printing solder paste on the solder mask.
  5. The method of any one claim of 1 to 4, wherein the step of firmly adhering the metal ball comprises reflowing the metal ball formed from a metal selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, In, or an alloy combined with two or more metals thereof.
  6. The method of any one claim of 1 to 4, wherein the step of firmly adhering the metal ball comprises reflowing the metal ball formed from a metal selected from a group consisting of Cu, Ni, Sn, Al, Ag, TiN, Pb, where the metal ball has a core made of a metal or a plastic.
  7. The method of claim 5, wherein the metal ball is superficially performed with a surface treatment of an organic material coating or a metal plating.
  8. The method of claim 7, wherein where the organic material is for organic solder preservation coating, and the metal plating is carried out using a metal selected from a group consisting of Au, Sn, Ni, Pb, Ag, In, or an alloy combined with one or more metals thereof.
  9. A semiconductor package, comprising: a solder mask layer disposed with an opening through which a surface of an adjacent substrate of a trace on an insulation substrate is exposed and a solder paste filled in the opening; and a metal ball connecting the solder paste and a chip bump of a chip of a wafer level, where the metal ball is diametrally 20μm~200μm.
  10. The semiconductor package of claim 9, wherein a bump pitch according to the metal ball is 50μm~200μm.
PCT/KR2010/002683 2009-04-30 2010-04-28 Semiconductor package with nsmd type solder mask and method for manufacturing the same WO2010126302A2 (en)

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