TWI404193B - 半導體裝置以及構成半導體結構之方法 - Google Patents

半導體裝置以及構成半導體結構之方法 Download PDF

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TWI404193B
TWI404193B TW098144916A TW98144916A TWI404193B TW I404193 B TWI404193 B TW I404193B TW 098144916 A TW098144916 A TW 098144916A TW 98144916 A TW98144916 A TW 98144916A TW I404193 B TWI404193 B TW I404193B
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Hsin Chih Chiang
Han Chung Tai
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System General Corp
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    • H—ELECTRICITY
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823892—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the wells or tubs, e.g. twin tubs, high energy well implants, buried implanted layers for lateral isolation [BILLI]
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    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823828—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes
    • H01L21/82385—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate conductors, e.g. particular materials, shapes gate conductors with different shapes, lengths or dimensions
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    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823857—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate insulating layers, e.g. different gate insulating layer thicknesses, particular gate insulator materials or particular gate insulator implants
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    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body
    • H01L27/08—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind
    • H01L27/085—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only
    • H01L27/088—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate
    • H01L27/092—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors
    • H01L27/0928—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being a semiconductor body including only semiconductor components of a single kind including field-effect components only the components being field-effect transistors with insulated gate complementary MIS field-effect transistors comprising both N- and P- wells in the substrate, e.g. twin-tub

Description

半導體裝置以及構成半導體結構之方法
本發明係有關於一種半導體裝置，特別是有關於一種新的高端裝置，其與一原始低端裝置結合在一起。
多種電源供應器與馬達驅動器利用橋式電路來控制電源給負載。此橋式電路一般具有連接電源之一高端電晶體(high-side transistor)以及連接接地端之低端電晶體(low-side transistor)。高端電晶體與低端電晶體之間的共通節點耦接該負載，隨著這些電晶體被控制來交替地導通，此共通節點之電壓則在電源之電壓位準與接地端之電壓位準之間擺動。因此，一高端電晶體驅動器則需要電荷泵電路(charge pump circuit)以及/或浮接驅動電路(floating drive circuit)，以完全地導通高端電晶體。在最近的發展中，揭露了許多浮接電路，例如美國專利編號6,344,959(Milazzo)、美國專利編號6,781,422(Yang)、以及美國專利編號6,836,173(Yang)。
第1圖係表示習知高端電晶體驅動電路。浮接電路10用來控制高端電晶體11的導通/關閉狀態。NMOS電晶體12透過在低端電路中的反相器13來接收控制信號S1 。NMOS電晶體12之汲極區域120耦接浮接電路10之反相器17。高端電晶體11耦接低端電晶體14於共通節點，且一輸出電壓VO 產生於此共通節點。電荷泵電容器15提供供電電壓給浮接電路10。一旦低端電晶體14根據控制信號S2 而導通，電壓VD 則透過二極體16來對電荷泵電容器15充電。當高端電晶體11導通時，電荷泵電容器15之接地參考端則被拉至電壓源VIN 的位準。
第2圖係表示第1圖中高端反相器17與低端反相器13之半導體裝置的上視圖。此積體電路包括高端區域2以形成複數高端裝置，例如高端反相器17。障壁(barrier)170介於高端區域2與低端區域3之間。
NMOS電晶體12之汲極區域120透過高端導線22來耦接高端區域2之NMOS電晶體20與PMOS電晶體21。NMOS電晶體12之閘極區域則耦接低端區域3之NMOS電晶體30與PMOS電晶體31。
第3圖係表示第2圖之半導體裝置的半導體架構截面圖。NMOS電晶體12配置在N型井區102。N+傳導型態區域形成汲極區(D)120，另一N+傳導型態區域形成源極區域(S)121，且介於汲極區域120與源極區域121之間的多晶矽材料形成閘極電極(G)122。其中，閘極電極122配置在氧化層123上，用以控制在傳導通道上的電流。高端裝置包括NMOS電晶體20以及PMOS電晶體21，用以作為高端反相器17。在NMOS電晶體20中，一N+傳導型態區域配置在P型井區204中以做為源極區域(S)200，配置在一N型區域201內的另一N+傳導型態區域(N型雙摻雜區域(N-type double diffusion region)，其中，N+傳導型態區域具有較濃的摻雜濃度，而N型區域201具有較淡的摻雜濃度)形成汲極區域(D)202，配置在汲極區域202與源極區域200之間的多晶矽材料則形成閘極電極(G)203。關於PMOS電晶體21，一P+傳導型態區域配置在N型井區102中以做為源極區域(S)210，配置在一P型區域211內的另一P+傳導型態區域(P型雙摻雜區域(P-type double diffusion region)，其中，P+傳導型態區域具有較濃的摻雜濃度，而P型區域211具有較淡的摻雜濃度)形成汲極區域(D)212，配置在汲極區域212與源極區域210之間的多晶矽材料則形成閘極電極(G)213。P型井區柵欄170係由一P+傳導型態區域171所構成。一P摻雜區域172配置在N型井區102。高端導線22(500V)係跨越P型井區障壁170而耦接。
低端裝置包括NMOS電晶體30以及PMOS電晶體31，用以作為低端反相器13。NMOS電晶體30與PMOS電晶體31配置在深N型井區102。NMOS電晶體30包括N+傳導型態區域，以作為汲極區域(D)40，也包括配置在P型井區41另一N+傳導型態區域，以做為源極區域(S)42。介於汲極區域40與源極區域42之間的一多晶矽材料則形成閘極電極(G)43。PMOS電晶體31包括P+傳導型態區域，以做為源極區域(S)50，也包括配置在P型井區51之另一P+傳導型態區域，以作為汲極區域(D)52。介於汲極區域52與源極區域50之間的一多晶矽材料形則形成閘極電極(G)53。
上述習知半導體架構的缺點在於，由於藉由高端導線22與障壁170之金屬間的介質崩潰電壓(金屬-金屬介質崩潰電壓)為500V，所以高端導線之操作電壓較低。NMOS電晶體20之操作電壓為15V。期望能有較高的介質崩潰電壓與較高的操作電壓。
本發明提供一種半導體裝置，包括一基底、一深井區、以及一第一高端裝置。基底具有第一傳導型態。深井區具有第二傳導型態，且形成在基底上。第一高端裝置配置在深井區內，且包括一隔離層、一井區、一第一區域、一第二區域、以及一第一多晶矽材料。隔離層具有第二傳導型態且形成在基底。井區具有第一傳導型態且形成在深井區內。第一區域及一第二區域皆具有第二傳導型態且皆形成在井區內。第一多晶矽材料配置在第一區域與第二區域之間且在深井區上。
本發明另提供一種構成半導體結構之方法，包括以下步驟：形成具有第一傳導型態之一基底；於基底形成具有第二傳導型態之一半導體層；形成具有第二傳導型態之一深井區，其中，此深井區由基底之表面向下延伸；由基底之表面形成具有第一傳導型態之一井區，其中，此井區配置在深井區內且在半導體層之上方；在深井區上配置一第一多晶矽材料；以及在井區內形成具有第二傳導型態之一第一區域以及一第二區域。
為使本發明之上述目的、特徵和優點能更明顯易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說明如下。
第4圖係表示根據本發明實施例之一高端裝置(high-side device)(反向器)60以及一低端裝置(low-side device)(反向器)61之半導體裝置的上視圖。第5圖係表示根據本發明實施例之半導體裝置之截面圖。參閱第4圖，半導體裝置包括高端區域70，用以形成高端裝置，在此實施例中例如為高端反向器60。障壁700配置在高端區域70與一低端區域71之間。障壁700具有開口區域710，其形成在高端導線10之下方。
NMOS電晶體8之汲極區域80透過高端導線10而耦接高端區域70之NMOS電晶體73與PMOS電晶體72。NMOS電晶體8之閘極區域耦接低端區域71之NMOS電晶體63與PMOS電晶體62。NMOS電晶體8之源極區域82具有開口820，其對應高端導線10之路徑而形成。
第5圖係表示在第4圖中半導體裝置之截面圖。NMOS電晶體8配置在N型井區102。一N+傳導型態區域形成汲極區域(D)80，另一N+傳導型態區域形成源極區域(S)82，以及配置在汲極區域80與源極區域82的多晶矽材料形成閘極電極(G)84。其中，閘極電極84配置在氧化層83之上，以控制在傳導通道上的電流。高端裝置60包括NMOS電晶體73以及PMOS電晶體72。在NMOS電晶體73中，一N+傳導型態半導體層730設置在P型基底P_SUB用作隔離，在此實施例中，其被定義為一隔離層。一P-傳導型態區域形成在N+傳導型態半導體層730上，作為深P型井區731。設置在N+傳導型態半導體層730上之一N+傳導型態區域形成源極區域(S)732，而設置在一N型區域733內之另一N+傳導型態區域((N型雙摻雜區域(N-type double diffusion region)，其中，N+傳導型態區域具有較濃的摻雜濃度，而N型區域733具有較淡的摻雜濃度)形成汲極區域(D)734。介於汲極區域734與源極區域732之間的一多晶矽材料形成閘極電極735。關於PMOS電晶體72，P+傳導型態區域配置在N型井區102中，以作為源極區域(S)720(第三區域)，配置在P型區域721(第五區域)之另一P+傳導型態區域((P型雙摻雜區域(P-type double diffusion region)，其中，P+傳導型態區域具有較濃的摻雜濃度，而P型區域721具有較淡的摻雜濃度)形成汲極區域(D)722(第四區域)。介於汲極區域722與源極區域720之間的一多晶矽材料形成閘極電極723。如第4及5圖所示，P摻雜區域103形成配置在N型井區102之P型井區柵欄700。配置在開口820與開口區域710上方的高端導線10耦接PMOS電晶體72與NMOS電晶體73的閘極區域723與735。
低端裝置61包括NMOS電晶體63及PMOS電晶體62，以作為低端反向器。NMOS電晶體63與PMOS電晶體62配置在深N型井區102。NMOS電晶體63包括一N+傳導型態區域，以作為汲極區域(D)630。NMOS電晶體63也包括配置在P型井區631內之另一N+傳導型態區域，以作為源極區域(S)632。介於汲極區域630與源極區域632之間的一多晶矽材料形成閘極電極(G)633。PMOS電晶體62包括一P+傳導型態區域，以作為源極區域(S)620。PMOS電晶體62也包括配置在P型井區621內之另一P+傳導型態區域，以作為汲極區域(D)622。介於源極區域620與汲極區域622之間的一多晶矽材料形成閘極電極(G)623。
根據前述，此實施例之半導體裝置具有給予NMOS電晶體73的較深P型井區731，使得高端NMOS電晶體73的操作電壓增加，在此實施例中例如可增加至30V。此外，開口820與開口區域710形成在高端導線10之下方，由於金屬-複晶崩潰電壓較高，因此高端導線10之操作電壓可提高至700V。
接下來將敘述形成第5圖中半導體裝置的方法。參閱第6圖，首先，形成具有第一傳導型態的基底，例如P型基底P_SUB(步驟600)。在P型基底P_SUB形成具有第二傳導型態的半導體層，例如N+傳導型態半導體層730(步驟610)。半導體層730形成在P型基底P_SUB內。接著，具有第二傳導型態的深井區，例如N型深井區102由P型基底P_SUB之表面向下延伸(步驟620)。具有第一傳導型態之深井區，例如P型井區731接著由P型基底P_SUB之表面來形成(步驟630)。其中，P型井區731配置在N型深井區102之內且在N+傳導型態半導體層730之上方。因此，N+傳導型態半導體層730提供了P型基底P_SUB與P型井區731之間的隔離。在步驟640中，複數第一摻雜區域(例如P型區域721、103、621、631)形成在N型深井區102內。接著，一第二摻雜區域(例如N型區域733)形成在P型井區內731(步驟650)。接下來，場氧化層83形成在N型深井區102上，且閘極區域723、735、84、623、以及633形成在N型深井區102上(步驟660)。接著，N+傳導型態區域732、734、82、630、以及632分別形成在P型井區731、N型區域733、N型深井區102、以及P型區域631內(步驟670)。之後，P+傳導型態區域722、720、620、以及622分別形成在P型井區721、N型深井區102、N型深井區102、以及P型區域621內(步驟680)。接著，執行接續的處理(例如連接介於汲極區域(D)80與NMOS電晶體73和PMOS電晶體72之間的高端導線10)以及其他程序步驟，以完成半導體製造(步驟690)。
在此實施例中，N+傳導型態源極區域732、N+傳導型態汲極區域734、以及閘極電極735形成高端裝置，例如第4圖中的NMOS電晶體73。P+傳導型態源極區域720、P+傳導型態汲極區域722、以及閘極區域723形成另一高端裝置，例如第4圖中的PMOS電晶體72。
本發明雖以較佳實施例揭露如上，然其並非用以限定本發明的範圍，任何所屬技術領域中具有通常知識者，在不脫離本發明之精神和範圍內，當可做些許的更動與潤飾，因此本發明之保護範圍當視後附之申請專利範圍所界定者為準。
 第1圖：
10．．．浮接電路
11．．．高端電晶體
12．．．NMOS電晶體
13．．．反相器
14．．．低端電晶體
15．．．電荷泵電容器
16．．．二極體
17．．．反相器
120．．．汲極區域
VD ．．．電壓
VIN ．．．電壓源
VO ．．．輸出電壓
S1 、S2 ．．．控制信號
第2圖：
2．．．高端區域
3．．．低端區域
20．．．NMOS電晶體
21．．．PMOS電晶體
22．．．高端導線
30．．．NMOS電晶體
31．．．PMOS電晶體
170．．．柵欄
第3圖：
50．．．源極區域
51．．．P型井區
52．．．汲極區域
53．．．閘極電極
40．．．汲極區域
41．．．P型井區
42．．．源極區域
43．．．閘極電極
102．．．N型井區
120．．．汲極區域
121．．．源極區域
122．．．閘極電極
123．．．氧化層
171．．．P+傳導型態區域
172．．．P摻雜區域
200．．．源極區域
201．．．N型區域
202．．．汲極區域
203．．．閘極電極
204．．．P型井區
210．．．源極區域
211．．．P型區域
212．．．汲極區域
213．．．閘極電極
第4圖：
8．．．NMOS電晶體
10．．．高端導線
60．．．高端裝置(反向器)
61．．．低端裝置(反向器)
62．．．PMOS電晶體
63．．．NMOS電晶體
70．．．高端區域
71．．．低端區域
72．．．PMOS電晶體
73．．．NMOS電晶體
80．．．汲極區域
82．．．源極區域
700．．．障壁
710．．．開口區域
820．．．開口
第5圖：
83．．．氧化層
84．．．閘極電極
102．．．N型井區
103．．．P摻雜區域
620．．．源極區域
621．．．P型井區
622．．．汲極區域
623．．．閘極電極
630．．．汲極區域
631．．．P型井區
632．．．源極區域
633．．．閘極電極
720．．．源極區域
721．．．P型區域
722．．．汲極區域
723．．．閘極電極
730．．．N+傳導型態半導體層
731．．．深P型井區
732．．．源極區域
733．．．N型區域
734．．．汲極區域
735．．．閘極電極
P_SUBP．．．型基底
第6圖：
600...690．．．流程步驟
第1圖表示習知高端電晶體驅動電路；
第2圖表示第1圖中高端反向器與低端反向器之半導體裝置之上視圖；
第3圖表示第2圖中半導體裝置的半導體架構截面圖；
第4圖表示根據本發明實施例之高端裝置與低端裝置之半導體裝置上視圖；
第5圖表示第4圖中半導體裝置的半導體架構截面圖；以及
第6圖表示形成第5圖中半導體裝置之方法。
10．．．高端導線
60．．．高端裝置(反向器)
61．．．低端裝置(反向器)
62．．．PMOS電晶體
63．．．NMOS電晶體
70．．．高端區域
71．．．低端區域
72．．．PMOS電晶體
73．．．NMOS電晶體
80．．．汲極區域
82．．．源極區域
700．．．柵欄
710．．．開口區域
820．．．開口

Claims (14)

  1. 一種半導體裝置，包括：一基底，具有一第一傳導型態；一深井區，具有一第二傳導型態，且形成在該基底上；以及一第一高端裝置，配置在該深井區內，且包括：一隔離層，具有該第二傳導型態，且形成在該基底，其中，該隔離層直接接觸該基底；一井區，具有該第一傳導型態，且形成在該深井區內，其中，該井區直接接觸該隔離層，且該隔離層將該井區完全地隔離於該基底；一第一區域及一第二區域，皆具有該第二傳導型態，且皆形成在該井區內，其中，由該井區將該第一區域以及該第二區域完全地隔離於該隔離層；以及一第一多晶矽材料，配置在該第一區域與該第二區域之間且在該深井區上。
  2. 如申請專利範圍第1項所述之半導體裝置，其中，該第一高端裝置更包括一第三區域，具有該第二傳導型態，形成在該井區內且介於該第二區域與該井區之間。
  3. 如申請專利範圍第2項所述之半導體裝置，其中，該第二區域與該第三區域形成一雙摻雜區域。
  4. 如申請專利範圍第1項所述之半導體裝置，更包括一第二高端裝置，配置在該深井區內且包括：一第三區域及一第四區域，皆具有該第一傳導型態，且皆形成在該深井區內；以及 一第二多晶矽材料，配置在該第三區域與該第四區域之間且在該深井區上。
  5. 如申請專利範圍第4項所述之半導體裝置，其中，該第二高端裝置更包括一第五區域，具有該第一傳導型態，形成在該深井區內且介於該第四區域與該深井區之間。
  6. 如申請專利範圍第5項所述之半導體裝置，其中，該第四區域與該第五區域形成一雙摻雜區域。
  7. 如申請專利範圍第1項所述之半導體裝置，更包括：一高端電晶體，耦接於一電壓源與一共通節點之間；以及一低端電晶體，耦接於該共通節點與一接地端之間，其中，該第一高端裝置用來控制該高端電晶體之狀態。
  8. 一種構成一半導體結構之方法，包括：形成具有一第一傳導型態之一基底；於該基底形成具有一第二傳導型態之一半導體層，其中，該半導體層直接接觸該基底；形成具有該第二傳導型態之一深井區，其中，該深井區由該基底之表面向下延伸；由該基底之表面形成具有該第一傳導型態之一井區，其中，該井區配置在該深井區內且在該半導體層之上方，該井區直接接觸該半導體層，且該半導體層將該井區完全地隔離於該基底；在該深井區上配置一第一多晶矽材料；以及在該井區內形成具有該第二傳導型態之一第一區域以及一第二區域，其中，由該井區將該第一區域以及該第二 區域完全地隔離於該半導體層。
  9. 如申請專利範圍第8項所述之構成半導體結構之方法，更包括：形成具有該第二傳導型態之一第三區域，其中，該第三區域形成在該井區內且在該第二區域與該井區之間。
  10. 如申請專利範圍第9項所述之構成半導體結構之方法，其中，該第二區域與該第三區域形成一雙摻雜區域。
  11. 如申請專利範圍第8項所述之構成半導體結構之方法，更包括：在該深井區內形成具有該第一傳導型態之一第三區域及一第四區域；以及配置一第二多晶矽材料，其中，該第二多晶矽材料配置在該第三區域與該第四區域之間且在該深井區上。
  12. 如申請專利範圍第11項所述之構成半導體結構之方法，更包括：形成具有該第一傳導型態之一第五區域，其中，該第五區域形成在該深井區內且在該第四區域與該深井區之間。
  13. 如申請專利範圍第12項所述之構成半導體結構之方法，其中，該第四區域與該第五區域形成一雙摻雜區域。
  14. 如申請專利範圍第11項所述之構成半導體結構之方法，該第一區域、該第二區域、以及該第一多晶矽材料形成一第一高端裝置，且該第三區域、該第四區域、以及該第二多晶矽材料形成一第二高端裝置。
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