TWI648821B - 高電壓雙擴散金氧半導體（ｄｍｏｓ）裝置及其製造方法 - Google Patents

高電壓雙擴散金氧半導體（ｄｍｏｓ）裝置及其製造方法 Download PDF

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TWI648821B
TWI648821B TW104101585A TW104101585A TWI648821B TW I648821 B TWI648821 B TW I648821B TW 104101585 A TW104101585 A TW 104101585A TW 104101585 A TW104101585 A TW 104101585A TW I648821 B TWI648821 B TW I648821B
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floating gate
control
region
control gate
gate
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TW201532198A (zh
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波麥 陳
蘇努 達瑞那尼
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美商微晶片科技公司
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Abstract

一種形成一積體雙擴散金氧半導體(DMOS)電晶體/電可擦除可程式化唯讀記憶體(EEPROM)胞之方法包含：在一基板上方形成一第一遮罩；使用該第一遮罩在該基板中形成一漂移植入以對準該漂移植入；同時在該漂移植入上方形成一第一浮動閘極及與該漂移植入隔開之一第二浮動閘極；形成罩蓋該第二浮動閘極且罩蓋該第一浮動閘極之一部分之一第二遮罩；使用該第一浮動閘極之一邊緣在該基板中形成一基極植入，以使該基極植入區域自對準；且同時在該第一浮動閘極上方形成一第一控制閘極及在該第二浮動閘極上方形成一第二控制閘極。該第一浮動閘極、第一控制閘極、漂移植入及基極植入形成該DMOS電晶體之組件，且該等第二浮動閘極及第二控制閘極形成該EEPROM胞之組件。

Description

高電壓雙擴散金氧半導體(DMOS)裝置及其製造方法
本發明係關於一種高壓雙擴散MOS裝置(HV DMOS)及其製造方法。本發明亦關於一種用於產生一積體電可擦除可程式化唯讀記憶體(EEPROM)胞及HV DMOS以用於高壓應用(例如，馬達控制、照明、開關等等)中之程序流程。
EEPROM係一類非揮發性半導體記憶體，其中可電程式化資訊至各記憶體元件或位元胞中及自各記憶體元件或位元胞擦除資訊。EEPROM之各位元胞包括兩個金氧半導體場效應電晶體(MOSFET)。該等MOSFET之一者具有兩個閘極且係用於儲存位元資訊，及另一MOSFET係用於選擇位元胞。EEPROM通常經實現為浮動閘極電晶體之陣列。
一典型EEPROM位元胞包含：一浮動閘極，其配置於形成於一矽基板中之源極與汲極區域之間，及一控制閘極，其控制該浮動閘極之充電，該控制閘極經配置(絕緣)以保持一電荷。在浮動閘極上無電荷之情況下，電晶體正常作用，且控制閘極上之一脈衝引起電流流動。當充電時，其阻止控制閘極作用，且電流不流動。藉由將源極及汲極終端接地且在通過氧化物至浮動閘極之一控制閘極穿隧上放置足夠電壓來完成充電。自另一電晶體通入之一反向電壓藉由引起電荷消散至 基板中而清除電荷。
一些EEPROM設計在一P型井基板上方提供N通道胞。其他設計在一N型井上方提供P通道胞，其自身駐留於一P型基板中，諸如美國專利第5,986,931號及第5,790,455號，EP2339585A1及EP2267775A2中所揭示，該等申請案之全文以引用方式併入本文中。
一雙擴散金氧半導體(DMOS)係適用於高壓應用之一常見電晶體。因為擴散程序涉及產生N摻雜及P摻雜區域兩者，所以一DMOS被稱為「雙擴散」。與許多其他電晶體類型比較，DMOS電晶體通常提供一較高崩潰電壓及較低接通狀態電阻。一些DMOS結構在源極與汲極區域之間界定一橫向通道，其中該通道係定位於閘極(例如，浮動閘極)下方。通常藉由包含通道尺寸及摻雜特性之參數來判定此等DMOS胞之性能特性(諸如崩潰電壓及接通狀態電阻)。
根據一實施例，一雙擴散金氧半導體(DMOS)裝置可包含：一基板；一基極植入區域，其形成於該基極中；一源極區域，其形成於該基極植入中；一汲極區域，其形成於該基板中；一浮動閘極，其形成於該基板上方；一控制閘極，其在該基極植入區域上方延伸；一浮動閘極電極，其電耦合至該浮動閘極；及控制電子器件，其等經組態以經由該浮動閘極電極來控制施加至該浮動閘極之一電壓，藉此控制該DMOS裝置之一崩潰電壓及一源極-汲極電阻。
根據一實施例，一種同時形成一雙擴散金氧半導體(DMOS)電晶體及一電可擦除可程式化唯讀記憶體(EEPROM)胞之方法，其可包含：在一基板上方形成一第一遮罩；使用該第一遮罩在該基板中形成一漂移植入區域以對準該漂移植入區域；同時在該基板中之該漂移植入區域上方形成一第一浮動閘極及在該基板上方與該漂移植入區域隔開之一位置處形成一第二浮動閘極；形成罩蓋該第二浮動閘極且罩蓋 該第一浮動閘極之一部分之一第二遮罩；使用該第一浮動閘極之一邊緣在該基板中形成一基極植入區域以自對準該基極植入區域；且同時在該第一浮動閘極上方形成一第一控制閘極及在該第二浮動閘極上方形成一第二控制閘極，其中該第一浮動閘極、第一控制閘極、漂移植入區域及基極植入區域形成該DMOS電晶體之組件，且其中該等第二浮動閘極及第二控制閘極形成該EEPROM胞之組件。
根據另一實施例，提供一種控制一雙擴散金氧半導體(DMOS)電晶體之方法，該DMOS電晶體包含：一基極植入區域，其形成於一基極中；一源極區域，其形成於該基極植入中；一汲極區域，其形成於該基板中；一浮動閘極；一控制閘極，其在該汲極植入區域上方延伸；一控制閘極電極，其電耦合至該控制閘極；及一浮動閘極電極，其電耦合至該浮動閘極，該方法包含經由該浮動閘極電極來施加一電壓至該浮動閘極，藉此影響該DMOS裝置之一崩潰電壓及一源極-汲極電阻。
10‧‧‧半導體基板
12A‧‧‧高壓(HV)p型井
12B‧‧‧高壓(HV)p型井
14‧‧‧高電壓雙擴散金氧半導體(HV DMOS)區域
16‧‧‧積體電可擦除可程式化唯讀記憶體(EEPROM)胞區域
18A‧‧‧隔離區域
18B‧‧‧隔離區域
20‧‧‧光罩
22‧‧‧n漂移植入區域
30A‧‧‧HV DMOS浮動閘極結構
30B‧‧‧EEPROM浮動閘極結構
32A‧‧‧穿隧氧化物區域
32B‧‧‧穿隧氧化物區域
34A‧‧‧DMOS浮動閘極
34B‧‧‧EEPROM浮動閘極區域
36A‧‧‧氮氧化物區域
36B‧‧‧氮氧化物區域
40‧‧‧光罩
42‧‧‧p摻雜基極植入/p通道/基極層
44‧‧‧邊緣
50‧‧‧氧化物層
54A‧‧‧HV DMOS控制閘極
54B‧‧‧EEPROM控制閘極
60A‧‧‧輕摻雜汲極(LDD)源極區域
60B‧‧‧輕摻雜汲極(LDD)源極區域
62A‧‧‧輕摻雜汲極(LDD)汲極區域
62B‧‧‧輕摻雜汲極(LDD)汲極區域
66‧‧‧邊緣
67‧‧‧沈積氧化物層
68‧‧‧垂直開口
70A‧‧‧n+栓塞植入
70B‧‧‧n+栓塞植入
72A‧‧‧n+栓塞植入
72B‧‧‧n+栓塞植入
80A‧‧‧源極電極
80B‧‧‧源極電極
82A‧‧‧汲極電極
82B‧‧‧汲極電極
84A‧‧‧控制閘極電極
84B‧‧‧控制閘極電極
86‧‧‧浮動閘極電極
90‧‧‧虛線
92‧‧‧累積區域
100‧‧‧高壓(HV)DMOS電晶體
102‧‧‧EEPROM胞
110‧‧‧控制電子器件
Lch‧‧‧閘極長度或通道長度
下文參考圖式討論實例性實施例，其中：圖1至圖8繪示根據一實施例之用於形成包含一積體高壓(HV)DMOS電晶體/EEPROM胞之一裝置之一實例性程序。
圖1至圖8繪示用於形成包含一積體高壓HV DMOS電晶體/EEPROM胞之一裝置之一實例性程序。在所繪示之實例中，HV DMOS電晶體及EEPROM胞經形成為n型裝置。然而，根據下文所揭示之程序，藉由切換整個程序中之摻雜物，HV DMOS電晶體及EEPROM胞可替代地經形成為p型裝置。
在一些實施例中，所繪示之積體n型HV DMOS電晶體及n型EEPROM胞經形成為一較大陣列之半導體裝置之部分，該較大陣列之 半導體裝置包含(a)多個積體n型HV DMOS電晶體及n型EEPROM胞及(b)多個積體p型HV DMOS電晶體及p型EEPROM胞兩者。因此，為製造此一陣列，可重複下文所討論之用於產生n型HV DMOS電晶體及n型EEPROM胞之程序步驟，其中切換n型/p型摻雜以產生該陣列之p型HV DMOS電晶體及p型EEPROM胞，使得可藉由一單一程序流程製造該陣列。
如圖1中所展示，可由任何適當材料(例如，矽、GaAs、InP等等)在一半導體基板10中形成裝置。首先，使用任何適當技術在基板10中形成高壓(HV)p型井12A及12B。HV p型井12A係提供給DMOS電晶體，而p型井12B則係提供給EEPROM胞，如下文所討論。例如，以14指示正形成之DMOS電晶體的區域及以16指示正形成之EEPROM的區域。如圖中所展示，HV p型井12A及12B可藉由基板10之一區域彼此隔開。
接著，使用任何適當技術在該基板中形成一對隔離區域18A及18B。例如，隔離區域18A及18B可經形成為氧化物或任何其他適當隔離材料之淺溝渠隔離(STI)區域。如下文將展示，隔離區域18A係形成於HV DMOS電晶體之後續形成之基極植入與汲極區域之間之一位置處，而隔離區域18B則係形成於DMOS電晶體之後續形成之汲極區域與EEPROM胞之一後續形成之源極區域之間。接著，可在EEPROM胞區域上方形成一光罩20及在HV p型井14A中形成由光罩20對準之一n漂移植入區域22。接著，可移除光罩20。
在一些實施例中，亦可重複上文關於圖1所討論之步驟，其中切換n型/p型摻雜以產生一積體陣列之p型HV DMOS電晶體EEPROM胞，如上文所討論。因此，對應於光罩20之另一光罩(圖中未展示)可用於定位正形成於陣列中之p型DMOS電晶體的p漂移植入區域。
接著，如圖2中所展示，可同時形成一HV DMOS浮動閘極結構 30A及一EEPROM浮動閘極結構30B，其中浮動閘極結構30A係HV DMOS電晶體之一組件，且浮動閘極結構30B係EEPROM胞之一組件。可依任何適當方式及由任何適當材料形成浮動閘極結構30A及30B。例如，可藉由產生一穿隧氧化物層、一浮動閘極層及氮氧化物層之一堆疊來形成浮動閘極結構30A及30B且蝕刻該堆疊以形成所繪示之浮動閘極結構30A及30B，使得DMOS浮動閘極結構30A包括一穿隧氧化物區域32A、一DMOS浮動閘極34A及氮氧化物區域36A，而EEPROM浮動閘極結構30B類似地包括一穿隧氧化物區域32B、一EEPROM浮動閘極區域34B及氮氧化物區域36B。如圖中所展示，DMOS浮動閘極結構30A可在第一隔離區域18A上方部分延伸，而EEPROM浮動閘極結構30B可經定位與第二隔離區域18B隔開。可由多晶矽或任何其他適當材料形成浮動閘極34A及34B，其等亦可被稱為「Poly 1」層。
在亦涉及產生一積體陣列之p型HV DMOS電晶體EEPROM胞之實施例中，亦可重複上文關於圖2所討論之步驟，其中切換n型/p型摻雜以產生一積體陣列之p型HV DMOS電晶體EEPROM胞，如上文所討論。
接著，如圖3中所展示，一光罩40可接著形成於EEPROM胞區域16上方，EEPROM胞區域16包含EEPROM浮動閘極結構30B且在HV DMOS區域14之一部分上方延伸，特定言之，在HV DMOS浮動閘極結構30A上方部分延伸。一p摻雜基極植入或「p通道」42形成於HV n漂移植入區域22中，使得p摻雜基極植入42與HV DMOS浮動閘極結構30A之一邊緣44自對準。接著，可移除光罩40。
在亦涉及產生一積體陣列之p型HV DMOS電晶體EEPROM胞之實施例中，可重複上文關於圖3所討論之步驟，其中切換n型/p型摻雜以產生一積體陣列之p型HV DMOS電晶體EEPROM胞，如上文所討論。 因此，對應於光罩40之另一光罩(圖中未展示)可用於形成各p型DMOS電晶體之一n摻雜基極植入區域，其中各n摻雜基極植入區域與一各自浮動閘極結構之一邊緣對準。根據浮動閘極層之厚度，由於此提供自對準遮罩至基極植入，所以在該植入之後可添加一熱驅動步驟以產生此基極層42之更大深度至半導體基板中。
接著，如圖4中所展示，氧化物層50可形成於完整結構上方。例如，可藉由一標準沈積及氧化程序來形成一HV 250A氧化物層。氧化物層50可與浮動閘極結構30A及30B之頂部上之氮氧化物區域36A及36B一起作用以界定浮動閘極34A及34B上方之氧化物-氮化物-氧化物(ONO)層。
在亦涉及產生一積體陣列之p型HV DMOS電晶體EEPROM胞之實施例中，氧化物層50可在n型HV DMOS電晶體EEPROM胞及p型HV DMOS電晶體EEPROM胞上方延伸。
接著，如圖5中所展示，可使用任何適當技術(例如，沈積、植入、圖案化及蝕刻程序)及使用任何適當材料分別在HV DMOS浮動閘極34A及EEPROM浮動閘極34B上方同時形成一HV DMOS控制閘極54A及一EEPROM控制閘極54B。例如，可由相同多晶矽層形成控制閘極54A及54B，且稱為形成於各自「Poly 1」浮動閘極34A及34B上方之「Poly 2」結構。在一實施例中，HV DMOS控制閘極54A僅部分延伸於浮動閘極結構30A之頂部上方，而EEPROM控制閘極54B完全罩蓋浮動閘極結構30B之頂部且完全橫跨浮動閘極結構30B之頂部而延伸。
接著，針對HV DMOS及EEPROM兩者，可依任何適當方式(例如，藉由輕摻雜汲極(LDD)摻雜裝置之各別位置)植入源極區域及汲極區域。例如，對於HV DMOS，一n-摻雜LDD源極區域60A可形成於p-摻雜基極植入42內，及一n摻雜LDD汲極區域62A可形成於隔離區域 18A之相對側上，如圖中所展示。LDD源極區域60A可與HV DMOS控制閘極54A(即，DMOS Poly 2)之一邊緣66自對準。對於EEPROM，n摻雜LDD源極及汲極區域60B及62B可形成於EEPROM控制閘極54B(即，EEPROM Poly2)之相對側上。
控制閘極之閘極長度或通道長度經指示為Lch。如此項技術中已知，一窄通道長度通常用於一高性能DMOS電晶體。
在亦涉及產生一積體陣列之p型HV DMOS電晶體EEPROM胞之實施例中，可重複上文關於圖3所討論之步驟，其中切換n型/p型摻雜以產生一積體陣列之p型HV DMOS電晶體EEPROM胞，如上文所討論。
接著，如圖6中所展示，可形成高摻雜n+栓塞植入及導電接觸件(電極)。特定言之，一沈積氧化物層67形成於結構上方，且如圖所展示般形成一系列垂直開口68。如圖中所展示，形成垂直開口68，其等向下延伸至各源極及汲極區域，向下延伸至各控制閘極54A及54B且亦向下延伸至HV DMOS浮動閘極結構30A之頂部。接著，透過各源極及汲極區域60A、62A、60B及62B上方之垂直開口68植入高摻雜n+栓塞植入以形成n+栓塞植入70A、72A、70B及72B。高摻雜n+栓塞植入70A、72A、70B及72B形成各源極及汲極之一低電阻接觸件。
接著，以金屬(例如，鎢)或其他導電材料填充垂直開口68以形成與結構之各別元件接觸之一系列電極。特定言之，源極/汲極電極80A、82A、80B及82B接觸各源極及汲極區域60A、62A、60B及62B；控制閘極電極84A及84B分別接觸HV DMOS控制閘極54A及EEPROM控制閘極54B；且浮動閘極電極86接觸HV DMOS浮動閘極34A。所得經完成的結構係指示為HV DMOS電晶體100及EEPROM胞102。浮動閘極電極86可用於施加一電壓至HV DMOS浮動閘極34A以用於各種目的，例如，用於控制HV DMOS裝置之一崩潰電壓(Vbd)及源極-汲極電阻(RSD)，及/或用於在HV DMOS控制閘極54A與汲極區域 62A之間提供一法拉第(Faraday)屏蔽，如下文更詳細地討論。
圖7及圖8專注於HV DMOS電晶體100且因此並未展示相鄰EEPROM胞102。控制電子器件110可經連接至源極電極80A、汲極電極82A、控制閘極電極84A及浮動閘極電極86，以施加選定電壓至源極60A、汲極62A、控制閘極54A及浮動閘極34A且根據期望控制此等電壓。為控制HV DMOS 100，經由控制閘極電極84A施加一電壓偏壓至控制閘極54A，此在基極植入(通道)區域42中產生一反向區域，此引起電子自源極電極70A流動至汲極電極72A。
圖7及圖8繪示兩個不同電壓偏壓方案及所得效果。特定言之，兩個方案繪示如何可藉由施加一選定電壓至浮動閘極34A來控制n-漂移區域之特性，諸如崩潰電壓(Vbd)及源極汲極電阻(RSD)或「接通狀態電阻」。
在圖7中所展示之方案中，浮動閘極34A被接地(經由浮動閘極電極86施加0V)，且自汲極62A至源極60A跨空乏n漂移區域發生一相對大的電壓降。一般由虛線90指示具有電壓降之場。此方案(接地浮動閘極)提供一相對高的崩潰電壓(Vbd)及相對高的源極-汲極電阻(RSD)。
在圖8中所展示之方案中，控制電子器件110經由浮動閘極電極86施加一小的正向電壓偏壓(+3V)至浮動閘極34A。此在浮動閘極34A下方之基板之表面處引起一n漂移累積，以92指示。累積區域92降低源極-汲極電阻(RSD)，但亦降低跨n漂移區域之電壓降(圖8之方案中36V，相較於圖7之方案中之48V)且因此降低崩潰電壓(Vbd)。
在一進一步方案中，控制電子器件110可施加一負向偏壓至浮動閘極，此使得n漂移區域完全空乏，且藉此提供比圖7之接地方案更高之一Vbd及RSD。
因此，可選擇、改變或控制經由閘極電極86施加至浮動閘極34A之電壓以提供一所要崩潰電壓(Vbd)及源極-汲極電阻(RSD)。例如，可 改變浮動閘極上之偏壓以在Vbd與RSD之間產生一所要折衷。此外，使浮動閘極偏壓來控制n-漂移區域特性容許HV DMOS裝置經形成具有一選定尺寸且接著經控制(例如，調整)至所要性能特性，因此減少精確標示裝置尺寸之需要或製造具有不同尺寸之HV DMOS裝置之需要以達成不同性能特性。
此外，施加一固定電位至DMOS浮動閘極34A在控制閘極(Poly 2)54A與汲極區域62A之間提供一法拉第(Faraday)屏蔽。在其中(例如)裝置用於一高頻應用中之情況中，此可為尤其有用。
上文所描述之程序容許修改形成EEPROM胞之一現有程序流程以同時形成具有EEPROM胞及HV DMOS電晶體兩者之一積體陣列，藉由添加兩個遮罩/植入步驟以形成n型或p型DMOS電晶體或藉由四個遮罩/植入步驟以形成n型及p型DMOS電晶體兩者，即，上文參考圖1及圖3所討論之遮罩/植入步驟。
儘管本發明中詳細描述所揭示之實施例，但應了解在不脫離其等精神及範疇之情況下可作出各種改變、替換及替代。

Claims (20)

  1. 一種雙擴散金氧半導體(DMOS)電晶體，其包括：一基板；一基極植入區域，其經形成於該基板中；一源極區域，其經形成於該基極植入區域中；一汲極區域，其經形成於該基板中；一浮動閘極，其經形成於該基板上方；一控制閘極，其在該基極植入區域上方延伸；一浮動閘極電極，其經電耦合至該浮動閘極；一氧化物層，其在該浮動閘極與該控制閘極上方；一高摻雜源極植入物，其透過該氧化物層中之一第一垂直開口而植入，其中以一導電材料填充該第一垂直開口以提供接觸該源極區域之一源極電極；一高摻雜汲極植入物，其透過該氧化物層中之一第二垂直開口而植入，其中以一導電材料填充該第二垂直開口以提供接觸該汲極區域之一汲極電極；及控制電子器件，其等經組態以經由該浮動閘極電極來控制施加至該浮動閘極之一電壓，藉此控制該DMOS電晶體之一崩潰電壓及一源極-汲極電阻。
  2. 如請求項1之DMOS電晶體，其中該基極植入區域係與該浮動閘極之一邊緣自對準。
  3. 如請求項1之DMOS電晶體，其中該源極區域係與該控制閘極之一邊緣自對準。
  4. 如請求項1之DMOS電晶體，其包括介於該基極植入區域與該汲極區域之間之該基板中之一溝渠隔離區域。
  5. 如請求項1之DMOS電晶體，進一步包括：一控制閘極電極，其經電耦合至該控制閘極；及其中該等控制電子器件經組態以經由獨立於施加至該浮動閘極之該電壓之該控制閘極電極來控制施加至該控制閘極之一電壓。
  6. 如請求項1之DMOS電晶體，其中：該控制閘極之一上部分在該控制閘極上方延伸；該浮動閘極係位於該控制閘極之該上部分與該汲極區域之間；及該等控制電子器件經組態以經由該浮動閘極電極來施加該電壓至該浮動閘極，以在該控制閘極之該上部分與該汲極區域之間產生一法拉第(Faraday)屏蔽。
  7. 如請求項1之DMOS電晶體，其中該控制閘極僅罩蓋該浮動閘極之一部分，且該浮動閘極電極在未被該控制閘極罩蓋之一位置處經電耦合至該浮動閘極。
  8. 一種雙擴散金氧半導體(DMOS)電晶體，其包括：一基板；一基極植入區域，其經形成於該基板中；一源極區域，其經形成於該基極植入區域中；一汲極區域，其經形成於該基板中；一浮動閘極，其經形成於該基板上方；一控制閘極，其在該基極植入區域上方延伸；一浮動閘極電極，其經電耦合至該浮動閘極；其中該基極植入區域係與該浮動閘極之一邊緣自對準及其中該源極區域係與該控制閘極之一邊緣自對準；及控制電子器件，其等經組態以經由該浮動閘極電極來控制施加至該浮動閘極之一電壓，藉此控制該DMOS電晶體之一崩潰電壓及一源極-汲極電阻。
  9. 如請求項8之DMOS電晶體，其包括介於該基極植入區域與該汲極區域之間之該基板中之一溝渠隔離區域。
  10. 如請求項8之DMOS電晶體，進一步包括：一控制閘極電極，其經電耦合至該控制閘極；及其中該等控制電子器件經組態以經由獨立於施加至該浮動閘極之該電壓之該控制閘極電極來控制施加至該控制閘極之一電壓。
  11. 如請求項8之DMOS電晶體，其中：該控制閘極之一上部分在該浮動閘極上方延伸；該浮動閘極係位於該控制閘極之該上部分與該汲極區域之間；及該等控制電子器件經組態以經由該浮動閘極電極來施加該電壓至該浮動閘極，以在該控制閘極之該上部分與該汲極區域之間產生一法拉第(Faraday)屏蔽。
  12. 如請求項8之DMOS電晶體，其中該控制閘極僅罩蓋該浮動閘極之一部分，且該浮動閘極電極在未被該控制閘極罩蓋之一位置處經電耦合至該浮動閘極。
  13. 如請求項8之DMOS電晶體，其進一步包括：一氧化物層，其在該浮動閘極與該控制閘極上方；一高摻雜源極植入物，其透過該氧化物層中之一第一垂直開口而植入，其中以一導電材料填充該第一垂直開口以提供接觸該源極區域之一源極電極；一高摻雜汲極植入物，其透過該氧化物層中之一第二垂直開口而植入，其中以一導電材料填充該第二垂直開口以提供接觸該汲極區域之一汲極電極；及在該氧化物層中之第三垂直開口與第四垂直開口，其中以一導電材料填充該第三垂直開口與該第四垂直開口以分別提供一控制閘極電極與該浮動閘極電極。
  14. 一種雙擴散金氧半導體(DMOS)電晶體，其包括：一基板；一基極植入區域，其經形成於該基板中；一源極區域，其經形成於該基極植入區域中；一汲極區域，其經形成於該基板中；一浮動閘極，其經形成於該基板上方；一控制閘極，其在該基極植入區域上方延伸；一浮動閘極電極，其經電耦合至該浮動閘極；一溝渠隔離區域，其位於該基板中介於該基極植入區域與該汲極區域之間，該溝渠隔離區域在該浮動閘極下方水平延伸但不在該控制閘極下方水平延伸；及控制電子器件，其等經組態以經由該浮動閘極電極來控制施加至該浮動閘極之一電壓，藉此控制該DMOS電晶體之一崩潰電壓及一源極-汲極電阻。
  15. 如請求項14之DMOS電晶體，其進一步包括：一氧化物層，其在該浮動閘極與該控制閘極上方；一高摻雜源極植入物，其透過該氧化物層中之一第一垂直開口而植入，其中以一導電材料填充該第一垂直開口以提供接觸該源極區域之一源極電極；及一高摻雜汲極植入物，其透過該氧化物層中之一第二垂直開口而植入，其中以一導電材料填充該第二垂直開口以提供接觸該汲極區域之一汲極電極。
  16. 如請求項15之DMOS電晶體，其進一步包括在該氧化物層中之第三垂直開口與第四垂直開口，其中以一導電材料填充該第三垂直開口與該第四垂直開口以分別提供一控制閘極電極與該浮動閘極電極。
  17. 如請求項14之DMOS電晶體，其中該基極植入區域係與該浮動閘極之一邊緣自對準及/或其中該源極區域係與該控制閘極之一邊緣自對準。
  18. 如請求項14之DMOS電晶體，進一步包括：一控制閘極電極，其經電耦合至該控制閘極；及其中該等控制電子器件經組態以經由獨立於施加至該浮動閘極之該電壓之該控制閘極電極來控制施加至該控制閘極之一電壓。
  19. 如請求項14之DMOS電晶體，其中：該控制閘極之一上部分在該浮動閘極上方延伸；該浮動閘極係位於該控制閘極之該上部分與該汲極區域之間；及該等控制電子器件經組態以經由該浮動閘極電極來施加該電壓至該浮動閘極，以在該控制閘極之該上部分與該汲極區域之間產生一法拉第(Faraday)屏蔽。
  20. 如請求項14之DMOS電晶體，其中該控制閘極僅罩蓋該浮動閘極之一部分，且該浮動閘極電極在未被該控制閘極罩蓋之一位置處經電耦合至該浮動閘極。
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