TWI404141B - 圖案形成方法、半導體裝置之製造方法及半導體裝置之製造裝置 - Google Patents

圖案形成方法、半導體裝置之製造方法及半導體裝置之製造裝置 Download PDF

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Publication number
TWI404141B
TWI404141B TW098104546A TW98104546A TWI404141B TW I404141 B TWI404141 B TW I404141B TW 098104546 A TW098104546 A TW 098104546A TW 98104546 A TW98104546 A TW 98104546A TW I404141 B TWI404141 B TW I404141B
Authority
TW
Taiwan
Prior art keywords
layer
pattern
mask
boundary layer
forming
Prior art date
Application number
TW098104546A
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English (en)
Chinese (zh)
Other versions
TW201003780A (en
Inventor
八重樫英民
志村悟
Original Assignee
東京威力科創股份有限公司
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Application filed by 東京威力科創股份有限公司 filed Critical 東京威力科創股份有限公司
Publication of TW201003780A publication Critical patent/TW201003780A/zh
Application granted granted Critical
Publication of TWI404141B publication Critical patent/TWI404141B/zh

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Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P76/00—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography
    • H10P76/40—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials
    • H10P76/408—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes
    • H10P76/4085—Manufacture or treatment of masks on semiconductor bodies, e.g. by lithography or photolithography of masks comprising inorganic materials characterised by their sizes, orientations, dispositions, behaviours or shapes characterised by the processes involved to create the masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B69/00—Erasable-and-programmable ROM [EPROM] devices not provided for in groups H10B41/00 - H10B63/00, e.g. ultraviolet erasable-and-programmable ROM [UVEPROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/69—Etching of wafers, substrates or parts of devices using masks for semiconductor materials
    • H10P50/691—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials
    • H10P50/693—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane
    • H10P50/695—Etching of wafers, substrates or parts of devices using masks for semiconductor materials for Group V materials or Group III-V materials characterised by their size, orientation, disposition, behaviour or shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks or sidewalls or to modify the mask
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P50/00—Etching of wafers, substrates or parts of devices
    • H10P50/73—Etching of wafers, substrates or parts of devices using masks for insulating materials
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10P—GENERIC PROCESSES OR APPARATUS FOR THE MANUFACTURE OR TREATMENT OF DEVICES COVERED BY CLASS H10
    • H10P72/00—Handling or holding of wafers, substrates or devices during manufacture or treatment thereof
    • H10P72/04—Apparatus for manufacture or treatment
    • H10P72/0402—Apparatus for fluid treatment
    • H10P72/0418—Apparatus for fluid treatment for etching

Landscapes

  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Photosensitive Polymer And Photoresist Processing (AREA)
  • Drying Of Semiconductors (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW098104546A 2008-02-15 2009-02-12 圖案形成方法、半導體裝置之製造方法及半導體裝置之製造裝置 TWI404141B (zh)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2008034230 2008-02-15
JP2009003910A JP5254049B2 (ja) 2008-02-15 2009-01-09 パターン形成方法及び半導体装置の製造方法

Publications (2)

Publication Number Publication Date
TW201003780A TW201003780A (en) 2010-01-16
TWI404141B true TWI404141B (zh) 2013-08-01

Family

ID=40955521

Family Applications (1)

Application Number Title Priority Date Filing Date
TW098104546A TWI404141B (zh) 2008-02-15 2009-02-12 圖案形成方法、半導體裝置之製造方法及半導體裝置之製造裝置

Country Status (4)

Country Link
US (2) US8273661B2 (https=)
JP (1) JP5254049B2 (https=)
KR (1) KR101000947B1 (https=)
TW (1) TWI404141B (https=)

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KR20100098843A (ko) * 2009-03-02 2010-09-10 삼성전자주식회사 패턴 형성 방법
JP5589692B2 (ja) 2010-09-08 2014-09-17 富士通セミコンダクター株式会社 半導体装置の製造方法
US8138097B1 (en) 2010-09-20 2012-03-20 Kabushiki Kaisha Toshiba Method for processing semiconductor structure and device based on the same
US9233840B2 (en) * 2010-10-28 2016-01-12 International Business Machines Corporation Method for improving self-assembled polymer features
KR101871748B1 (ko) 2011-12-06 2018-06-28 삼성전자주식회사 반도체 소자의 패턴 형성 방법
CN104576515B (zh) * 2013-11-15 2017-10-13 北京京东方光电科技有限公司 图案化石墨烯薄膜及阵列基板的制作方法、阵列基板
JP6126570B2 (ja) * 2013-12-13 2017-05-10 富士フイルム株式会社 パターン形成方法、電子デバイスの製造方法
JP6272949B2 (ja) * 2016-06-06 2018-01-31 東京エレクトロン株式会社 パターン形成方法
CN106707715B (zh) * 2017-01-11 2019-05-21 中国科学院长春光学精密机械与物理研究所 一种半导体器件及其制作方法
US10734238B2 (en) * 2017-11-21 2020-08-04 Lam Research Corporation Atomic layer deposition and etch in a single plasma chamber for critical dimension control
KR102431218B1 (ko) * 2018-10-01 2022-08-09 유니산티스 일렉트로닉스 싱가포르 프라이빗 리미티드 기둥상 반도체 장치의 제조 방법
US11629402B2 (en) 2019-04-16 2023-04-18 Applied Materials, Inc. Atomic layer deposition on optical structures
US11572619B2 (en) 2019-04-16 2023-02-07 Applied Materials, Inc. Method of thin film deposition in trenches

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US6858361B2 (en) * 2002-03-01 2005-02-22 David S. L. Mui Methodology for repeatable post etch CD in a production tool
US20070020565A1 (en) * 2005-07-25 2007-01-25 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device
US20070077524A1 (en) * 2005-09-30 2007-04-05 Samsung Electronics Co., Ltd. Method for forming patterns of semiconductor device
US20070123037A1 (en) * 2005-04-19 2007-05-31 Ji-Young Lee Method of forming pattern using fine pitch hard mask
US20070287299A1 (en) * 2006-06-08 2007-12-13 Doo-Youl Lee Method of forming a semiconductor device

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JPS60207339A (ja) * 1984-03-30 1985-10-18 Matsushita Electronics Corp パタ−ン形成方法
JPS6449231A (en) * 1987-08-20 1989-02-23 Fujitsu Ltd Manufacture of semiconductor device
JPH0670954B2 (ja) * 1988-01-26 1994-09-07 日本電気株式会社 半導体装置の製造方法
US5618383A (en) * 1994-03-30 1997-04-08 Texas Instruments Incorporated Narrow lateral dimensioned microelectronic structures and method of forming the same
US6143126A (en) * 1998-05-12 2000-11-07 Semitool, Inc. Process and manufacturing tool architecture for use in the manufacture of one or more metallization levels on an integrated circuit
JP3474865B2 (ja) * 2001-04-20 2003-12-08 株式会社東芝 半導体装置の製造方法
US6833232B2 (en) * 2001-12-20 2004-12-21 Dongbu Electronics Co., Ltd. Micro-pattern forming method for semiconductor device
US7064078B2 (en) * 2004-01-30 2006-06-20 Applied Materials Techniques for the use of amorphous carbon (APF) for various etch and litho integration scheme
US7560390B2 (en) * 2005-06-02 2009-07-14 Micron Technology, Inc. Multiple spacer steps for pitch multiplication
KR100714305B1 (ko) * 2005-12-26 2007-05-02 삼성전자주식회사 자기정렬 이중패턴의 형성방법
KR100672123B1 (ko) 2006-02-02 2007-01-19 주식회사 하이닉스반도체 반도체 소자의 미세 패턴 형성방법
US7745339B2 (en) 2006-02-24 2010-06-29 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device
US7314810B2 (en) * 2006-05-09 2008-01-01 Hynix Semiconductor Inc. Method for forming fine pattern of semiconductor device

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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6858361B2 (en) * 2002-03-01 2005-02-22 David S. L. Mui Methodology for repeatable post etch CD in a production tool
US20070123037A1 (en) * 2005-04-19 2007-05-31 Ji-Young Lee Method of forming pattern using fine pitch hard mask
US20070020565A1 (en) * 2005-07-25 2007-01-25 Samsung Electronics Co., Ltd. Methods of fabricating a semiconductor device
US20070077524A1 (en) * 2005-09-30 2007-04-05 Samsung Electronics Co., Ltd. Method for forming patterns of semiconductor device
US20070287299A1 (en) * 2006-06-08 2007-12-13 Doo-Youl Lee Method of forming a semiconductor device
TW200807502A (en) * 2006-06-08 2008-02-01 Samsung Electronics Co Ltd Method of forming a semiconductor device

Also Published As

Publication number Publication date
US20120312472A1 (en) 2012-12-13
KR20090088823A (ko) 2009-08-20
KR101000947B1 (ko) 2010-12-13
US8273661B2 (en) 2012-09-25
JP2009218574A (ja) 2009-09-24
TW201003780A (en) 2010-01-16
JP5254049B2 (ja) 2013-08-07
US20090209109A1 (en) 2009-08-20

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