TWI360863B - Transistor having three electrically isolated elec - Google Patents

Transistor having three electrically isolated elec Download PDF

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TWI360863B
TWI360863B TW093133254A TW93133254A TWI360863B TW I360863 B TWI360863 B TW I360863B TW 093133254 A TW093133254 A TW 093133254A TW 93133254 A TW93133254 A TW 93133254A TW I360863 B TWI360863 B TW I360863B
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gate
layer
gate structure
sidewall
semiconductor
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TW093133254A
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TW200527599A (en
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Leo Mathew
Ramachandran Muralidhar
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Freescale Semiconductor Inc
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    • B82—NANOTECHNOLOGY
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    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66833—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a charge trapping gate insulator, e.g. MNOS transistors
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
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    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • H10B12/056—Making the transistor the transistor being a FinFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/785—Field effect transistors with field effect produced by an insulated gate having a channel with a horizontal current flow in a vertical sidewall of a semiconductor body, e.g. FinFET, MuGFET
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Description

1360863 九、發明說明： [相關申請書交互參照] 本專利申請案已經在2003年11月10曰在美國以 10/705,317號申請專利。 【發明所屬之技術領域】 本發明係關於半導體，且更明確地關於使用於記憶體的 電晶體。 【先前技術】 隨著電晶體幾何尺寸已經大幅縮小到次微米的範圍，電 晶體結構因為較小尺寸對電晶體裝置物理特性產生之影響 而被迫改變。明確地說’電晶體之通道已經變得極窄。闽 為通道的長度甚短，所以電晶體之汲電極開始對通道内之 電流導通產生負面控制，而非由閘電極做為控制機制。此 問題明顯呈現於文獻中且一般稱為短通道效應。為了減少 短通道效應的問題，已經有人提出一種電晶體結構，其中 有一閘電極位在通道的相反側上。雖然此種方法大幅減少 了短通道問題，但大量生產此種結構的能力仍有問題，因 為在大量生產時將位於相反側的閘極對齊非常難以實施。 被提出的一種替代方案之電晶體結構有一被閘電極環繞之 垂直矽通道，以減少短通道效應。此種電晶體有許多不同 名稱’包括鰭狀場效電晶體（FINFET)與雙閘極電晶體。雖 然FINFET電晶體的某些實施法有單—閘電極，但已有其他 的實施法使用㊣㈣氣隔離的閘電極以改善包括控制電晶 體之臨限電壓等效能。為了將環纟A s aa q Ί π >衣現通道的兩個閘電極做電 96921 .doc 氣隔離’使用化學機械磨光（CMP)或磨光步驟。由於這些電 晶體的鳍狀結構甚窄，所以磨光步驟會造成電晶體裝置磨 光不均勻或形成碟狀。 電晶體結構的縮小也使將非揮發記憶體（譬如唯讀記憶 體與快閃記憶體）和揮發記憶體⑴尺八“與SRam)陣列整合 以做系統晶片（system 〇n chip，s〇c)應用成為可能。一般以 不同製程實現的不同電晶體結構被要求同時能實現非揮發 與揮發記憶體陣列。譬如，‘决閃記憶體電晶體以介於通道 與控制閘極間的浮動閘極結構實現。反之，動態隨機存取 $憶體電晶體以控制深槽電容器之平坦電晶體實現。平坦 電晶體使用單-平面通道，該通道分隔源極與沒極且受位 於上方的閘極控制。所一 茺隹早積體電路上實現揮發與 非揮發記憶體陣列之要求會大幅 文水a大ΐ田i曰加成本，因為必須實施 不同的製程與結構。此外，因為 u两而要不冋的電晶體結構， 所以在相同積體電路上之雷 上之電日日體的刼作特性會顯著地不 同0 【發明内容】 在-種形式中’本發明提出一種製 法。該方法形成一年導龍沾 、置的方 體結構，其中該半導體結構 頂部表面、一第一側壁、及— 及與第一側壁相對之第二
該方法形成一第—閑極結 一側J 乐一閘極結構，宜φ 泫 -閘極結構的位置與第—側壁相广第 位置與第二側壁相鄰 °亥第-閘極結構的 第二閘極結構位於頂部 方’其t該第一閘極結構、第_ 又 弟一間極結構、與第三閘極結 9692l.doc 構彼此在實體上隔離。 ^ β ^ ^ , 閘極、，，σ構與第二閘極結構的形 成疋猎者沉殺-層閉極材料於第三閑極結構和一基板2 並移除閘極材料層位在第二 一 閘極結構上方的部分以形成第 閘極、..D構和第二閘極結構 佴向升/成在另一種形式中，第 :構與第二閘極結構是藉對位於半導體結構頂部表 之間極材料層做非研磨㈣而形成。一基本上平，曰 2層形成於基板上方低於閘極材料層頂部表面的高度。該 1上平坦的層被使用當做—遮罩層以形成第—閘極結構 和第-閘極結構。在另一種形式中，第三問極結構與半導 體結構藉由單一圖樣化步驟形成。一分隔該半導體結構斑 第二閉極結構之第一介電質材料連同至少兩個位於第三問 極結構上方之額外層用單一圖樣化步驟畫出圖樣。於半導 體結構相對兩側在與第一閘極結構和第二開極結構之側面 垂直的方向從半導體結構延伸出㈣—源極/淡極區域和 第二源極/汲極區域被形成，其中形成第一源極/汲極區域和 第二源極/汲極區域的步驟進一步包括在對應於第一源極/ 汲極區域和第二源極/汲極區域之位置摻雜該積體電路。第 一源極/汲極區域和第二源極/汲極區域係藉將第一閘極結 構、第二閘極結構和第三閘極結構圖樣化以暴露第一源極/ 汲極區域和第二源極/汲極區域而形成。形成第一源極/汲極 區域和第二源極/汲極區域之後，藉在基板上方形成一低於 閉極材料層頂部高度之大致平坦的層並使用該大致平坦的 層當做遮罩層來形成第一閘極結構與第二閘極結構。在一 種幵> 式_ ’環繞半導體結構之第一側壁和第二側壁形成一 9692l.doc 1360863 第一介電質層並料導體結構與第—㈣ 結構做電氣隔離。H 冑第一間極 β表面上方’其形成的製之頂 用者不同。在一種形式中，該成第—介電質層所使 材料形成而該第二介電質 二電質層以第-介電質 二介電質材料至少有一二介電質材料形成，該第 . 有種物理性質與該第一介電質絲钮 二。在另-種形式中，該至少—種 質： 厚度、介電質電氣導通度、質係從"電吳層 構一部表二存結構，該電荷储存結 結構包括奈米箱。在—種形式尹广亥電何錯存 鍺奈米晶避1鍺合金奈米晶體;^族包㈣奈米晶體、 體、和始夺米曰f Μ 金奈米晶體、銀奈米晶 不测’丁、木日日體中的至少一種。 儲存結構包括電荷保持介電質;例中，電荷 化物、給氧化物、錯氧化物、：保持介電質包括石夕氮 物中的至少—種 “A之氧化物、和鋁氧化 成於與第-側壁相鄰的位置二:二_結構形 一電荷儲存結構相鄰處， 針、，，。構位於與該第 相對側上。-第電何錯存結構與第一側壁 第一電何儲存結構形成於 :置處，第二_結構位於與該、:二相鄰的 處，在第二電荷儲存結構與第二侧壁2存^相鄰 ㈣例中，一第三電荷儲存結構㈣A j另一種 、。構位於項部表面與第三間極結 ：第二電何儲存 例中，僅對第—間極結構、第二間極種替代實施 構與第三閘極結構 9692I.doc 1360863 申的兩個閘極結構形成電氣接觸 對第—閉極結構、第二間極結構盘第種形式中，僅 間極結構形成電氣接觸體。在一種型結構令的-個 要被摻雜以結果具有第—種導通:文第二間極結構 第一間極蛀槿盘筮0日 種形式中， ，·口構與第_間極結構要被推雜以 導通型式，第-種導通型式與第二種_果;有第二種 '中弟-間極結構、第二間極結構、 …構各以不同的導通率摻雜。在另二間極 極結構與第二閘極砝 &歹1中，第一間 . *㈣、構被以不同㈣雜條 進订摻雜。在還有另-種形式中，半導體穿）入而 體結構，該結構有-頂部表面、-第_側壁、2一半導 側壁。-第=播間極結構的位置相鄰於第-第一閉極結構的位置相鄰於第二側壁。 極結構的位置在該頂部表面的上方。在 第二間 閘極結構、第二間極結構'血第 /式中，第- 隔離。一源極區域和一沒極區域;^ 構彼此在實體上 體社M # 。。° 半導體之相反侧從半導 “構延伸出來’其與第 千导 面垂直。在mu 稱和第一閘極結構的側 側壁，其在半=的位置，極結構的位置相鄰於第- 極結構的位置相鄰μ 源極和汲極之間。第二閘 :的位置相鄰於第二側壁，其在半導體上 隸和沒極之間，且第三閉極結構的位置在頂部表面上方 1源極和沒極之間。在另一種實施例中，一第一介電質 層裱繞半導體結構之第一側壁盥 叙货ΒΗα /、第一側壁且將半導體結構 、f香結構和第二閘極結構做電氣絕緣。—第二介電 96921.doc 1360863 質層位於半導體結構之頂部表面的上方。 第—介電質層與第二介電質層有至+ 。在—種形式中， 質，且該不同的物理性質勺 v —個不同的物理性 κ匕括介電質層厚庠人 氣導通度、或介電常數中的一個 又、"電質的電 部表面與第三閘極結構之間。在 電荷儲存結構位於頂 結構包括奈米箱，其令該奈;^形式中，該電荷儲存 晶體、石夕錯合金奈来晶體、金奈二曰：奈米晶體、錯奈米 鉑奈米晶體中的至少一種。在另μ 銀奈米晶體、與 結構是一電荷保持介電質且該電荷中’該電荷健存 物、銓氧化物、鈐氧化物^何保持7丨電質包括矽氮化 中的-種。在另一種形式令， 匕物、和紹氧化物 相鄰於第H U 何儲存結構的位置 一㈣該第一電 側上…第二電荷存 ㈣對於第-侧壁的- 电仃诨#結構的位置相 二閘極結構的位置相鄰於 、一則壁，且第 電何储存結構相對於第二側壁的—側上 :第- 令，第-電荷儲存結構與第 種實施例 其中該㈣…太 存結構包括奈米鎮， 米晶體、金夺米曰f “ 鲔-水曰曰體、矽鍺合金奈 少一種。第二 '與始奈米晶體中的至 二第一電何儲存結構與第二電荷儲 何保持介電質，其中哕 ^ 電 氧化物^ 持介電質包括矽氮化物、铪 乳化物、錯氧化物、富合 少-種。-坌1 巩化物、和鋁氧化物中的至 第二電何儲存結構的位置介於 閘極結構之間，啰笛一 f 4 月丨衣面與第二 冓之間D亥第二電荷儲存結構具有與第—電荷儲存 9692 丨.doc 1360863 結構和第二電荷儲存結構不同的至少一個性質。在一種形 式中。玄苐一閘極結構被摻雜以具有一第一導通型式且該 第一閘極結構和第二閘極結構被摻雜以具有一第二導通型 式。在另一種形式中，該第一閘極結構、第二閉極結構、 與第三閘極結構具有不同的導通度。 【實施方式】 圖1顯示半導體晶圓丨2在製造具有三個電氣隔絕閘極結 構之場效電晶體10期間的截面圖。半導體晶圓12包括基板 15,該基板可用許多種不同半導體材料中的任一種（譬如籲 SOI晶圓）或用諸如玻璃或藍寶石基板等任何機械基板來實 現。一絕緣層1 3位於基板1 5上方。絕緣層i 3可用任何氧化 物或任何氮化物或藍寶石來實現。絕緣層13上方覆有一圖 樣化鰭狀半導體結構，該結構形成鰭狀場效電晶體（Fh Field Effect Transistor，FinFET)的通道 14,該結構為矽（多 晶矽、結晶矽、非晶矽、鍺化矽、鍺或任何這些物質的組 合）。一層氧化物16位於通道14上方。氧化物16上方有一第 二閘極1 8(第一與第二閘極將在下文中描述）。在一種形式鲁 中’第二閘極1 8是多晶矽。在另一種形式中，第三閘極j 8 可為使用傳統植入製程的摻雜材料。第三閘極18的上方有 一層氧化物20。在一種形式中’氧化物2〇是二氧化矽。氧 化物層20上方有一氮化物層22〇在一種形式中，氮化物層 22是氮化矽。為了形成上述場效電晶體1〇的結構，通道μ、 · 氧化物1 6、第三閘極1 8、氧化物層20與氮化物層22係藉將 · 各材料熱長成層或沉澱各層而形成。諸層藉蝕刻各層而做 9692 丨.doc -12- 1360863 典型圖樣化以產生場效電晶體10的結構。通道14、氧化物 16、第三閘極18與氮化物層22有暴露的側壁結果。 圖2顯示圖i之場效電晶體1〇的進一步製程。在银刻之後 執仃-傳統犧牲氧化物清除步驟。通道14有侧壁，圖2的截 面圖顯㈣二側壁互相對立。氧化層卿成在通道Μ之側 壁（圖2中位於通道14相對兩側上的第一與第二側壁）上，氧 ^物層=8形成在第三閘極18之側壁上。請注意氧化物㈣ =際上是-環繞通道14的連續材料層，所以對左側與右侧 有私派、不同的編號。氧化物層26與氧化物層Μ可用熱 長成或沉澱等傳統方法形成。氧化物層26被配置的功能是' 當做-閘極介電質，且氧化物層28被配置的功能是當做第 三閘極18的絕緣體以避免與其他表面接觸。請注意有其他 材料適合使用做氧化層26與氧化物層28。譬如，可使用氮 氧化物或諸如給氧化物等任何高介電係數材料或這些材料 的組合當作氧化物層26或氧化物層28的材料。 圖3中顯示圖2之場效電晶體1〇的進一步製程。一共形多 晶石夕層30形成在現存結構的周圍。在一種形式中，多、晶矽 層30以沉澱法形成。可自由選用實施多晶矽層⑽的植入製 程。該自由選用之植入製程可採用許多種形式之一。植入 製程可用諸如L或砰等相同的或不同的物質（亦即N 型或P型)做多重植入。植入物質之劑量、方向與能量可予 以改變以界定多晶矽層30内區域到通道14左與右的導通 度。若多晶石夕層30的摻雜型式不同於第一間極㈣摻雜型 式，則這樣使通道臨限電壓可如非對稱雙閘極電晶體—般 9692l.doc 1360863 被控制。在其他形式中，可用諸如石夕錯欽氣化物、组石夕 亂化物或金屬矽化物或這些物質的組合來實現多晶矽層 3〇。一杬反射塗層（antlreflective c〇ating八尺㈡^覆蓋在多 晶石夕層30上方。在-種形式中，抗反射塗層32為氮化物。 請注意抗反射塗層32是可自由選用層。抗反射塗層32與現 存結構共形且以沉殿方式形成。一旋轉塗佈抗蝕劑層34沉 殿在場效電晶體10上達一高度，該高度在初始時大於氮化 物層22上部表面之高度’然後蝕刻回來以暴露抗反射塗層 32的一部分。該蝕刻可為等向性蝕刻或非等向性蝕刻。旋 轉塗佈抗蝕劑層34暴露位在FinFET的鰭狀區域上方之氮化 物抗反射塗層32且覆蓋抗反射塗層32的其他部分。可使用 諸如旋轉塗佈玻璃等其他旋轉塗佈材料做旋轉塗佈抗蝕劑 層34。或者，也可使用傳統旋轉塗佈法或沉澱技術來形成 旋轉塗佈抗蝕劑層34達所需高度。 圖4中顯示的是圖3之場效電晶體1〇的進一步製程。在圖4 中，場效電晶體ίο已經被蝕刻以移除八11(：層32之暴露部分 和多晶矽層30的一部分。該蝕刻結果形成了第一閘極料與 第二閘極42。此蝕刻過程可在各種不同的點停止。在另一 種形式中，使用化學機械磨光法的磨光步驟且磨光結果在 邊緣52處形成第一閘極44之上部表面。當執行蝕刻製程 時，第一閘極44與帛二閘極42之上部表面可定位在各種不 同位置處，譬如在邊緣52處或者進一步往下到像是邊緣55 處。第一閘極44與第二閘極42上部表面的位置決定了第三 閘極18與第一閘極44和第二閘極42之間各存在多少的電容 9692l.doc •14· I360863 性耦合量。所以在某些應用上一般會較希望蝕刻在第一閘 極44與第二閘極42之上部表面低於第三閘極18之下部表面 時停止。在另一些應用上會希望在第三閘極與第一和第二 閘極間各有某些電容性耦合量。所以，蝕刻製程在控制第 一閘極44和第二閘極42的大小方面提供了相當程度的彈 性。接著使用傳統濕蝕刻製程移除旋轉塗佈抗蝕劑層34與 氮化物ARC層32。此外，可藉傳統濕蝕刻製程移除氮化物 ARC層22。同時請注意當使用適當材料做旋轉塗佈抗蝕劑 層34、且使用氮化物做八尺(：層32並使用氮化物層22做其上 的電氣接觸體時，這些層可保留在原位而不必被移除。譬 如若旋轉塗佈層34被實施成旋轉塗佈介電質，且第一閘 極、第二閘極和第三閘極各為金屬矽化物或金屬，則旋轉 塗佈抗蝕劑層34、ARC層32與氮化物層22就不必被蝕刻掉。 圖5中顯示的是圖4之場效電晶體1〇的立體透視圖。第一 閘極44、第二閘極42、第三閘極18、氮化物層22與氧化物 層20已經被以微影技術晝出圖樣並使用傳統光微影技術蝕 刻完成》此圖樣化製程界定了第一閘極44、第二閘極42與 第二閘極18各自的閘極長度而顯示於圖5中。使用光敏抗蝕 劑畲作光罩’多晶矽層30、氮化物層22、氧化物層20和第 二閘極1 8的一部分被移除。氧化物層26和閘極氧化物16之 作用是在此微影技術触刻圖樣化過程甲當作蚀刻停止層。 此製程暴露一些區域，源極區域7〇與汲極區域72藉由諸如 植入法等傳統摻雜步驟形成於該等區域内。然後可進一步 實施其他的製程。譬如，各在第一閘極44、第二閘極42與 96921.doc •15· 1360863 弟二閘極18相鄰處形成侧壁分隔器（未顯示）。而且，可在暴 露之石夕帛導體表面實施金屬石夕化製程以降低石夕I面之電 阻。若如此，則此金屬矽化製程會在第一閘極料、第二閘 極42第二閘極18、源極區域70和汲極區域72之暴露部分 的上部表面處形成金屬石夕化物層。請注意本文所述的各製 程步驟之次序可以改變。譬如，形成第一閘極料與第二閘 極42所用的银刻（或取代的磨光）步驟可在上述形成分隔器 (未顯示）或金屬矽化製程之後實施。 圖6中顯禾的是場效電晶體1〇的進一步製程，其令藉沉澱# 層諸如氧化物、氮化物、低介電常數介電質或這些材料 之組合物質形成一層間介電質（interlevel dielectric ILD) 66。然後以微影技術界定並蝕刻形成ild &内之接觸孔。 接觸孔可能接達第一閘極44、第二閘極42、與第三閘極！ 8 專所有一個閘極或這二個閘極中被選擇的某些閘極。當形 成接觸孔時，一金屬接觸體64在以上述金屬石夕化步驟產生 之至屬石夕化物區域6 3處連接第一閘極4 4 β類似地，金屬接 觸體58在金屬石夕化物區域65處連接第二閘極42，且金屬接春 觸體62在金屬矽化物區域61處連接第三閘極以。可使用諸 如鶴或欽氮化物或其他材料等任何金屬做金屬接觸體58、 62與64«金屬接觸體64連接至第一偏壓電壓Vbias广金屬 接觸體58連接至第二偏壓電壓Vbias广金屬接觸體62連接 至第二偏壓電壓Vbias 此三個偏壓電壓之電壓可相同或 . 不同或只有兩個偏壓電壓相同。 · 至此已知:形成一具有三個電氣隔絕之閘極-第一閘極 96921.doc •16- 1360863 44、第二閘極42和第三閘極18_的電晶體。所有此三個間極 均可獨立控制通道14。各金屬接觸體58、62與64可個別以 不同的電塵予以偏壓以控制諸如臨限電壓、"導通”電流及 "截止"電流等特性。此外’這三個電氣隔絕之閘極的個別 摻雜濃度可藉選擇植入第一閘極44、第二閘極心和第三閘 極18之摻雜濃度而改變1雜濃度變化與型式衫了場效 電晶體10的臨限電壓特性。 圖7中顯示的是具有多重電氣隔絕之閘極的場效電晶體 的另-種形式，該電晶體額外擁有記憶儲存能力。明確地 說，晶圓HH上具有非揮發記憶區域1〇4和揮發記憶區域1〇6 且分別以電晶體1G5和電晶體1()3代表。使用純影愈姓刻 技術來界定電晶體105與103之寬度。請注意非揮發記憶區 域104内之電晶體的寬度大於揮發記憶區域1〇6内之電晶體 的寬度。也請注意形成電晶體1〇5與1〇3之電晶體堆疊：高 度相同’因為它們是從相同層形成的。在舉例顯示的形式 中’非揮發記憶區域1〇4與揮發記憶區域1〇6定位在晶圓⑻ 的不同區域内，圖甲顯示該二區域之間有間斷。基板 上覆蓋有絕緣層109。通道113位於絕緣層1〇9上方。位於通 道U3上方之介電質層⑴、位於介電質層ιΐ5上方之電荷儲 存層118、及控制㈣介電fU9形成電荷儲存結構。在一 種形式中’介電質層115和控制閘極介電質U9各為以埶長 成方式形成之氧化物。在另—種形式中，介電質層⑴是^ 氧化合物層或化學蒸氣沉澱法形成之氧化物。電荷儲存層 118係使用-層奈米箱而形成的。在一種形式中，奈米鎮是 9692l.doc 1360863 藉石夕奈米晶體體實施的。在另一種形式中，奈米鎮是藉一 層電荷儲存氮化物材料實施的。在另一種形式中，使用這 些材料的組合形成奈米簇。也可使用其他電荷儲存材料。 位於電荷儲存結構上方的是位於控制閘極.介電質丄19上方 的第三閘極123。位於控制閘極介電質119上方的是襯墊氧 化物層12 7與氮化物層13 1。 在非揮發記憶區域106内’通道111位於絕緣層} 〇9上方。 位於通道111上方之介電質層117、位於介電質層117上方之 電荷儲存層12〇、及控制閘極介電質121形成電荷儲存結鲁 構。在一種形式中，介電質層11 7和控制閘極介電質1 2 1各 為以熱長成方式形成之氧化物。在另一種形式中，介電質 層Π 7是氮氧化合物層或化學蒸氣沉澱法形成之氧化物。電 荷儲存層120係使用一層奈米簇而形成的。在一種形式中， 奈米簇是藉矽奈米晶體體實施的。在另一種形式中，奈米 藏是藉一層電荷儲存氮化物材料實施的。在另_種形式 中，使用這些材料的組合形成奈米簇。也可使用其他電荷 儲存材料。位於電荷儲存結構上方的是位於控制閘極介電_ 質12 1上方的第三閘極丨25。位於控制閘極介電質12丨上方的 是襯墊氧化物層129與介電質層133，該介電質層在一種形 式中為氮化物。 圖8中顯示的是圖7之場效電晶體的進一步製程。介電質 層135與139分別形成於通道U3與第三閘極123的側壁上。· 類似地’介電質層137與介電質層141分別形成於通道^丨丨與 · 第一閘極125的側壁上。一層奈米簇丄43使用傳統化學蒸氣 96921.doc -18- 1360863 沉澱法形成在所有暴露表面的上方。如上文所述，夺米蘇 M3可為各，不同電荷儲存材料令的任一種。位於奈米鎮· 上方的疋"電質層145。介電質層145可沉澱形成或長 · 成心成且在-種形式中為氣化物層、氧化物層或氮氧化 合物層中的一種。 圖9中表„員不的疋圖7之場效電晶體的進一步製程。可使用 一自由選項的非等向性敍刻製程以將奈米箱143從結構之 暴露水平表面上區域和在鄰接於電晶體堆疊之邊緣的垂直 方向部分區域飯刻掉。雖然圖9顯示奈米鎮⑷被沿著電晶鲁 體堆®之側壁蝕刻到_低於第三閘極123與125的點，但被 從側壁蝕刻掉之奈米蔟量為可變，從沿著氮化物層131側壁· 上的任何點下m通道113側壁上的任何點料^此姓， 刻製程產生電晶體105與103各自的獨立介電質層145血介 電々質層⑷。類似地，分別為電晶體1〇5與1〇3產生隔離的奈 米条143與144。不會發生奈米竊143的勒刻且圖9之製程不 會被實施。
圖10中顯示的是圖7之電晶體的進一步製程。在電晶體 105與103上方執行閘極層147的共形沉澱。閘極層⑷可為 多晶矽、矽鍺、金屬或其組合。位於閘極層147上方的是一 氮化物請。也可使用其他介電質取代氮化物。氮化物層 的功能是做為―紙層。此時可使用光微影技術在晶圓 101上界㈣極材料的敎範圍，第—閘極、第二閘極與第 二閘極在後續製程巾將定位於該範圍内。此時在沒有保護 氮化物層M9的閘極圖樣化區域内可執行移除氮化物層 9692l.doc -19-
1 4 9、 pa I f 1層147、氮化物層131、氧化物層127、第三閛極 /、电荷儲存結構（控制閘極介電質119、電荷儲存層118 與介電皙JS 1〗ς、 ^ ^ '曰U5) ° —紅轉塗佈抗蝕劑層151沉澱在場效電晶 體105與103上達-高度’該高度在初始時大於氮化物層149 =。卩表面之向度，然後被蝕回以暴露氮化物層149的一部 刀< °亥蝕刻可為等向性蝕刻或非等向性蝕刻。旋轉塗佈抗 姓劑層15 1暴露氮化物層149位於FinFET縛狀區域上方之部 刀並覆蓋氮化物層149的其他部分。也可使用諸如旋轉塗佈 玻璃等其他旋轉塗佈材料做旋轉塗佈抗蝕劑層151。 在圖11中，場效電晶體105與1 〇3被姓刻以移除氮化物層 149的暴露部分與閘極層147的一部分。該蝕刻結果形成了 電晶體105之第一閘極153與第二閘極&，並形成電晶體 103之第閘極157與第二閘極159。同樣地，此蝕刻步驟可 在與圖11中所明確顯示之點不同的各種不同點停止。然後 以傳統方式移除旋轉塗佈抗蝕劑層丨5丨與氮化物層149的剩 餘邙伤。但凊注意若使用諸如旋轉塗佈玻璃等適當材料做 旋轉塗佈抗蝕劑層151，則旋轉塗佈抗蝕劑層151、氣化物 層149與氮化物層131可保留在原處。在另一種形式中，氮 化物層131可用移除氮化物層149相同的步驟加以移除。因 為非揮發記憶區域104之電晶體105與揮發記憶區域1〇6之 電晶體103有相同的垂直尺寸，所以電晶體1〇5與電晶體1〇3 除了上文所述閘極寬度不同之外有相同的輪廓。 圖12中顯示的是圖11中所示各電晶體1〇3與電晶體ι〇5現 狀之頂視平面圖。閘極接觸區域17 3位於電晶體1 〇 $之氮化 9692 丨.doc -20- 1360863 物層13 1上方》閘極接觸區域175與閘極接觸區域177分別位 於電晶體103之第一閘極157與第二閘極159上方。源極接觸 區域179位於電晶體1〇5之源極擴散區域上方，且汲極接觸 區域181位於電晶體105之汲極擴散區域上方。類似地，源 極接觸區域185位於電晶體ι〇3之源極擴散區域上方，且汲 極接觸區域183位於電晶體1〇3之汲極擴散區域上方。從該 頂視圖可見，揮發記憶區域丨〇6之電晶體i 〇3的通道寬度一 般小於非揮發記憶區域！ 〇4之電晶體i 〇5的通道寬度，但是 並非一定要小於。形成非揮發儲存電晶體之電晶體1〇5的寬 度主要由接達第三閘極123之電氣接觸所需之面積量界 定。電晶體105之寬度也根據電荷儲存層118内使電晶體1〇5 成為非揮發所4之電何储存面積量決定。換言之，電晶體 105之寬度需要大得足以使電荷儲存層i 18當偏壓電壓從第 三閘極123移除時可保持其電荷。相反地，電晶體1〇3可有 較乍的寬度，因為儲存特性受通道丨丨丨側壁内的電荷儲存元 件144界定而不受電荷儲存層12〇之寬度影響。額外接達電 晶體103之電氣接觸體不一定要在頂部第三閘極處製 作。所以，電晶體103之高度與介電質層137和介電質層 之電氣特性控制了電晶體1〇3之記憶保持特性，而電晶體 105之寬度與控制閘極介電質119和介電質層⑴之電氣特 性控制了電晶體1 0 5之記憶保持特性。可能尚有可自由選擇 的額外接觸體（未顯示）接達第一閑極153、第二閘極⑸和 三問極123等各閘極。可使料些接觸體來實施對通道113 及114、電㈣存層143之奈錢層和電荷儲存層144之夺米 96921.doc 簇層或電荷儲存層118及電荷儲存層12〇做額外偏壓。 圖13中顯示的是電晶體105與1〇3之橫截面圖，其中矽化 接觸通路已經形成以接達電晶體之預定閘極。單一閘極接 觸體接達非揮發記憶區域1 〇4内的各電晶體。非揮發記憶區 域1 04内各電晶體被接觸之閘極是位於通道上方之上位或 頂部閘極。兩個閘極接觸體接達揮發記憶區域1〇6内的各電 曰曰體。揮發記憶區域1〇6内各電晶體被接觸之閘極鄰接於電 晶體之側壁。在接觸由接觸體173、175與177形成的地方， 位於下方之金屬矽化物區域165、167與171分別被形成。藉 著以單一電壓程式化（亦即寫入）偏壓非揮發記憶區域104内 的各電晶體之位於通道上方的閘極並使通道寬得足以保持 奈米簇143層内之電荷，電晶體105之功能得以做為非揮發 έ己憶儲存元件。類似地，當電晶體1 〇3在鄰接於通道1丨丨之 側壁的兩個閘極被偏壓時，電晶體103之奈米簇144層被充 電且在第一閘極15 7或第二閘極15 9處之電源被更新或維持 期間保持充電狀態。 圖丨4中顯示的是具有兩種不同型式記憶體的積體電路 18〇 ’該兩種記憶體係使用相同製程實施以實現像非揮發記 憶區域104内之電晶體105的電晶體、像圖1-6中在區域1〇5 内實施之具有三閘極電晶體之電晶體10的電晶體、和像揮 發記憶區域106内之電晶體103的電晶體。雖然諸如動態隨 機存取記憶體等動態記憶體被標示為揮發記憶區域1〇6之 儲存裝置型式，但其他型式的揮發記憶體陣列也可被實 施’譬如快閃記憶體陣列。包括邏輯、類比與數位電路等 %92 丨.doc • 22- 1360863 任何種類的電路均可使 使用二閘極電晶體在區域105内實 把。任何其他各種不同雷 、 杈，，且（未顯示）均可包含於積體電 路180内，該等電路楛 慣藤电 、，使用本文所述二種電晶體（非揮發 記憶體三閘極電晶體、揮 坪货d 體二閘極電晶體、盥非圮 憶體三問極電晶體結構)功能中的-種或全部三種。很清楚 的是僅使關14中所示三種電路㈣中㈣可 實施一積體電路。 至此很清楚知道本發明提出一種具有三個獨立閘極之電 晶體結構。在一種形式中，t晶體可被組態以提供一通用 記憶體結構中可使用相同半導體製程在一相同積體電 路上實施非揮發與揮發記顧單元。本文所述之電晶體結 構的多功能可大Μ低在相同晶片上製造諸如具有R0M或 SRAM之Fiash或DRAMff己憶體的成本。傳統上需要在積體 電路上使用不同的製程步驟來實施不同的記憶體模組。藉 著擁有三個獨立的閘極’電晶體可發揮作用以提供三種不 同的通道電氣調變來源。有了對通道電流較多的控制，就 可更精確地控制電晶體臨限電壓（亦即可藉改變閘極組合 之偏壓而動態地提升或降低臨限電壓）。電晶體臨限電壓也 可根據被使用做通道與二個閘極介面之閘極介電質的尺寸 與種類及根據閘極之尺寸與摻雜和閘極之材料成分而設 疋。第二閘極可用傳統植入技術或就地摻雜技術做摻雜。 第一與第二閘極可用相同或不同元素以傾角植入技術做植 入。第一與第二閘極也可做就地摻雜以獲得相同的導通度。 藉著使用一種型式的記憶儲存方式給電荷儲存層丨丨8而 96921.doc -23· 1360863 使用不同型式的記憶儲存方式給電荷儲存層i43，就可產生 不同的讀取和寫人記憶機制1確地說，f晶體105可使用 位於上方之第三閘極利用熱載子注人⑽咖⑼⑽ HCI)被編長（亦即寫入），且藉源極與汲極間之載子導通做 随通或熱電洞載子而抹除。電晶體1()3可使用第—閘極Η? 與第一閘極1 59藉著利用隧通或暖通道編程而被編程。電晶 體103可藉使用從三個間極中的任一個做隧通或藉適當地 偏壓來源沒極而被抹除。 在上文的發明說明中，係參考特定的實施例描述本發 明但本領域中的—般技術者會知道可有各種不同的修改 與改變而不背離下文㈣請專利範圍中所陳述之本發明的 範脅。譬如，錢化物層22下方之通道14與第三閘極18可 在上文所述之蝕刻與清淨步驟之後於側壁邊緣處做成凹 陷。在圖8令形成電荷儲存層143之後，晶圓1〇1的一部分可 被遮罩住且阳圓ιοί未被遮罩住之區域的電荷儲存層143 電為層145可被移除。這些區域可用來做在周圍（側面 與頂部）沒有儲存位置的電晶體。此外’電晶體1〇3之第三 閘極堆豐結構的蝕刻可被實施以移除電荷儲存層143、介電 貝曰145 "電質層133、氧化物層129、第三閘極125、介 電質層14卜控制閘極介電質121、與電荷儲存層12〇。其結 果的結構是具有多重側面通道之電晶體。而且，三個閘極 區域可有不同的材料性質，纟中某些閘極區域是多晶矽而 其他閘極區域是金屬的。 所以’本文的陳述與圖式應被視為舉例說明而非限制， 9692I.doc 1360863 且所有這些修改應被視為包含於本發明之範疇内。上文根 月確的實施例描述本發明之優點、其他好處、和問題解 、、法但3亥等優點、好處、或解决方法以及將發生或宣 :會造成任何優點、好處、或解決方法的任何元件應不被 解項為任何或所有申請專利範圍之關鍵、必要'或重要機 二本文t所使用的"包含"或”包括"或其任何其他變 體：在涵蓋非排他的包括，所以包括一列示元件的製程、 、'物件或叹備不僅包括所列示的該等元件，還包括 顯列示或此類製程、方法、物件、或設備固有的· 【圖式簡單說明】 本發明藉附圖做舉例說明，但不受附圖範例的限制 附圖中類似的編號表示類似的^件，且諸圆式中： 體圖w以截面圖顯示根據本發明第一種形式的場效電晶 圖5以立體透視圖顯示圖4之場效電晶體； 垃圖6以截面圖顯示圖4之場效電晶體，該電晶體具有電氣· 接點； 、男€軋 圖7_11以截面圖顯+丄々 羝口 *.、“使用本發明第二種形式之 體電晶體與非揮發記情 皁發5己憶 6隐體電晶體的記憶體應用例； 圖12以頂視平面圖海+闽 圖員不圖11之揮發記憶體電 發記憶體電晶體； 體和非揮 圖13以截面圖顯+ js|彳， 、圖11之揮發記憶體電晶體和 憶體電晶體，該等電晶體有電氣接點；且 揮發兄 9692l.doc -25- 1360863 圖14以平面圖顯示藉使用圖11之揮發記憶體電晶體和非 揮發記憶體電晶體來實現不同種類的記憶體陣列之積體電 路。 熟習本技術領域者會知道圖式中元件的顯示只是為了說 明的簡化與清晰，而不一定依照比例繪製。譬如，圖式中 某些元件的尺寸可能相對於其他元件做誇大顯示以俾益對 本發明實施例的較佳了解。 【主要元件符號說明】 10 場效電晶體 12 半導體晶圓 13 絕緣層 14 通道 15 基板 16 氧化物 18 閘極 20 氧化物層 22 氮化物抗反射塗層（ARC) 26 氧化物層 28 氧化物層 30 多晶矽層 32 抗反射塗層 34 旋轉塗佈抗蝕劑層 42 問極 44 閘極 96921.doc -26- 1360863 52 邊緣 55 邊緣 58 金屬接觸體 61 金屬矽化物區域 62 金屬接觸體 63 金屬矽化物區域 64 金屬接觸體_ 65 金屬矽化物區域 66 層間介電質（ILD) 70 源極區域 72 汲極區域 101 晶圓 103 電晶體 104 非揮發記憶區域 105 電晶體 106 揮發記憶區域 107 基板 109 層 111 通道 113 通道 114 通道（多數） 115 介電質層 117 介電質層 118 電荷儲存層
96921.doc ·27· 1360863 119 控制閘極介電質 120 電荷儲存層 121 控制閘極介電質 123 閘極 125 閘極 127 氧化物層 129 氧化物層 131 氮化物層 133 介電質層 135 介電質層 137 介電質層 139 介電質層 141 介電質層 143 電荷儲存層 144 電荷儲存元件 145 介電質層 146 介電質層 147 閘極層 149 氮化物層 151 旋轉塗佈抗触劑層 153 閘極 155 閘極 157 閘極 159 閘極 96921.doc •28 1360863 165 167 171 173 175 177 179 180 181 183 185 金屬^夕化物區域 金屬*2夕化物區域 金屬^夕化物區域 閘極接觸區域 閘極接觸區域 閘極接觸區域 源極接觸區域 電路 汲極接觸區域 汲極接觸區域 源極接觸區域
96921.doc -29

Claims (1)

1360863 (―--— 第〇93丨33254號專利申請案 々。年5月丨丨日脩太 中文㈣專利範g替換本(1G吟5卩）L---一 又’ ♦ 十、申請專利範圍： 1. 一種製造一半導體裝置之方法，包括： 形成一半導體通道結構，該半導體通道結構包括〜頂 部水平表面、一第一垂直側壁、與一和該第一側壁相訝 之第二垂直側壁； 、 形成一第一閘極結構與一第二閘極結構，其中該第〜 閘極結構的位置側面地相鄰於及實質地沿著該第—垂直 側壁，且该第二閘極結構的位置側面地相鄰於及實質地 沿著該第二垂直側壁； 形成一實質地沿著且位於該頂部水平表面上方之第= 閑極結構，λ中該第一間極結構、該第二閉極結構、與 该第三閘極結構彼此在實體上隔離；其中形成該第〜閘 極結構與該第二閘極結構進一歩包括在該第三閘極結^ 和一基板二者上方沉澱一層閘極材料，及移除該層閘極 材料位於該第三閘極結構上方之一部分以形成該 極結構與該第二閘極結構；及 f +形成一電荷儲存層，介於該半導體通道結構及包含誃 第H結構、該第二閘極結構及該第三閘極結構的群 組中至少—閘極結構之間。 2 ·如請求項1 $ f 方法，其中形成該第一閘極結構與該第二間 ^ 構進歩包括在移除該層閘極材料位於該第三閘極 a冓上方之该部分後，圖樣化製成該第一閘極結構及該 第二閘極結構。 3.如請求項1 $ 法’進一歩包括形成一位於該基板上方的 9692丨-1000511.doc B60863 ；ί -V 大致平坦層達到一低於該層問極材料的一頂部表面之古 度，且使用該大致平坦表面當做—遮㈣㈣ 閘極結構與該第二閘極結構。 一種半導體裝置，包括： 與 半導體結構，包括一頂部表面、一第一側壁 和該第一側壁相對之第二側壁； 一位於相鄰於該第-側壁之第-閘極結構； -位於相鄰於該第二側壁之第二閘極結構； -位於在該頂部表面上方之第三祕結構； -位於該頂部表面及該第三間極結構之間的第 儲存結構；其中該第—閘極結構、該第二祕結構、^ 该第二閘極結構彼此在實體上隔離；及 -位於相鄰於該第一側壁之第二電荷儲存結構，1中 該第-閘極結構在該第二電荷儲存結構相對於該第一側 壁的一側上相鄰於該第二電荷儲存結構。 如請求項4之半導體裝置，進一歩包括： 一源極區域和—㈣區域，該二區域在該半導體結構 之相對兩側上從該半導體結構延伸出來，其與該第一閘 極結構和該第二閘極結構的側面垂直； 其中該第一閘極結構位於相鄰於該第一側壁位於該半 導體結構一介於該源極與該汲極之間的位置處； 其中該第二閘極結構的位於相鄰於該第二側壁位於該 半導體結構-介於該源極與該沒極之間的位置處；且 其中該第三閘極結構的位於在該頂部表面上方介於該 96921-1000511.doc •1· ⑤ 1360863 源極與該汲極之間。 如請求項4之半導體裝置，進一歩包括： -第-介電質層，該第-介電質層環繞該半導體結構 之-亥第側壁與該第一側壁’且電氣隔離該半導體結構 與該第一閘極結構和該第二閘極結構；及 一位於該半導體結構之該頂部表面上方之第二介電質 層，該第-介電質層與該第二介電質層包括至少一個不 同的物理性質。 7. 如請求項4之半導體裝置’其中該 @ 豕至；一個不同的物理性 質包含介電質層厚度、.介電質導 者 %貝等電性或介電常數中之一 如巧求項4之半導體裝置，其中該筮^ 太半f^ a第一電何儲存結構包含 -未叢集’其中該奈米叢集包含矽 晶、石夕鍺合金奈米結晶、 …卡…鍺奈米結 奈米結晶中至少一者。卡結晶、銀奈米結晶及始 9，如請求項4之半導體裝置，其 -電荷擁取介電質，其包含氮二電荷―構包含 富含石夕之氧化物及氧化財至少—者魏給、乳化錯、 10·如請求項4之半導體裝置，進—歩包括. 一位於相鄰於該第二側壁之 I . 二間極結構在該第三電荷儲存結存結構，該第 一側上相鄰於該第三電荷館存^ &㈣二側壁的 9692 M00051I.doc
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