CN100433363C - 具有三个电气隔离的电极的晶体管及形成方法 - Google Patents
具有三个电气隔离的电极的晶体管及形成方法 Download PDFInfo
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Abstract
形成了一种晶体管(10),其具有三个分离可控的栅极(44、42、18)。这三个栅极区域可进行不同的电气偏置,并且该栅极区域可以具有不同的传导属性。沟道侧壁上的介质可以不同于沟道上面的介质。选择性地实现针对源极、漏极和三个栅极的电接触。通过包括与晶体管沟道相邻的电荷存储层,诸如纳米团簇(143、144),并且经由三个栅极区域控制该电荷存储层,使用相同的工艺实现了易失和非易失存储器单元,产生了通用的存储器工艺。在被实现作为易失单元时,晶体管的高度和沟道侧壁的介质的属性控制存储保持特性。在被实现作为非易失单元时,晶体管的宽度和上面的沟道介质的特性控制存储保持特性。
Description
技术领域
本发明涉及半导体,更具体地,涉及用于存储器的晶体管。
背景技术
随着晶体管的几何尺寸引人注目地减小到亚微米的尺寸,由于较小尺寸所产生的对器件物理的影响,迫使晶体管的结构改变。特别地,晶体管的沟道变得非常窄。由于小的沟道长度,晶体管的漏极开始不利地控制沟道中的电流传导,而非由栅极作为控制机制。该问题已得到良好的证明,并且通常被称为短沟道效应。为了减小短沟道效应的问题,其他人提出了这样的晶体管结构,其中将栅极安置在沟道的反面。尽管该方法引人注目地减小了短沟道效应问题,但是由于使反面安置的栅完全对准对于批量生产而言是难于实现的,因此批量制造该结构的能力是成问题的。作为替换方案,提出了一种晶体管结构,其具有由栅极围绕的垂直的硅沟道,以减小短沟道效应。该晶体管被称为数个不同的名称,包括FINFET和双栅晶体管。尽管FINFET晶体管的某些实现方案具有单一的栅极,但是其它的实现方案使用了两个电气隔离的栅极,用于改善包括晶体管阈值电压控制的性能。为了使沟道周围的两个栅极电气隔离,使用了化学机械抛光(CMP)或抛光步骤。由于这些晶体管的窄的鳍式结构,抛光步骤趋于引起不均匀的抛光或者晶体管器件的“凹陷”。
减小的晶体管结构还带来了集成非易失(例如,只读存储器和闪存Flash)和易失(DRAM和SRAM)存储器阵列的能力,用于片上系统(SOC)应用。典型地,需要利用不同的工艺实现的不同的晶体管结构,用于实现非易失和易失存储器阵列。例如,Flash存储器晶体管是利用浮栅结构实现的,其位于沟道和控制栅极之间。相反地,DRAM存储器晶体管是利用平面晶体管实现的,其控制深槽电容器。该平面晶体管使用单一平面的沟道,其使源极和漏极分离,并且由上面的栅极控制。由于必须实现不同的工艺和结构,因此对在单一的集成电路上实现易失和非易失存储器阵列的需要,增加了相当大的成本。此外,由于所需要的不同的晶体管结构,相同的集成电路上的晶体管的工作特性可能明显不同。
附图说明
将借助于示例描述本发明,但是其不限于附图,在附图中相似的参考符号表示相似的元件,并且其中:
图1~4以剖面图的形式说明了根据本发明的第一形式的场效应晶体管;
图5以透视图的形式说明了图4的场效应晶体管;
图6以剖面图的形式说明了具有电接触的图4的场效应晶体管;
图7~11以剖面图的形式说明了使用第二形式的场效应晶体管的易失存储器晶体管和非易失存储器晶体管的存储器应用;
图12以顶部平面图的形式说明了图11的易失存储器晶体管和非易失存储器晶体管;
图13以剖面图的形式说明了具有电接触的图11的易失存储器晶体管和非易失存储器晶体管;并且
图14说明了通过使用图11的易失存储器晶体管和非易失存储器晶体管实现不同类型的存储器阵列的集成电路的平面图。
本领域的技术人员应认识到,图中的元件被说明用于简化和清晰的目的,并且不必依比例绘制。例如,图中某些元件的尺寸可以相对于其它的元件放大,以协助理解本发明的实施例。
具体实施方式
图1中说明的是场效应晶体管10的制造阶段中的半导体晶片12的剖面图,该场效应晶体管10具有三个电气隔离的栅极结构。半导体晶片12包括基板15,其是通过多种半导体材料中的任何材料实现的,诸如SOI晶片,或者通过任何机械基板实现,诸如玻璃或蓝宝石基板。在基板15上面是绝缘层13。绝缘层13可以通过任何氧化物或任何氮化物或蓝宝石实现。在绝缘层13上面是构图的鳍式半导体结构,其形成了FinFET(鳍式场效应晶体管)的沟道14,其是硅(多晶硅、晶体硅、各向异性硅、SiGe、锗、或任何这些材料的组合)。在沟道14上面是氧化物16。在氧化物16上面是第三栅极18(第一和第二栅极在下面标记)。在一个形式中,第三栅极18是多晶硅。在另一形式中,第三栅极18可以是使用传统的注入工艺的掺杂材料。在第三栅极18上面是氧化物层20。在一个形式中,氧化物20是二氧化硅。在氧化物层20上面是氮化物层22。在一个形式中,氮化物层22是氮化硅。为了形成所说明的场效应晶体管10的结构,沟道14、氧化物16、第三栅极18、氧化物层20和氮化物层22中的每一个,通过指定材料的层的热生长或者层的淀积形成。传统地通过刻蚀层对该层构图,以产生场效应晶体管10的结构。结果沟道14、氧化物16、第三栅极18和氮化物层22具有暴露的侧壁。
图2说明的是图1的场效应晶体管10的进一步的处理。在刻蚀之后执行牺牲氧化物清洗步骤。沟道14具有侧壁,其在图2的剖面图中被说明为是相对的。在沟道14的侧壁(在沟道14的相对侧面上的图2中的第一和第二侧壁)上形成了氧化物层26,并且在第三栅极18的侧壁上形成了氧化物层28。应当理解,氧化物层26实际上是围绕沟道14的连续材料层,并且因此未将不同的参考数字分配给左侧和右侧。氧化物层26和氧化物层28可以以传统的方式热生长或淀积。氧化物层26被提供用作栅介质,而氧化物层28被提供用作用于阻碍第三栅极18同其它表面接触的隔离。应当理解,其它的材料也适于用作氧化物层26和氧化物层28。例如,氧氮化物或任何高介电常数的材料,例如,氧化铪,或者这些材料的组合等,可以用作用于每个氧化物层26和氧化物层28的材料。
图3中说明的是图2的场效应晶体管10的进一步的处理。在现有结构周围形成了共形多晶硅层30。在一个形式中,多晶硅层30是淀积的。可以实现任选的多晶硅层30的注入。该任选的注入可以采用数种形式中的一种。该注入可以采用多种注入材料,其具有相同的或不同的物质(即,N型和P型),诸如硼、磷或砷等。注入物质的剂量、方向和能量可以改变,以针对沟道14的左侧和右侧,定义多晶硅层30中的区域的传导率。如果多晶硅层30的掺杂类型不同于第一栅极18的掺杂,则允许控制沟道阈值电压,如同非对称双栅晶体管。在其它形式中,多晶硅层30可以通过其它的材料实现,诸如锗硅、氮化钛、氮化钽硅或硅化物或者这些材料的组合。在多晶硅层30上面是抗反射涂层(ARC)层32。在一个形式中,ARC层32是氮化物。应当理解,ARC层32是任选的层。ARC层32对于现有的结构是共形的,并且是淀积的。将旋涂光刻胶层34淀积到场效应晶体管10上,其高度为,初始大于氮化物层22的上表面的高度,并且随后被回刻,以暴露一部分ARC层32。该刻蚀可以是各向同性或各向异性刻蚀。旋涂光刻胶层34使FinFET的鳍式区域上面的氮化物ARC层32暴露,同时覆盖ARC层32的其它部分。其它的旋涂材料,诸如旋涂玻璃,可用于旋涂光刻胶层34。可替换地,可以使用传统的旋涂或淀积技术使旋涂光刻胶层34形成为所需的高度。
图4中说明的是图3的场效应晶体管10的进一步的处理。在图4中,场效应晶体管10被刻蚀,以移除ARC层32的暴露部分和一部分多晶硅层30。该刻蚀导致了第一栅极44和第二栅极42的形成。该刻蚀可以停止于不同的点。在另一形式中,使用CMP抛光步骤,并且该抛光导致了第一栅极44的上表面处于边缘52。在执行刻蚀时,可以使第一栅极44和第二栅极42的上表面位于不同的位置,诸如位于边缘52,或者进一步往下,诸如位于边缘55。第一栅极44和第二栅极42的上表面的位置确定了在第三栅极18和每个第一栅极44和第二栅极42之间存在多大的容性耦合。因此,在某些应用中,通常较理想的是,当第一栅极44和第二栅极42的上表面低于第三栅极18的下表面时停止刻蚀。在其它应用中,理想的是在第三栅极和每个第一栅极和第二栅极之间具有一定量的容性耦合。因此,该刻蚀在第一栅极44和第二栅极42的尺寸控制中,提供了相当大的灵活度。使用传统的湿法刻蚀步骤,移除旋涂光刻胶层34和氮化物ARC层32。此外,可以通过传统的湿法刻蚀步骤,移除氮化物ARC层22。而且,应当注意,当适当的材料用于旋涂光刻胶层34,并且氮化物用于ARC层32和氮化物层22,用于实现同其的电接触时,可以使这些层保留在适当的位置,而非将其刻蚀掉。例如,如果旋涂光刻胶层34被实现作为旋涂介质,并且每个第一栅极,第二栅极和第三栅极是硅化物或金属时,不需要将旋涂光刻胶层34、ARC层32和氮化物层22刻蚀掉。
图5中说明的是图4的场效应晶体管10的透视图。使用传统的光刻方法对第一栅极44、第二栅极42、第三栅极18、氮化物层22和氧化物层20进行光刻构图和刻蚀。该构图定义了关于图5中说明的第一栅极44、第二栅极42和第三栅极18的栅长度。使用光刻胶作为掩膜,移除部分多晶硅层30、氮化物层22、氧化物层20和第三栅极18。氧化物层26和栅氧化物16在该光刻构图的刻蚀过程中用作刻蚀阻挡层。该处理使这样的区域暴露,即其中通过传统的掺杂步骤,诸如注入,形成了源极区域70和漏极区域72。可以实现另外的处理。例如,可以形成侧壁隔层(未示出),其同每个第一栅极44、第二栅极42和第三栅极18相邻。而且,可以实现暴露的硅半导体表面的硅化,以减少硅表面的电阻率。如果这样操作,则该硅化将在第一栅极44、第二栅极42、第三栅极18、源极区域70和漏极区域72的暴露部分的上表面处形成硅化层。应当注意,可以改变此处描述的工艺步骤的顺序。例如,用于形成第一栅极44和第二栅极42的刻蚀(或者可替换的抛光)可以在上文描述的形成隔层(未示出)或硅化之后实现。
图6中说明的是场效应晶体管10的进一步的处理,其中通过淀积诸如氧化物、氮化物、低介电常数的介质或者这些材料的组合的层,形成了夹层介质(ILD)66。ILD 66中的接触孔是光刻定义和刻蚀的。该接触孔可以针对全部三个第一栅极44、第二栅极42和第三栅极18,或者仅针对这三个栅极中的所选择的栅极。当形成接触孔时,金属接触64在通过上文所述的硅化步骤产生的硅化物区域63处连接第一栅极44。相似地,金属接触58在硅化物区域65处连接第二栅极42,并且金属接触62在硅化物区域61处连接第三栅极18。任何金属可用于金属接触58、62和64,诸如钨或氮化钛或者其它金属。金属接触64连接到第一偏置电压VBIAS1。金属接触58连接到第二偏置电压VBIAS2。金属接触62连接到第三偏置电压VBIAS3。这三个偏置电压可以是相同的电压或者可以是不同的电压或者仅有两个偏置电压是相同的。
晶体硅被形成为具有三个电气隔离的栅极,第一栅极44、第二栅极42和第三栅极18。所有这三个栅极可以独立地控制沟道14。每个金属接触58、62和64可以分离地偏置有不同的电压电位,以控制诸如阈值电压、“开启”电流和“截止”电流的特性。此外,通过改变所选择的用于注入到第一栅极44、第二栅极42和第三栅极18的掺杂浓度,可以改变这三个电气隔离的栅极的每一个的掺杂浓度。该掺杂浓度变化和类型确定了场效应晶体管10的阈值电压特性。
图7中说明的是具有多个电气隔离的栅极的场效应晶体管的另一形式,其额外地具有存储器存储能力。特别地,在晶片101上提供了非易失区域104和易失区域106,并且其分别由晶体管105和晶体管103表示。使用光刻和刻蚀定义晶体管105和103的宽度。应当注意,非易失区域104中的晶体管的宽度大于易失区域106中的晶体管的宽度。还应当注意,形成晶体管105和103的晶体管叠层的高度是相同的,这是因为它们是由相同的层形成的。在所说明的形式中,非易失区域104和易失区域106被安置在晶片101的不同的区域中,其由两个区域之间的破隙表示。向基板107提供上面的绝缘层109。沟道113位于绝缘层109上面。电荷存储结构由沟道113上的介质层115、介质层115上的电荷存储层118和控制栅介质119形成。在一个形式中,每个介质层115和控制栅介质119是氧化物,并且是热生长的。在另一形式中,介质层115是氧氮化物层或者CVD形成的氧化物。通过使用纳米团簇层,形成了电荷存储层118。在一个形式中,由硅纳米晶体实现纳米团簇。在另一形式中,由电荷俘获氮化物材料层实现纳米团簇。在另一形式中,使用这些材料的组合形成纳米团簇。还可以使用其它的电荷存储材料。在电荷存储结构上面是第三栅极123,其在控制栅介质119上面。在控制栅介质119上面是衬垫氧化物层127和氮化物层131。
在非易失区域106中,沟道111在绝缘层109上面。电荷存储结构由沟道111上的介质层117、介质层117上的电荷存储层120和控制栅介质121形成。在一个形式中,每个介质层117和控制栅介质121是氧化物,并且是热生长的。在另一形式中,介质层117是氧氮化物层或者CVD形成的氧化物。通过使用纳米团簇层,形成了电荷存储层120。在一个形式中,由硅纳米晶体实现纳米团簇。在另一形式中,由电荷俘获氮化物材料层实现纳米团簇。在另一形式中,使用这些材料的组合形成纳米团簇。还可以使用其它的电荷存储材料。在电荷存储结构上面是第三栅极125,其在控制栅介质121上面。在控制栅介质121上面是衬垫氧化物层129和介质层133,其在一个形式中是氮化物。
图8中说明的是图7的场效应晶体管的进一步的处理。分别在沟道113和第三栅极123的侧壁上形成介质层135和139。相似地,分别在沟道111和第一栅极125的侧壁上形成介质层137和介质层141。使用传统的CVD方法,在全部的暴露表面上形成纳米团簇层143。如上文所提及的,纳米团簇143可以是多种不同电荷存储材料中的任何材料。在纳米团簇143上面是介质层145。该介质层145可以是淀积或生长的,并且在一个形式中,其是氮化物层、氧化物层或氧氮化物层中的一个。
图9中说明的是图7的场效应晶体管的进一步的处理。使用任选的各向异性刻蚀,从该结构的暴露的水平表面上,并且部分地在同晶体管叠层的边缘相邻的垂直方向中,刻蚀掉纳米团簇143的区域。尽管图9说明了,沿晶体管叠层的侧壁,直到低于第三栅极123和125的点,刻蚀纳米团簇143,但是自侧壁刻蚀的纳米团簇量可以从沿氮化物层131的任何点变化到沿沟道113的侧壁的任何点。该刻蚀分别为晶体管105和103产生了分离的介质层145和介质层146。相似地,分别为晶体管105和103产生了分离的纳米团簇143和144。此外,未发生纳米团簇143的刻蚀,并且未实现图9的处理。
图10中说明的是图7的晶体管的进一步的处理。在晶体管105和103上进行栅极层147的共形淀积。栅极层147可以是多晶硅、锗硅、金属或其组合。在栅极层147上面是氮化物层149。可使用其它的介质替换氮化物。该氮化物层149用作ARC层。此时,可以使用光刻方法在晶片101上定义栅极材料的预定区域,随后将在其中安置第一栅极、第二栅极和第三栅极。此时,在不存在保护氮化物层149的栅极构图的区域中,可以执行氮化物层149、栅极层147、氮化物层131、氧化物层127、第三栅极123和电荷存储结构(控制栅介质119、电荷存储层118和介质层115)的移除。将旋涂光刻胶层151淀积到场效应晶体管105和103上,其高度为,初始大于氮化物层149的上表面的高度,随后被回刻蚀以暴露一部分氮化物层149。该刻蚀可以是各向同性或各向异性刻蚀。旋涂光刻胶层151使FinFET的鳍式区域上面的氮化物层149暴露,同时覆盖氮化物层149的其它部分。其它的旋涂材料,诸如旋涂玻璃,可用于旋涂光刻胶层151。
在图11中,场效应晶体管105和103被刻蚀,以移除氮化物层149的暴露部分和一部分栅极层147。该刻蚀导致了晶体管105的第一栅极153和第二栅极155的形成,并且导致了晶体管103的第一栅极157和第二栅极159的形成。再次地,该刻蚀可以停止于除了图11中说明的特定的点以外的不同的点。以传统的方式移除剩余的旋涂光刻胶层151和氮化物层149。然而,应当注意,如果适当的材料,诸如旋涂玻璃,用于旋涂光刻胶层151,则可以将旋涂光刻胶层151、氮化物层149和氮化物层131保留在适当的位置。在另一形式中,可以通过与移除氮化物层149的步骤相同的步骤,移除氮化物层131。由于非易失区域104的晶体管105具有与易失区域106的晶体管103相同的垂直尺寸,因此除了前面提及的栅极宽度的差异以外,晶体管105和晶体管103的外形是相同的。
图12中说明了图11表示的目前状态下的每个晶体管103和晶体管105的顶部平面图。栅极接触区域173位于晶体管105的氮化物层131上。栅极接触区域175和栅极接触区域177分别位于晶体管103的第一栅极157和第二栅极159上面。源极接触区域179位于晶体管105的源极扩散区域上面,并且漏极接触区域181位于晶体管105的漏极扩散区域上面。相似地,源极接触区域185位于晶体管103的源极扩散区域上面,并且漏极接触区域183位于晶体管103的漏极扩散区域上面。如由顶部示图所看到的,易失区域106的晶体管103的沟道宽度典型地小于非易失区域104的晶体管105的沟道宽度,但是没有必要必须比其小。形成非易失存储晶体管的晶体管105的宽度主要由所需用于实现同第三栅极123的电接触的面积量定义。晶体管105的宽度还依赖于用于使晶体管105是非易失的电荷存储层118中所需的电荷存储面积量。换言之,晶体管105的宽度需要是足够大的,用于在从第三栅极123移除偏置电压时,使电荷存储层118保留其电荷。相反地,由于存储特性由沟道111的侧壁中的电荷存储元144定义,而非由电荷存储层120的宽度定义,因此晶体管103可以具有较窄的宽度。此外,不必在顶部的第三栅极125处实现针对晶体管103的电接触。因此,晶体管103的高度以及介质层137和介质层146的电学特性,控制晶体管103的存储保持特性,而晶体管105的宽度以及控制栅介质119和介质层115的电学特性控制晶体管105的存储保持特性。任选地,可以存在额外的针对每个第一栅极153、第二栅极155和第三栅极123的接触(未示出)。该接触可用于实现沟道113和114、电荷存储层的纳米团簇层143和电荷存储元件的纳米团簇层144、或者电荷存储层118和电荷存储层120的额外的偏置。
图13中说明的是晶体管105和103的截面图,其中形成了针对预定的晶体管栅极的硅化接触过孔。针对非易失区域104中的每个晶体管,实现了单一的栅极接触。所接触的用于非易失区域104中的每个晶体管的栅极,是上面的栅极或者顶部栅极,其位于沟道上面。针对易失区域106中的每个晶体管,实现了两个栅极接触。所接触的用于易失区域106中的每个晶体管的栅极,同晶体管的侧壁相邻。在通过接触173、175和177实现接触的情况中,分别形成了下面的硅化物区域165、167和171。通过编程(即,写),即利用针对沟道上面的栅极的单一的电压,使非易失区域104中的每个晶体管偏置,并且使沟道是足够宽的,以使电荷保持在纳米团簇层143中,晶体管105用作非易失存储器存储元件。相似地,在同沟道111的侧壁相邻的两个栅极处使晶体管103偏置时,晶体管103的纳米团簇层144被充电,并且在第一栅极157或第二栅极159处刷新功率或维持功率时保持电荷。
图14中说明的是集成电路180,其具有两个不同类型的存储器,其是使用同用于实现如非易失区域104中的晶体管105的晶体管、区域105中的如图1~6中体现的晶体管10的晶体管(其具有含有三栅晶体管的电路)、和如易失区域106中的晶体管103的晶体管的处理相同的处理实现的。尽管动态存储器,诸如DRAM被认为是关于易失区域106的存储器件的类型,但是还可以实现其它类型的易失存储器阵列,诸如FLASH存储器阵列。使用三栅晶体管,可以在区域105中实现任何类型的电路,包括逻辑电路、模拟电路和数字电路。在集成电路180中可以包括任何其它的多种电路模块(未示出),其使用此处描述的一个或全部三个类型的晶体管功能(NVM三栅晶体管、易失存储器三栅晶体管和非存储三栅晶体管结构)。应当认识到,可以实现仅使用图14中说明的三个电路类别中的一个或两个的集成电路。
到目前为止,应当认识到,提供了一种晶体管结构,其具有三个独立的栅极。在一个形式中,该晶体管可被设置为提供通用存储器架构,其中可以使用相同的半导体工艺,在相同的集成电路上实现非易失和易失存储单元。此处描述的晶体管结构的多样性显著地减少了同在相同芯片上制造诸如Flash或具有ROM的DRAM或RAM的存储器相关联的成本。传统地,需要在集成电路上实现使用不同的处理步骤制造的不同的存储器模块。通过具有三个独立的栅极,该晶体管用于提供三个不同的沟道电气调制的源。通过增加的沟道电流控制,可以更加准确地控制晶体管的阈值电压(即,通过改变栅极的偏置组合,可以动态地提高或降低阈值电压)。依赖于用于使沟道同三个栅极接合的栅介质的尺寸和类型,并且依赖于栅极的尺寸和掺杂以及栅极的材料构成,还可以设置晶体管阈值电压。可以通过传统的注入或现场掺杂,对第三栅极进行掺杂。可以通过有角度注入向第一和第二栅极注入相同或不同的物质。第一和第二栅极还可以进行原位掺杂,以获得相同的传导率。
通过使用一种类型的存储器存储物质用于电荷存储层118和不同类型的存储器存储物质用于电荷存储层143,可以产生不同的读和写存储器机制。特别地,通过使用上面的第三栅极,使用热载流子注入(HCI),可以对晶体管105编程(即,写),并且通过源极和漏极之间的载流子传导,通过隧穿或热空穴载流子,可以擦除晶体管105。通过使用第一栅极157和第二栅极159,使用隧穿或热沟道编程,可以对晶体管103编程。通过使用源自三个栅极的任何栅极的隧穿或者通过适当的偏置源漏,可以擦除晶体管103。
在前面的说明书中,通过参考具体的实施例描述了本发明。然而,本领域的普通技术人员应认识到,在不偏离如附属权利要求所阐述的本发明的范围的前提下,可以进行多种修改和变化。例如,在上文所述的刻蚀和清洗步骤之后,可以使氮化物层22下面的沟道14和第三栅极18在侧壁边缘处凹陷。在形成图8中的电荷存储层143之后,可以遮盖一部分晶片101,并且可以从那些未被遮盖的晶片101的区域中,移除电荷存储层143和介质层145。这些区域可以用作不具有周界(侧面和顶面)上的存储位置的晶体管。此外,可以实现晶体管103的第三栅极叠层结构的刻蚀,以移除电荷存储层143、介质层145、介质层133、氧化物层129、第三栅极125、介质层141、控制栅介质121和电荷存储层120。得到的结构是具有多面沟道的晶体管。而且,三个栅极区域可以具有不同的材料属性,其中某些栅极区域是多晶硅,而其它的栅极区域是金属。
在一个形式中,此处提供了一种制造半导体器件的方法。形成了半导体结构,其中该半导体结构包括顶表面、第一侧壁和同第一侧壁相对的第二侧壁。形成了第一栅极结构和第二栅极结构,其中第一栅极结构被安置为同第一侧壁相邻,并且第二栅极结构被安置为同第二侧壁相邻。在顶表面上安置第三栅极结构,其中第一栅极结构、第二栅极结构和第三栅极结构在物理上相互分离。通过在第三栅极结构和基板上淀积栅极材料层,并且移除第三栅极结构上面的栅极材料层部分以形成第一栅极结构和第二栅极结构,形成了第一栅极结构和第二栅极结构。在另一形式中,通过非研磨刻蚀半导体结构的顶表面上的栅极材料层,形成了第一栅极结构和第二栅极结构。在基板上面形成了基本上平坦的层,其低于栅极材料层的顶表面的高度。该基本上平坦的层用作掩膜层,用于形成第一栅极结构和第二栅极结构。在另一形式中,通过单一的构图步骤形成了第三栅极结构和半导体结构。通过单一的构图步骤,连同第三栅极结构上面的至少两个另外的层,对使半导体结构和第三栅极结构分离的第一介质材料构图。形成了第一源极/漏极区域和第二源极/漏极区域,其自半导体结构开始在垂直于第一栅极结构和第二栅极结构的侧面的半导体结构的相反侧面上延伸,其中形成第一源极/漏极区域和第二源极/漏极区域进一步包括,在对应于第一源极/漏极区域和第二源极/漏极区域的位置对集成电路进行掺杂。通过对第一栅极结构、第二栅极结构和第三栅极结构构图,以暴露第一源极/漏极区域和第二源极/漏极区域,形成了第一源极/漏极区域和第二源极/漏极区域。在形成第一源极/漏极区域和第二源极/漏极区域之后,通过形成基板上面的基本上平坦的层,其低于栅极材料层的顶表面的高度,并且使用该基本上平坦的层作为掩膜层以形成第一栅极结构和第二栅极结构,形成了第一栅极结构和第二栅极结构。在一个形式中,第一介质层被形成为围绕半导体结构的第一侧壁和第二侧壁,并且使半导体结构同第一栅极结构和第二栅极结构电气绝缘。在半导体结构的顶表面上,通过与用于形成第一介质层的处理步骤不同的处理步骤,形成了第二介质层。在一个形式中,第一介质层通过第一介质材料形成,并且第二介质层通过第二介质材料形成,第二介质材料具有至少一个不同于第一介质材料的物理属性。在另一形式中,该至少一个物理属性选自下列属性中的一个:介质层厚度、介质电导率、或介电常数。在另一实施例中,形成了电荷存储结构,该电荷存储结构位于顶表面和第三栅极结构之间,其中该电荷存储结构包括纳米团簇。在一个形式中,纳米团簇包括硅纳米团簇、锗纳米团簇、锗硅合金纳米团簇、金纳米团簇、银纳米团簇和铂纳米团簇中的至少一个。在一个实施例中,电荷存储结构包括电荷俘获介质,并且该电荷俘获介质包括氮化硅、氧化铪、氧化锌、富氧化硅、和氧化铝中的至少一个。在一个形式中,形成了第一电荷存储结构,其被安置为同第一侧壁相邻,第一栅极结构在第一电荷存储结构的与第一侧壁相反的侧面上,被安置为同第一电荷存储结构相邻。形成了第二电荷存储结构,其被安置为同第二侧壁相邻,第二栅极结构在第二电荷存储结构的与第二侧壁相反的侧面上,被安置为同第二电荷存储结构相邻。在另一实施例中,形成了第三电荷存储结构,该第三电荷存储结构位于顶表面和第三栅极结构之间。在可替换的形式中,仅形成了针对第一栅极结构、第二栅极结构和第三栅极结构中的两个的电接触。在另一形式中,仅实现了针对第一栅极结构、第二栅极结构和第三栅极结构中的一个的电接触。在一个形式中,第三栅极结构具有形成的第一传导类型。在另一形式中,第一栅极结构和第二栅极结构被掺杂,以具有形成的第二传导类型,第一传导类型同第二传导类型相反。在另一形式中,每个第一栅极结构、第二栅极结构和第三栅极结构被掺杂为具有不同的传导率。在另一实施例中,通过有角度掺杂对第一栅极结构和第二栅极结构进行掺杂,其具有不同的掺杂条件。在另一形式中,半导体器件包括半导体结构,其具有顶表面、第一侧壁和同第一侧壁相对的第二侧壁。第一栅极结构被安置为同第一侧壁相邻。第二栅极结构被安置为同第二侧壁相邻。第三栅极结构被安置在顶表面上。在一个形式中,第一栅极结构、第二栅极结构和第三栅极结构在物理上相互分离。源极区域和漏极区域自半导体结构开始在垂直于第一栅极结构和第二栅极结构的侧面的半导体结构的相反侧面上延伸。在一个形式中,第一栅极结构被安置为,在源极和漏极之间的半导体结构的位置处,同第一侧壁相邻。第二栅极结构被安置为,在源极和漏极之间的半导体结构的位置处,同第二侧壁相邻,并且第三栅极结构被安置在源极和漏极之间的顶表面上。在另一实施例中,第一介质层围绕半导体结构的第一侧壁和第二侧壁,并且使半导体结构同第一栅极结构和第二栅极结构电气绝缘。第二介质层位于半导体结构的顶表面上。在一个形式中,第一介质层和第二介质层具有至少一个不同的物理属性,并且该至少一个不同的物理属性包括介质层厚度、介质电导率、或介电常数中的一个。电荷存储结构位于顶表面和第三栅极结构之间。在一个形式中,电荷存储结构包括纳米团簇,其中该纳米团簇包括硅纳米团簇、锗纳米团簇、锗硅合金纳米团簇、金纳米团簇、银纳米团簇和铂纳米团簇中的至少一个。在另一形式中,电荷存储结构是电荷俘获介质,并且该电荷俘获介质包括氮化硅、氧化铪、氧化锌、富氧化硅、和氧化铝中的一个。在另一形式中,第一电荷存储结构被安置为同第一侧壁相邻,并且第一栅极结构在第一电荷存储结构的与第一侧壁相反的侧面上,被安置为同第一电荷存储结构相邻。第二电荷存储结构被安置为同第二侧壁相邻,并且第二栅极结构在第二电荷存储结构的与第二侧壁相反的侧面上,被安置为同第二电荷存储结构相邻。在一个实施例中,第一电荷存储结构和第二电荷存储结构包括纳米团簇,其中该纳米团簇包括硅纳米团簇、锗纳米团簇、锗硅合金纳米团簇、金纳米团簇、银纳米团簇和铂纳米团簇中的至少一个。第一电荷存储结构和第二电荷存储结构包括电荷俘获介质,其中该电荷俘获介质包括氮化硅、氧化铪、氧化锌、富氧化硅、和氧化铝中的至少一个。第三电荷存储结构位于顶表面和第三栅极结构之间,该第三电荷存储结构具有至少一个不同于第一电荷存储结构和第二电荷存储结构的属性。在一个形式中,第三栅极结构被掺杂为具有第一传导类型,并且第一栅极结构和第二栅极结构被掺杂为具有第二传导类型。在另一形式中,第一栅极结构、第二栅极结构和第三栅极结构具有不同的传导率。
因此,本说明书和附图应被视为说明性的而非限制性的,并且所有该修改方案的目的在于涵盖在本发明的范围内。上文针对具体的实施例描述了好处、其它优点和对问题的解决方案。然而,该好处、点、对问题的解决方案,以及可以引出任何好处、优点或解决方案或使其变得更加显著的任何元素,不应被解释为任何或全部权利要求的关键的、需要的或基本的特征。如此处所使用的,术语“包括”或其任何变化形式,目的在于涵盖非排它性的内含物,因此包括一系列元素的工艺、方法、物体或装置不仅包括这些列出的元素,而且可以包括未明确列出或者对于该工艺、方法、物体或装置是固有的元素。
Claims (8)
1.一种制造半导体器件(105)的方法,包括:
形成沟道(113),该沟道包括顶水平表面、第一垂直侧壁和同第一侧壁相对的第二垂直侧壁;
形成第一栅极结构(153,图11)和第二栅极结构(155),其中第一栅极结构(153)被安置为同第一侧壁侧向相邻且基本沿着第一侧壁,并且第二栅极结构被安置为同第二侧壁侧向相邻且基本沿着第二侧壁;
形成第三栅极结构(123),其安置在全部顶水平表面上且基本沿着全部顶水平表面,其中第一栅极结构(153)、第二栅极结构(155)和第三栅极结构(123)在物理上相互分离,其中形成第一栅极结构(153)和第二栅极结构(155)进一步包括:
在第三栅极结构(123)和基板(107)上淀积栅极材料层(147),并且移除第三栅极结构(123)上面的一部分栅极材料层(147)以形成第一栅极结构(153)和第二栅极结构(155);以及
在沟道和第一栅极结构(153)、第二栅极结构(155)、第三栅极结构(123)中至少一个栅极结构之间形成电荷存储层(143、118)。
2.权利要求1的方法,进一步包括:在第三栅极结构和基板上淀积栅极材料层之后,对第三栅极结构(123)构图。
3.权利要求1的方法,其中形成第一栅极结构(153)和第二栅极结构(155)进一步包括:在移除第三栅极结构上面的一部分栅极材料层之后,对第一栅极结构(153)和第二栅极结构(155)构图。
4.权利要求3的方法,进一步包括:在基板(107)上面形成基本上平坦的层(151),其低于栅极材料层的顶表面的高度,将该基本上平坦的层用作掩膜层,以形成第一栅极结构和第二栅极结构。
5.一种半导体器件(105),包括:
沟道(113),其包括顶表面、第一侧壁和同第一侧壁相对的第二侧壁;
第一栅极结构(155),其被安置为同第一侧壁相邻;
第二栅极结构(153),其被安置为同第二侧壁相邻;
第三栅极结构(123),其被安置在顶表面上;以及
第一电荷存储结构(118),其被安置在顶表面和第三栅极结构(123)之间;
其中,第一栅极结构(155)、第二栅极结构(153)和第三栅极结构(123)在物理上相互分离。
6.权利要求5的半导体器件,进一步包括:
源极区域(179)和漏极区域(181),其自沟道开始在垂直于第一栅极结构(155)和第二栅极结构(153)的侧面的沟道的相反侧面上延伸;
其中,第一栅极结构(155)被安置为,在源极区域和漏极区域之间的沟道(113)的位置处,同第一侧壁相邻;
其中,第二栅极结构(153)被安置为,在源极区域和漏极区域之间的沟道的位置处,同第二侧壁相邻;并且
其中,第三栅极结构(123)被安置在源极区域和漏极区域之间的顶表面上。
7.权利要求5的半导体器件,进一步包括:
第一介质层(135),其围绕沟道(113)的第一侧壁和第二侧壁,并且使沟道同第一栅极结构和第二栅极结构电气绝缘;和
第二介质层(115),其位于沟道(113)的顶表面上,第一介质层(135)和第二介质层(115)具有至少个不同的物理属性。
8.权利要求5的半导体器件,进一步包括:
第二电荷存储结构(143),其被安置为同第一侧壁相邻,第一栅极结构(155)在第二电荷存储结构的与第一侧壁相反的侧面上,被安置为同第二电荷存储结构相邻;和
第三电荷存储结构,其被安置为同第二侧壁相邻,第二栅极结构(153)在第三电荷存储结构的与第二侧壁相反的侧面上,被安置为同第三电荷存储结构相邻。
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US7098502B2 (en) | 2006-08-29 |
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WO2005048299A3 (en) | 2005-11-17 |
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JP2007511090A (ja) | 2007-04-26 |
TWI360863B (en) | 2012-03-21 |
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WO2005048299A2 (en) | 2005-05-26 |
CN1868067A (zh) | 2006-11-22 |
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