TWI351733B - Dielectric spacers for metal interconnects and met - Google Patents
Dielectric spacers for metal interconnects and met Download PDFInfo
- Publication number
- TWI351733B TWI351733B TW096115614A TW96115614A TWI351733B TW I351733 B TWI351733 B TW I351733B TW 096115614 A TW096115614 A TW 096115614A TW 96115614 A TW96115614 A TW 96115614A TW I351733 B TWI351733 B TW I351733B
- Authority
- TW
- Taiwan
- Prior art keywords
- dielectric
- interconnect
- spacer
- dielectric layer
- interconnects
- Prior art date
Links
- 125000006850 spacer group Chemical group 0.000 title claims description 137
- 229910052751 metal Inorganic materials 0.000 title description 109
- 239000002184 metal Substances 0.000 title description 109
- 238000000034 method Methods 0.000 claims description 50
- 238000005229 chemical vapour deposition Methods 0.000 claims description 10
- JMANVNJQNLATNU-UHFFFAOYSA-N oxalonitrile Chemical compound N#CC#N JMANVNJQNLATNU-UHFFFAOYSA-N 0.000 claims description 7
- OKTJSMMVPCPJKN-UHFFFAOYSA-N Carbon Chemical compound [C] OKTJSMMVPCPJKN-UHFFFAOYSA-N 0.000 claims description 6
- 239000003989 dielectric material Substances 0.000 claims description 6
- NFFIWVVINABMKP-UHFFFAOYSA-N methylidynetantalum Chemical compound [Ta]#C NFFIWVVINABMKP-UHFFFAOYSA-N 0.000 claims description 6
- 229910003468 tantalcarbide Inorganic materials 0.000 claims description 6
- QGZKDVFQNNGYKY-UHFFFAOYSA-N Ammonia Chemical compound N QGZKDVFQNNGYKY-UHFFFAOYSA-N 0.000 claims description 4
- 229910000420 cerium oxide Inorganic materials 0.000 claims description 4
- VNWKTOKETHGBQD-UHFFFAOYSA-N methane Chemical compound C VNWKTOKETHGBQD-UHFFFAOYSA-N 0.000 claims description 4
- BMMGVYCKOGBVEV-UHFFFAOYSA-N oxo(oxoceriooxy)cerium Chemical compound [Ce]=O.O=[Ce]=O BMMGVYCKOGBVEV-UHFFFAOYSA-N 0.000 claims description 4
- 229920000642 polymer Polymers 0.000 claims description 4
- 238000004528 spin coating Methods 0.000 claims description 4
- 238000000231 atomic layer deposition Methods 0.000 claims description 3
- XMHIUKTWLZUKEX-UHFFFAOYSA-N hexacosanoic acid Chemical class CCCCCCCCCCCCCCCCCCCCCCCCCC(O)=O XMHIUKTWLZUKEX-UHFFFAOYSA-N 0.000 claims description 3
- UNASZPQZIFZUSI-UHFFFAOYSA-N methylidyneniobium Chemical compound [Nb]#C UNASZPQZIFZUSI-UHFFFAOYSA-N 0.000 claims description 3
- MZLGASXMSKOWSE-UHFFFAOYSA-N tantalum nitride Chemical compound [Ta]#N MZLGASXMSKOWSE-UHFFFAOYSA-N 0.000 claims description 3
- ZOXJGFHDIHLPTG-UHFFFAOYSA-N Boron Chemical compound [B] ZOXJGFHDIHLPTG-UHFFFAOYSA-N 0.000 claims description 2
- 229910021529 ammonia Inorganic materials 0.000 claims description 2
- 229910052796 boron Inorganic materials 0.000 claims description 2
- 229910052799 carbon Inorganic materials 0.000 claims description 2
- -1 diborane Chemical compound 0.000 claims description 2
- 239000007789 gas Substances 0.000 claims description 2
- IJGRMHOSHXDMSA-UHFFFAOYSA-N Atomic nitrogen Chemical compound N#N IJGRMHOSHXDMSA-UHFFFAOYSA-N 0.000 claims 2
- 238000000151 deposition Methods 0.000 claims 2
- KRKNYBCHXYNGOX-UHFFFAOYSA-K Citrate Chemical compound [O-]C(=O)CC(O)(CC([O-])=O)C([O-])=O KRKNYBCHXYNGOX-UHFFFAOYSA-K 0.000 claims 1
- CETPSERCERDGAM-UHFFFAOYSA-N ceric oxide Chemical compound O=[Ce]=O CETPSERCERDGAM-UHFFFAOYSA-N 0.000 claims 1
- 229910000422 cerium(IV) oxide Inorganic materials 0.000 claims 1
- 230000008021 deposition Effects 0.000 claims 1
- 238000009830 intercalation Methods 0.000 claims 1
- 238000004519 manufacturing process Methods 0.000 claims 1
- BFRGSJVXBIWTCF-UHFFFAOYSA-N niobium monoxide Chemical compound [Nb]=O BFRGSJVXBIWTCF-UHFFFAOYSA-N 0.000 claims 1
- 229910052757 nitrogen Inorganic materials 0.000 claims 1
- 230000004888 barrier function Effects 0.000 description 11
- 239000000463 material Substances 0.000 description 11
- 230000015572 biosynthetic process Effects 0.000 description 6
- 230000008878 coupling Effects 0.000 description 6
- 238000010168 coupling process Methods 0.000 description 6
- 238000005859 coupling reaction Methods 0.000 description 6
- 238000000059 patterning Methods 0.000 description 5
- 239000004065 semiconductor Substances 0.000 description 5
- 239000002041 carbon nanotube Substances 0.000 description 4
- 229910021393 carbon nanotube Inorganic materials 0.000 description 4
- 239000010941 cobalt Substances 0.000 description 4
- GUTLYIVDDKVIGB-UHFFFAOYSA-N cobalt atom Chemical compound [Co] GUTLYIVDDKVIGB-UHFFFAOYSA-N 0.000 description 4
- 229910017052 cobalt Inorganic materials 0.000 description 3
- 230000000295 complement effect Effects 0.000 description 3
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 3
- 229910052737 gold Inorganic materials 0.000 description 3
- 239000010931 gold Substances 0.000 description 3
- 150000002739 metals Chemical class 0.000 description 3
- 239000011532 electronic conductor Substances 0.000 description 2
- 230000002401 inhibitory effect Effects 0.000 description 2
- 230000005012 migration Effects 0.000 description 2
- 238000013508 migration Methods 0.000 description 2
- 230000003647 oxidation Effects 0.000 description 2
- 238000007254 oxidation reaction Methods 0.000 description 2
- 239000000126 substance Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- WGTYBPLFGIVFAS-UHFFFAOYSA-M tetramethylammonium hydroxide Chemical compound [OH-].C[N+](C)(C)C WGTYBPLFGIVFAS-UHFFFAOYSA-M 0.000 description 2
- 229910000531 Co alloy Inorganic materials 0.000 description 1
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- ZOKXTWBITQBERF-UHFFFAOYSA-N Molybdenum Chemical compound [Mo] ZOKXTWBITQBERF-UHFFFAOYSA-N 0.000 description 1
- BQCADISMDOOEFD-UHFFFAOYSA-N Silver Chemical compound [Ag] BQCADISMDOOEFD-UHFFFAOYSA-N 0.000 description 1
- RTAQQCXQSZGOHL-UHFFFAOYSA-N Titanium Chemical compound [Ti] RTAQQCXQSZGOHL-UHFFFAOYSA-N 0.000 description 1
- 229910001080 W alloy Inorganic materials 0.000 description 1
- 229910045601 alloy Inorganic materials 0.000 description 1
- 239000000956 alloy Substances 0.000 description 1
- 229910052782 aluminium Inorganic materials 0.000 description 1
- XAGFODPZIPBFFR-UHFFFAOYSA-N aluminium Chemical compound [Al] XAGFODPZIPBFFR-UHFFFAOYSA-N 0.000 description 1
- 238000000277 atomic layer chemical vapour deposition Methods 0.000 description 1
- QVGXLLKOCUKJST-UHFFFAOYSA-N atomic oxygen Chemical compound [O] QVGXLLKOCUKJST-UHFFFAOYSA-N 0.000 description 1
- GPBUGPUPKAGMDK-UHFFFAOYSA-N azanylidynemolybdenum Chemical compound [Mo]#N GPBUGPUPKAGMDK-UHFFFAOYSA-N 0.000 description 1
- 230000000903 blocking effect Effects 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005137 deposition process Methods 0.000 description 1
- 238000010586 diagram Methods 0.000 description 1
- 239000004744 fabric Substances 0.000 description 1
- NBVXSUQYWXRMNV-UHFFFAOYSA-N fluoromethane Chemical compound FC NBVXSUQYWXRMNV-UHFFFAOYSA-N 0.000 description 1
- 229910044991 metal oxide Inorganic materials 0.000 description 1
- 150000004706 metal oxides Chemical class 0.000 description 1
- 239000000203 mixture Substances 0.000 description 1
- 229910052750 molybdenum Inorganic materials 0.000 description 1
- 239000011733 molybdenum Substances 0.000 description 1
- 229910052758 niobium Inorganic materials 0.000 description 1
- 239000010955 niobium Substances 0.000 description 1
- GUCVJGMIXFAOAE-UHFFFAOYSA-N niobium atom Chemical compound [Nb] GUCVJGMIXFAOAE-UHFFFAOYSA-N 0.000 description 1
- 150000004767 nitrides Chemical class 0.000 description 1
- 230000006911 nucleation Effects 0.000 description 1
- 238000010899 nucleation Methods 0.000 description 1
- 229910052760 oxygen Inorganic materials 0.000 description 1
- 239000001301 oxygen Substances 0.000 description 1
- 238000005240 physical vapour deposition Methods 0.000 description 1
- 150000003254 radicals Chemical class 0.000 description 1
- 230000002787 reinforcement Effects 0.000 description 1
- 230000000717 retained effect Effects 0.000 description 1
- 229910052709 silver Inorganic materials 0.000 description 1
- 239000004332 silver Substances 0.000 description 1
- 229910052715 tantalum Inorganic materials 0.000 description 1
- GUVRBAGPIYLISA-UHFFFAOYSA-N tantalum atom Chemical compound [Ta] GUVRBAGPIYLISA-UHFFFAOYSA-N 0.000 description 1
- 239000010936 titanium Substances 0.000 description 1
- 229910052719 titanium Inorganic materials 0.000 description 1
- 229910052721 tungsten Inorganic materials 0.000 description 1
- 239000010937 tungsten Substances 0.000 description 1
- WFKWXMTUELFFGS-UHFFFAOYSA-N tungsten Chemical compound [W] WFKWXMTUELFFGS-UHFFFAOYSA-N 0.000 description 1
- 239000011800 void material Substances 0.000 description 1
- 238000001039 wet etching Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
- H01L21/76834—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers formation of thin insulating films on the sidewalls or on top of conductors
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
- H01L21/28008—Making conductor-insulator-semiconductor electrodes
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/7682—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing the dielectric comprising air gaps
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
- H01L21/76877—Filling of holes, grooves or trenches, e.g. vias, with conductive material
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- H01L23/5222—Capacitive arrangements or effects of, or between wiring layers
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- H01L23/5226—Via connections in a multilevel interconnection structure
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- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53214—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being aluminium
- H01L23/53223—Additional layers associated with aluminium layers, e.g. adhesion, barrier, cladding layers
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- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/53204—Conductive materials
- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53228—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
- H01L23/53238—Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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- H01L23/53209—Conductive materials based on metals, e.g. alloys, metal silicides
- H01L23/53242—Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being a noble metal, e.g. gold
- H01L23/53252—Additional layers associated with noble-metal layers, e.g. adhesion, barrier, cladding layers
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- H01L23/53276—Conductive materials containing carbon, e.g. fullerenes
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- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
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- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Manufacturing & Machinery (AREA)
- Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
- Production Of Multi-Layered Print Wiring Board (AREA)
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1351733 遲之方法。 【發明內容及實施方式】 描述用於積體電路中之具有電介質隔片之複數個金屬 互連以及製造具有電介質隔片的此種複數個金屬互連的程 序。在下列說明中,提出各種的細節,例如特定尺寸與化 學方法,以提供本發明之詳盡的了解。對熟悉該項技藝者 很明顯地,可不以這些特定細節實施本發明。在其他的例 子中,並未詳細描述已知的程序步驟,如圖案化步驟,以 不非必要地模糊本發明。此外,可理解到圖中顯示的各種 的實施例爲例式性的代表,且非絕對按比例繪製。 在此揭露金屬互連的電介質以及形成此種電介質隔片 的方法。將電介質隔片包含在金屬互連的側壁旁可使各種 金屬互連間有相對低的耦合電容、可提供複數個互連及其 連接的通孔之實體支撐、以及可提供未著底之通孔可駐著 於其上之區域。因此,可形成一種「氣隙」金屬互連架構 ,其提供包含到積體電路內之足夠的完整性以及提供可供 未著底之通孔「著底」之區域。 在金屬互連之間使用電介質隔片可減少金屬互連間的 耦合電容,或「串音」,因此,電介質隔片可用來減輕一 組的金屬互連內的「RC延遲」。並且,將電介質隔片包 含在金屬互連間得允許在此種金屬互連間的空間中使用減 少的介電常數之材料(如具有比二氧化矽更小的介電常數 之材料),進一步減少耦合電容。例如,金屬互連間之低 -5- 1351733 電介質層106的塡充。在一實施例中,間隙120足夠的寬 ,以減輕相鄰電介質隔片1 0 8間的串音。在一實施例中, 間隙120的寬度實質上等於電介質隔片1〇8間的寬度。在 另一實施例中,間隙120的寬度在5-20奈米的範圍中。 在一實施例中,間隙1 20的寬度大約爲相鄰金屬互連間之 距離的三分之一。 包含不接觸之電介質隔片之複數個金屬互連可能需要 結構性加強。根據本發明的一實施例,此種金屬互連陷入 下層的電介質層中,因而「固定(anchor)」金屬互連。 參照第2圖,包含阻障層216之金屬互連202與204陷入 電介質層206中。電介質隔片208可不陷入,但仍由間隙 220所分開且不連接,如第2圖中所示。在一實施例中, 結構200,包含複數個金屬互連,具有因固定金屬互連 202與2 04而導致之改善的結構完整性。在另一實施例中 ,凹陷的金屬互連202與204由金屬鑲嵌程序所形成,其 中在金屬鑲嵌圖案化步驟中形成陷入電介質層20 6的凹陷 〇 包含不連接之電介質隔片的複數個金屬互連可包含具 有可變化的間隔之主動金屬互連的架構。此種主動金屬互 連間之各種間隔的架構抑制完全氣隙架構的形成,因爲上 層電介質會塡入較寬的間隙中,因而增加間隔較遠的金屬 互連間的耦合電容。根據本發明的一實施例,假金屬互連 ’亦即不與積體電路的主動部分連接之金屬互連,用於在 金屬互連間維持均等間隔。參照第3圖,複數個金屬互連 -9-
1351733 300包含假金屬互連330。在一實 33〇阻擋電介質層306塡入在相鄰的 連接的電介質隔片間的間隙^ 替代與第3圖關聯之結構,包爸 動金屬互連的架構之包含不連接的電 屬互連可不包含假互連。根據本發明 電介質層塡入與互相間隔較遠的相鄰 接的電介質隔片間的間隙中。參照第 4 1 2與4 1 4間的間隔比相鄰金屬互連 更遠。在金屬互連402與404上之電 金屬互連402與404間的間隙中, 414上之電介質層4 4 0則塡入金屬互 隙中。在一實施例中,具有比電介質 度之間隙會被上層的電介質層440填 實施例,沉積電介質層440至足以J 4 1 4間的間隙之厚度,其中間隙的寬 寬度,以及厚度足以後續被磨光成在 之上與之間中的平表面,如第4圖中 —實施例,旋塗電介質層440至足以 4 1 4間的間隙之厚度,其中間隙的寬 寬度,以及厚度足以提供在金屬互連 間中的平表面,如第4圖中所示。 可由任何適當的方法製造金屬互 在電介質隔片的形成期間維持金屬互 施例中,假金屬互連 J主動金屬互連上之不 Γ具有可變化間隔之主 :介質隔片之複數個金 丨之一實施例,由上層 ;金屬互連關聯之不連 4圖,相鄰金屬互連 402與404間的間隔 :介質層406不會塡入 而在金屬互連412與 連4 1 2與4 1 4間的間 隔片的寬度更大的寬 :補。根據本發明之一 眞補金屬互連412與 度大於電介質隔片的 金屬互連412與414 所示。根據本發明之 塡補金屬互連412與 度大於電介質隔片的 412與414之上與之 連的電介質隔片,以 連的完整性以及下層 -10- 1351733 的電介質層。根據本發明之一實施例,第5A-J圖顯示在 積體電路中之複數個金屬互連之不連接的電介質隔片之形 _ 成。參照第5A圖,結構5〇〇可包含複數個互連、半導體 基底、或半導體或電子裝置的陣列的一部分。在一實施例 中,結構5 00爲由電介質層圍住之互補金屬氧化物半導體 (CMOS )電晶體的陣列。電介質層502沉積在結構500 上,如第5A圖所示。電介質層502可由任何適當的技術 • 沉積,該技術在結構500之上提供實質上一致的覆蓋之電 介質層5 02。在一實施例中,由旋塗程序、化學蒸氣沉積 程序、或基於聚合物之化學蒸氣沉積程序沉積電介質層 5〇2。電介質層502可包含任何適當的材料,作爲具有電 介質隔片之複數個金屬互連的耐用基部。在一實施例中, 電介質層5 02由二氧化矽、矽酸鹽、或具有0-10%的孔 隙率之摻雜碳的氧化物所構成。 可由任何適合的技術在電介質層502上形成金屬互連 。在一實施例中,由施加至平坦金屬薄膜之減去式蝕刻程 序來形成金屬互連。在另一實施例中,由金屬鑲嵌技術形 成金屬互連。參照第5B-5D圖,可使用利用犧牲電介質 層之金屬鑲嵌技術來形成金屬互連。犧牲電介質層504可 由在電介質層502之上提供實質上一致的覆蓋之犧牲電介 質層504的任何適當的技術形成,如第5B圖中所示。在 一實施例中,由旋塗程序、化學蒸氣沉積程序、或基於聚 合物之化學蒸氣沉積程序沉積犧牲電介質層504。犧牲電 介質層504可包含後續被移除而不影響電介質層502或金 1351733 % 屬互連之任何適當的材料。在一實施例中,犧牲電 5 04由具有20-3 5 %的孔隙率之摻雜碳的氧化物所精 參照第5C圖’可圖案化犧牲電介質層504以 案化的犧牲電介質層506,其暴露電介質層502的 。可接著在圖案化的犧牲電介質層中,在電介質層 暴露出來之表面上,形成金屬互連510,如第5D 示。可由任何適合的技術形成金屬互連510,其塡 化的犧牲電介質層506中形成的溝槽。在一實施例 電性沉積程序接著化學機械硏磨步驟來沉積金屬互 。金屬互連510可包含從金屬互連的一端傳導電流 互連的另一端之任何適當的材料。在一實施例中, 連510由銅、銀、鋁、或上述之合金所構成。在另 例中,金屬互連510包含散佈的碳奈米管陣列。 金屬互連510可包含阻障層508,如第5D圖 。阻障層508可由任何適當的技術沉積,其均勻地 成在圖案化的犧牲電介質層506的溝槽之側壁與底 一實施例中,由原子層沉積程序、化學蒸氣沉積程 物理蒸氣沉積程序來沉積阻障層508。阻障層508 適合用於禁止金屬互連510之電性遷移、防止金 510的氧化、或在金屬鑲嵌程序中提供晶核生成之 料。在一實施例中,阻障層508由鉬、鈦、氮化鉬 鈦:或上述之組合所構成。在另一實施例中,阻障 的厚度在50-1 5 0埃的範圍中。 金屬互連510亦包含蓋層512»蓋層512可包
介質層 I成。 形成圖 一部分 502的 圖中所 補圖案 中,由 連 5 10 至金屬 金屬互 一實施 中所示 圍繞形 部。在 序、或 可包含 屬互連 任何材 、氮化 層 508 含適合 < S -12- 1351733 用於禁止金屬互連內的電性遷移、防止金屬互連氧化、或 在形成電介質隔片的期間保護金屬互連之任何材料。蓋層 512亦可允許使用含氧電介質隔片》在一實施例中,蓋層 512包含銥、釕、鈷 '鈷/鎢合金、磷化鈷/鎢、磷化鈷硼 、或其之組合所構成。 可移除圖案化的犧牲電介質層506以提供獨立的金屬 互連510,如第5E圖中所示。可藉由任何適合的技術移 除圖案化的犧牲電介質層506,其中移除程序不會影響電 介質層502或金屬互連510。根據本發明之一實施例,圖 案化的犧牲電介質層506由具有20-35%的孔隙率之摻雜 碳的氧化物所構成、電介質層502由具有0-10%的孔隙 率之摻雜碳的氧化物所構成,以及以包含20-30%體積之 氫氧化四甲銨的濕蝕刻化學移除圖案化的犧牲電介質層 506 ° 參照第5F圖’可在金屬互連510以及在電介質層 502之暴露的表面上保角地沉積形成隔片電介質層514。 可由能夠形成保角或幾乎保角層之任何適合的技術沉積形 成隔片電介質層514。並且,可由不會過度加熱在複數個 互連下的任何電子或半導體裝置之何適合的技術沉積形成 隔片電介質層514。在一實施例中,在400。(:或以下之溫 度沉積形成隔片電介質層514。在另一實施例中,由原子 層沉積或化學蒸氣沉積來沉積形成隔片電介質層514。形 成隔片電介質層514可包含提供未著底之通孔可「著底」 之表面的任何適合的電介質材料。在一實施例中,形成隔 -13- 1351733 片電介質層514係由氮化矽、碳化矽、摻雜氮之碳化矽、 摻雜氧之碳化矽、摻雜硼之氮化碳、或摻雜硼之碳化矽。 在另一實施例中,形成隔片電介質層514係由摻雜硼的氮 化碳層所構成,其中藉由使甲烷、二硼烷、以及氨起作用 來形成該摻雜砸的氮化碳層。在一實施例中,形成隔片電 介質層514的厚度決定電介質隔片116的寬度,如下所述 〇 可圖案化形成隔片電介質層514以形成不連接的電介 質隔片516,如第5G圖中所示。可藉由從金屬互連510 的上表面或其各自的蓋層512以及從在金屬互連510間暴 露出來的電介質層5 02的上表面移除形成隔片電介質層 514的部分之任何適合的技術來圖案化隔片電介質層514 。因此,可保留下與金屬互連510的側壁或其各自的阻障 層5 08相鄰的形成隔片電介質層514的部分,以形成不連 接的電介質隔片516,如第5G圖中所示。在一實施例中 ,可藉由使用非等向性蝕刻程序來圖案化形成隔片電介質 層514以形成電介質隔片516。在另一實施例中,使用包 含具有之CxFy的通式之垂直乾或電漿蝕刻程序來圖案化 形成隔片電介質層514以形成電介質隔片516,其中X與 y爲自然數。在另一實施例中,使用包含自由基碳氟化合 物之垂直乾或電漿蝕刻程序來圖案化形成隔片電介質層 514以形成電介質隔片516。在一實施例中,電介質隔片 116的寬度係由形成隔片電介質層514的厚度所決定。在 另一實施例中,延伸非等向性蝕刻程序以移除電介質層 -14- 1351733 5 02的一部分。 參照第5Η圖,在金屬互連510上形成電介質隔片 516之後,可在金屬互連510或其各自的蓋層512上以及 電介質隔片516上沉積電介質層518。可由在金屬互連 510與511之上提供實質上平坦覆蓋且不實質上塡充相鄰 金屬互連510與511之電介質隔片之間的空間的任何適合 的技術來沉積電介質層518,如第5Η圖中所示。在一實 施例中’可由旋塗程序、化學蒸氣沉積程序、或基於聚合 物之化學蒸氣沉積程序來沉積電介質層518。電介質層 518可包含作爲新的一層金屬互連之耐用基部之任何適合 的材料。在一實施例中,電介質層518係由二氧化矽、矽 酸鹽、或具有0-10%的孔隙率之摻雜碳的氧化物所構成 可在相鄰的金屬互連510與511的電介質隔片516之 間以及電介質層5 02與5 1 8之間形成間隙5 20。可由能使 金屬互連510與511之間有微不足道之電容耦合之任何適 合的材料或氣體構成間隙520。在一實施例中,由空氣構 成間隙5 20。在另一實施例中,由具有25-40%的孔隙率 之摻雜碳的氧化物構成間隙5 20,如連同第6A-C圖所述 〇 參照第51圖,可圖案化電介質層518以在金屬互連 511或其各自的蓋層512的至少一部分上形成通孔溝槽 5 3 0。不直接在金屬互連511的上表面上或其各自的蓋層 512上的通孔溝槽530的任何部分可在電介質隔片516的 -15- 1351733 一部分上。根據本發明之—實施例,電介質隔片516提供 未著底之通孔溝槽530可著底之表面,如第51圖中所示 。參照第5J圖,可在電介質層5丨8上形成第二層的金屬 互連522與524。根據本發明之一實施例,金屬互連524 透過未著底通孔5 26與下層的金屬互連511連接。因此, 可形成具有不連接的電介質隔片之「氣隙」金屬互連架構 ’其提供包含到積體電路內之足夠的完整性以及提供未著 底之通孔「著底」之區域。 根據本發明之一實施例,可由空氣之外的材料塡充第 5H圖之間隙520,如第6A-C圖中所示。參照第6B圖, 可在第6A圖中所示的結構上沉積有空隙之電介質層660 (其與第5G圖中所示的結構類似)。有空隙之電介質層 660可由能使金屬互連610間有微不足道的電容耦合之任 何適合的材料所構成。在一實施例中,有空隙之電介質層 660的介電常數介於丨與2.5。在另一實施例中,有空隙 之電介質層660由具有25-40 %的孔隙率之摻雜碳的氧化 物所構成。在一實施例中,有空隙之電介質層660的介電 常數小於電介質層6 02的介電常數。可接著在金屬互連 610上或其各自的金屬蓋612上、在電介質隔片616上、 以及有空隙之電介質層660上沉積電介質層618。在一實 施例中,有空隙之電介質層660的介電常數小於電介質層 618的介電常數。因此,可形成具有不連接的電介質隔片 之「超低K氣隙」金屬互連架構’其提供包含到積體電 路內之足夠的完整性以及提供未著底之通孔「著底J之區 -16 - 1351733 域。 在圖案化形成隔片電介質層514以形成電介質隔片 516的期間(於上第5F與5G圖),不完全蝕刻程序可在 金屬互連上以及在電介質隔片之間的電介質層的部分上留 下形成隔片電介質層514之殘留部份。根據本發明之—實 施例,形成隔片電介質層514之不完全的圖案化會在電介 質層702之上以及金屬互連710之上造成「稍微連接」的 電介質隔片716以及殘留電介質材料770,如第7圖中所 示。因此,可形成具有稍微連接的電介質隔片之「氣隙」 金屬互連架構,其提供包含到積體電路內之足夠的完整性 以及提供未著底之通孔「著底」之區域。 雖上述的實施例考量到用於金屬互連之不連接的電介 質隔片,本發明不限於金屬互連的使用。可將導電奈米碳 管綑在一起並用作微互連,以將電子或半導體裝置包含入 積體電路中。根據本發明之一實施例,連同基於導電奈米 碳管之互連一起使用不連接的電介質隔片。因此,可在基 於導電奈米碳管之互連的側壁上形成不連接的電介質隔片 ,以減少與此種互連關聯的RC延遲、提供互連架構的耐 用性、或提供未著底之通孔可著底之表面。 因此,已描述包含電介質隔片的複數個金屬互連以及 形成此種電介質隔片的方法。在一實施例中,與相鄰的金 屬互連鄰接的電介質隔片互不連接。在另一實施例中,與 相鄰的金屬互連鄰接的電介質隔片稍微連接。在一實施例 中,電介質隔片可提供未著底之通孔可有效著底之區域。 -17- 1351733 【圖式簡單說明】 第1圖顯示根據本發明之一實施例的描繪著底通孔與 " 未著底通孔之具有不連接的隔片之複數個互連的剖面圖。 • 第2圖顯示根據本發明之一實施例的具有不連接的隔 片之一對互連的剖面圖,其中互連陷入下層的電介質層中 〇 φ 第3圖顯示根據本發明之一實施例的描繪假互連之具 有不連接的隔片之複數個互連的剖面圖。 第4圖顯示根據本發明之一實施例的具有不連接的隔 片之複數個互連的剖面圖,其描繪在金屬互連旁塡充有電 介質層之大間隔。 第5A-J圖顯示根據本發明之一實施例的代表包含形 成不連接的電介質隔片之步驟的複數個互連之形成的剖面 I 〇,1 圖〇 ♦ 第6A-C圖顯示根據本發明之一實施例的代表具有不 連接的電介質隔片之複數個互連之形成的剖面圖。 第7圖顯示根據本發明之一實施例的具有稍微連接的 電介質隔片之複數個互連的剖面圖。 【主要元件符號說明】 100 :結構 102 、 104 、 110 :金屬互連 106 :電介質層 -18- 1351733 1 08 :電介質隔片 1 1 2 :未著底通孔 1 1 4 :著底通孔 1 1 6 :阻障層 1 1 8 :蓋層 1 2 0 :間隙 200 :結構 202、204 :金屬互連 206 :電介質層 208 :電介質隔片 2 1 6 :阻障層 2 2 0 :間隙 3 00 :金屬互連 3 3 0 :假金屬互連 402、 404、 412、 414:金屬互連 406、440 :電介質層 500 :結構 502 :電介質層 504 :犧牲電介質層 506:圖案化的犧牲電介質層 5 0 8 :阻障層 510、511 :金屬互連 5 1 2 :蓋層 5 1 4 :形成隔片電介質層 -19- 1351733 516 :電介質隔片 5 18 :電介質層 5 2 0 :間隙 5 22、524 :金屬互連 ' 5 26 :未著底通孔 5 3 0 :通孔溝槽 602 :電介質層 φ 6 1 0 :金屬互連 6 1 2 :金屬蓋 616 :電介質隔片 618 :電介質層 660 :有空隙之電介質層 702 :電介質層 7 1 0 :金屬互連 7 1 6 :電介質隔片 # 77〇 :電介質材料 -20-
Claims (1)
1351733 ‘· ' π年ι ^日修(更)正本 附件t/i :第096115614號申請專利範圍修正本 日修正 質層之上 質層之上 該第一互 一與該第 該第一互 該第一互 該第二互 —與該第 第二互連 第二互連 互不連接 的第一間 民國100年2 J 十、申請專利範圍 1. 一種具有複數個互連的電子結構,包含: 第一電介質層; 第一互連,其中該第一互連係在該第一電介 t φ 第二互連,其中該第二互連係在該第一電介 ,以及其中該第二互連與該第一互連間隔; 第一電介質隔片,其中該第一電介質隔片與 連之側壁鄰接,其中該第一電介質隔片係在該第 二互連之間中,以及其中從該第一互連之上部至 連之底部該第一電介質隔片係朝外呈錐狀而離開 連之該側壁; 第二電介質隔片,其中該第二電介質隔片與 φ 連之側壁鄰接,其中該第二電介質隔片係在該第 二互連之間之中,其中從該第二互連之上部至該 之底部該第二電介質隔片係朝外呈錐狀而離開該 之該側壁,以及其中該第一與該第二電介質隔片 並且具有在該第一與該第二電介質隔片之間之中 隙;以及 第二電介質層,其中該第二電介質層在該第一與該第 二互連之上,其中該第二電介質層在該第一與該第二電介 質隔片之上,以及其中該第二電介質層在該第一與該第二 1351733 電介質隔片之間之中的該第一間隙之上。 2. 如申請專利範圍第1項之結構,其中該第一間隙 由空氣構成。 3. 如申請專利範圍第1項之結構,其中該第一與該 第二電介質隔片的介電常數大於該第一與該第二電介質層 的介電常數,以及其中該第一與該第二電介質層的介電常 數大於該第一間隙的介電常數。 4. 如申請專利範圍第3項之結構,其中該第一與該 φ 第二電介質隔片由氮化矽、碳化矽、摻雜氮之碳化矽、摻 雜氧的碳化矽、摻雜硼的氮化碳或摻雜硼的碳化矽構成, 其中該第一與該第二電介質層由二氧化矽、矽酸鹽、或具 有0-10%孔隙度之摻雜碳的氧化物構成,以及其中該第一 間隙由具有2 5-40%孔隙度之摻雜碳的氧化物或空氣構成 〇 5. 如申請專利範圍第1項之結構,其中該第一與該 第二電介質隔片的寬度實質上等於該第一間隙的寬度。 φ 6. 如申請專利範圍第5項之結構,其中該第一與該 第二電介質隔片的寬度在5-20奈米的範圍中。 7. 如申請專利範圍第1項之結構,進一步包含: 一通孔,其中該通孔的至少一部分在該第二電介質層 中,其中該通孔在該第一互連的上表面的—部分之上,以 及其中該通孔在該第一電介質隔片的上表面的一部分之上 〇 8. 如申請專利範圍第1項之結構,其中該第一與該 -2- 1351733 第二互連陷入該第一電介質層中。 9. 如申請專利範圍第1項之結構,進一步包含: 第三互連,其中該第三互連在該第一電介質層之上, 其中該第三互連與該第二互連間隔; 第三電介質隔片,其中該第三電介質隔片與該第二互 連的側壁鄰接,其中從該第二互連之上部至該第二互連之 底部該第三電介質隔片係朝外呈錐狀而離開該第二互連之 該側壁,以及其中該第三電介質隔片在該第二與該第三互 連之間之中; 第四電介質隔片,其中該第四電介質隔片與該第三互 連之側壁鄰接,其中該第四電介質隔片係在該第二與該第 三互連之間之中,其中從該第三互連之上部至該第三互連 之底部該第四電介質隔片係朝外呈錐狀而離開該第三互連 之該側壁,其中該第三與該第四電介質隔片互不連接並且 具有在該第三與該第四電介質隔片之間之中的第二間隙, 其中該第二間隙的寬度大於該第一與第二電介質隔片之間 之中的該第一間隙的寬度,以及其中該第二電介質層在該 第三與該第四電介質隔片之間之中的該第二間隙之中。 10. 如申請專利範圍第1項之結構,進—步包含: 第三互連,其中該第三互連在該第一電介質層之上, 其中該第三互連與該第二互連間隔,以及其中該第二互連 爲假互連; 第三電介質隔片,其中該第三電介質隔片與該第二互 連的側壁鄰接,以及其中該第三電介質隔片在該第二與該 -3- 1351733 第三互連之間之中,其中從該第二互連之上部至該第二互 連之底部該第三電介質隔片係朝外呈錐狀而離開該第二互 連之該側壁; 第四電介質隔片,其中該第四電介質隔片與該第三互 連之側壁鄰接,其中該第四電介質隔片係在該第二與該第 三互連之間之中,其中從該第三互連之上部至該第三互連 之底部該第四電介質隔片係朝外呈錐狀而離開該第三互連 之該側壁,其中該第三與該第四電介質隔片互不連接並且 φ 具有在該第三與該第四電介質隔片之間之中的第二間隙, 其中該第二間隙的寬度實質上等於在該第一與該第二電介 質隔片之間之中的該第一間隙的寬度,以及其中該第二電 介質層在該第三與該第四電介質隔片之間之中的該第二間 隙之上。 11·如申請專利範圍第1 〇項之結構,其中該第一與 該第二間隙由空氣構成。 12. 如申請專利範圍第10項之結構,其中該第一、 φ 該第二、該第三、及該第四電介質隔片的寬度實質上等於 該第一與該第二間隙的寬度。 13. —種製造具有複數個互連之電子結構的方法,包 含: 形成第一電介質層; 形成第一與第二互連,其中該第一與該第二互連形成 在該第一電介質層之上,以及其中該第一互連與該第二互 連間隔; -4 - 1351733 於該第一與該第二互連之上、沿著該第一與該第 連之側壁、以及在該第一與該第二互連之間之中的該 質層的上表面之上沉積形成隔片之電介質層; 移除在該第一與該第二互連之上以及在該第一與 二互連之間之中的該第一電介質層的該上表面之上的 成隔片之電介質層之區域的一部分,以形成與該第一 第二互連之該些側壁鄰接的電介質隔片,在位在該第 該第二互連之間的該些電介質隔片之間之中有間隙, 從該第二互連之上部至該第二互連之底部該第二電介 片係朝外呈錐狀而離開該第二互連之該側壁;以及 於該第一與該第二互連之上、在位在該第一與該 互連之間的該些電介質隔片之間之中的該間隙之上、 與該第一與該第二互連的該些側壁鄰接之該些電介質 之上形成第二電介質層。 1 4 .如申請專利範圍第1 3項之方法,其中移除 第一與該第二互連之上以及在該第一與該第二互連之 中的該第一電介質層的該上表面之上的該形成隔片之 質層之該些區域的該部分暴露出該第一與該第二互連 些上表面以及暴露出在該第一與該第二互連之間之中 第一電介質層之該上表面,以形成與該第一與該第二 之該些側壁鄰接之不連接的電介質隔片。 1 5 .如申請專利範圍第1 3項之方法,其中由化 氣沉積程序或由原子層沉積程序沉積該形成隔片的電 層,以及其中該形成隔片的電介質層由氮化矽、碳化 二互 電介 該第 該形 與該 一與 其中 質隔 第二 及在 隔片 在該 間之 電介 之該 的該 互連 學蒸 介質 矽、 -5- 1351733 摻雜氮之碳化矽、摻雜氧的碳化矽、摻雜硼的氮化碳或摻 雜硼的碳化矽構成。 16. 如申請專利範圍第13項之方法,其中該形成隔 片的電介質層由摻雜硼的氮化碳層構成,以及其中藉由使 氣體甲烷、二硼烷、及氨起作用而形成該摻雜硼的氮化碳 層。
17. 如申請專利範圍第13項之方法,其中移除在該 第一與該第二互連之上以及在該第一與該第二互連之間之 中的該第一電介質層的該上表面之上的該形成隔片之電介 質層之該些區域的該部分包含使用非等向性蝕刻程序。 18. 如申請專利範圍第13項之方法,其中該第一與 該第二電介質層由旋塗程序、化學蒸氣沉積程序、或基於 聚合物之化學蒸氣沉積程序所形成。
19. 如申請專利範圍第18項之方法,其中該第一與 該第二電介質層由二氧化矽、矽酸鹽、或具有0-10%孔隙 度之摻雜碳的氧化物所構成。 20. 如申請專利範圍第13項之方法,進一步包含: 在形成該第一與該第二互連之前在該第一電介質層上 形成犧牲電介質層:以及 在形成該第一與該第二互連之後以及在沉積該形成隔 片電介質層之前移除該犧牲電介質層,其中不影響該第一 電介質層地移除該犧牲電介質層。
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-
2006
- 2006-05-04 US US11/429,165 patent/US7649239B2/en not_active Expired - Fee Related
-
2007
- 2007-05-01 GB GB0819769A patent/GB2451373B/en not_active Expired - Fee Related
- 2007-05-01 CN CN2007800159995A patent/CN101438388B/zh active Active
- 2007-05-01 WO PCT/US2007/010484 patent/WO2007130368A2/en active Application Filing
- 2007-05-01 DE DE112007000966T patent/DE112007000966B4/de active Active
- 2007-05-02 TW TW096115614A patent/TWI351733B/zh active
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2009
- 2009-12-03 US US12/630,771 patent/US7923760B2/en active Active
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2011
- 2011-03-22 US US13/069,253 patent/US8394701B2/en not_active Expired - Fee Related
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CN101438388B (zh) | 2010-12-08 |
WO2007130368A2 (en) | 2007-11-15 |
US20110171823A1 (en) | 2011-07-14 |
DE112007000966B4 (de) | 2013-11-28 |
WO2007130368A3 (en) | 2007-12-27 |
GB2451373B (en) | 2011-03-09 |
GB2451373A (en) | 2009-01-28 |
DE112007000966T5 (de) | 2009-03-12 |
US8394701B2 (en) | 2013-03-12 |
US7923760B2 (en) | 2011-04-12 |
GB0819769D0 (en) | 2008-12-03 |
TW200811995A (en) | 2008-03-01 |
US20070257368A1 (en) | 2007-11-08 |
CN101438388A (zh) | 2009-05-20 |
US20100071941A1 (en) | 2010-03-25 |
US7649239B2 (en) | 2010-01-19 |
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