TWI333260B - An enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same - Google Patents

An enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same Download PDF

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TWI333260B
TWI333260B TW093100253A TW93100253A TWI333260B TW I333260 B TWI333260 B TW I333260B TW 093100253 A TW093100253 A TW 093100253A TW 93100253 A TW93100253 A TW 93100253A TW I333260 B TWI333260 B TW I333260B
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layer
gate
oxide
implant
field effect
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Matthias Passlack
Olin L Hartin
Marcus Ray
Nicholas Medendorp
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Motorola Inc
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    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
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    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
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    • H01L29/43—Electrodes ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/49—Metal-insulator-semiconductor electrodes, e.g. gates of MOSFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7784—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with delta or planar doped donor layer
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    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/778—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface
    • H01L29/7782—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET
    • H01L29/7783—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material
    • H01L29/7785—Field effect transistors with two-dimensional charge carrier gas channel, e.g. HEMT ; with two-dimensional charge-carrier layer formed at a heterojunction interface with confinement of carriers by at least two heterojunctions, e.g. DHHEMT, quantum well HEMT, DHMODFET using III-V semiconductor material with more than one donor layer
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    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/12—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed
    • H01L29/20—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by the materials of which they are formed including, apart from doping materials or other impurities, only AIIIBV compounds

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Description

1333260 玖、發明說明： 先前專利申請案件參考資料 本專利申請文件已於2003年1月9日於美國辦理專利申 請，並經編定為第10/339,379號申請案。 【發明所屬之技術領域】 概言之，本發明係與各種化合物半導體場效裝置有關， 更明確言之，係與各種增強型金屬-氧化物半導體場效電晶 體以及其各種製造方法有關。 【先前技^術】 增強型金屬-氧化物場效半導韙（EMOSFET)乃係一種設 計金屬-氧化物半導體（MOS)積體電路時最被廣泛使用之裝 置。矽互補MOS(CMOS)是一種可供EMOSFET設計時採用 之成熟技術，可提供設計簡單及耗電量低之雙重效益。但 是，Group III-V化合物半導體技術，由於其具備超高速度/ 功率性能及效率等特性，因而，仍然是頗受歡迎之 EMOSFET設計技術。 有一種EMOSFET之設計是採用自我調準離子植入技術 形成低電阻性源極及汲極延伸部分。但是，製造含有植入 離子式源極及汲極延伸部分之III-V化合物半導體 EMOSFET時，貝有技術上的困難之處。植入材料須視其本 身與結格中Group III或Group V排列位置之關係而決定其 究應是一施體雜質抑或應是一受體雜質。再者，形成源極 及汲極延伸部分時所使用之靭化處理溫度通常均高於 700°C (以η-通道裝置為例），可能無法與半導體/閘極氧化物 1333260 介面之穩疋度要求相容。用以形成源極及汲極之離子植入 處理法也可此在半導體/閘極氧化物介面造成不需要之陷 阱密度問題。而且，在大多數用以形成源極及汲極延長部 分之技術均要求將閘極電極當作一種遮罩，因而必須在植 入離子之耵應先形成閘極，如此，則會使製造技術之使用 彈性丈限。此外，該等裝置之源極及汲極延長部分之片阻 值在800°C以上靭化溫度環境中會高達每平方公分3〇〇至 400歐姆；而在靭化溫度約為7〇〇<t時，則會高達5〇〇歐姆/ 平方公分，。 因此，乃需要一種「無植入物」III-V化合物半導體 EMOSFET。本說明書中所稱「無植入物」一詞應指不含有 以離子植入法形成之源極及汲極延長部分。同時也需要開 發一種可用以製造無植入物式增強型金屬·氧化物半導體 %效電晶體之生產方法。本發明之其他應具備特點與特 性，可由下列配合各種附圖所提供之說明及隨附之申請專 利範圍等資料中獲悉。 【發明内容】 本發明係提供一種無植入物增強型金屬—氧化物半導體 %效電晶體（EMOSFET)。該EMOSFET有一 ΐπ-ν化合物半導 體基體，以及與該III-V化合物半導體基體重疊之一磊晶層 結構。該磊晶材料層有一通道層以及至少一層摻雜層。有 閘極氧化物層與該磊晶層結構重疊。該EM〇SFET另亦包 括一個與該閘極氧化物層重疊之金屬閘極，以 /、 σ么曰日 層結構重疊之源極及汲極電阻性接觸層。 ^33260 【實施方式】 以下提供之詳細說明係介紹本發明之數種具體實例，並 無意限制本發明之内容或本發明之適用範圍。而係提供一 種如何具體實施本發明之範例。在不偏離本說明書附錄中 所列申明專利範圍所說明之本發明適用範圍之原則下，可 對本說明書中提供之各種具體實例進行各種不同的修改與 變更設計。 圖1所不乃係依據本發明某一具體實例所設計之一種增 強型化合，物半導體M0SFET裝置10之剖面簡圖。裝置ι〇有二 個利用任何適用之單晶爪-V化合物半導體材料製成之基體 12。理想的基體12材料，是採用半導體業界常用之一種高 單晶鎵碎化合物（GaAs)基質。 有一磊晶層結構14重疊在基體12上。該磊晶層結構丨斗含 有一緩衝層16, 一通道層18，及一間隔層2〇。緩衝層16， 通道層18和間隔層20,可利用任何可用的m_v材料作成， 但是，理想的情形是，緩衝層16，通道層18 ,及間隔層2〇 各自使用不同的III-V材料製成。在某一可採用之本發明具 體實例中，緩衝層16是採用鎵砷化合物（GaAs)為材料，通 道層18是採用銦鎵砷化合物（InGaAs)為材料，而間隔層 係採用鋁鎵砷化合物（A1GaAs)形成。應注意者乃是，在 中雖然該緩衝層16是一層與基體12分離之薄層，但該緩衝 層16和基體12則可製成一連續層，端視其各自使用之材料 而定。 磊晶層結構14亦包含至少一層摻雜層’如圖丨所示摻雜層 丄 22。雖然圖1所示磊晶 a、··。構1 4含有二層摻雜層，但讀者應 〇 ’該磊晶層結構14可人士 * „ ^ 』3有1層、兩層或更多層摻雜層。 摻雜層22可設置在诵$既， 層18的上方、下方及（或）通道層18 内部。摻雜層22，月 1何附加摻雜層可含有半導體業界熟 知之任何可用之摻雜 ^雜成伤’諸如，矽（Si)(n-波道裝置）及鈹 (Be)(p-波道裝置）。如 _ 乂下棱供之更詳細說明，該磊晶層結 構14之各摻雜層可特 特別、疋（亦即，22的摻雜處理程度）可預 先選定在可達到執行辦％ 丁增強型刼作之任一特定MOSFET組態
之摻雜程，度。 一 尸# 物層24重疊在晶膜層結構14上方。該閑極 氧化物層24最好含有鎵氧化物（wo;)，但是，該間極氧化 物層24可含有任何其他可用之氧化物材料。 將-種可在間極氧化物材料中保持穩定特性之金屬問極 %重疊在上述間極氧化物層24上。如以下之詳細說明，選 擇該金屬閉極26之材料時，可選擇能夠具備可達成某種特 定增強型MOSFET組態功能之材料。
源極及沒極電阻性接觸點28及卿成後係重疊在該蟲晶 層、，。構14上方，並由源極及没^存取區32將其_金屬間極 26分隔開”隸及沒極存取區32分別包括在源極電阻性接 觸點28和金屬閘極26之間，以及在沒極電阻性接觸㈣和 金屬閘極26之間的那些蟲晶層結構14區域。源極及汲極電 阻性接觸點28、30之材料可採用半導體業界熟知之任何^ 適用導電性材料》 裝 置10之增強型操作可根據金屬閘極26之 功函數和摻雜 -9- 丄 :之每雜程度二者之間的關係實現之。雖然該蟲晶層， 構14之各層摻雜層22可提供自由載子之功能，從而物 在&晶層結構Μ内所需要之離子植入式源極及及極延長 部分，而不需要-可適用之金屬閘極，但是，纟該捧雜； 邱可能以不利的方式使裝置此臨限電壓偏移，因㈣ 礙增強型操作之執行。例如，該等摻雜層22可能使— η型通 ‘MOSFET之臨壓變成一負值’因而妨礙增強型操作之執 行。使用-種具備一種適當的高功函數之金屬閘極％即可 補償此穠臨限電壓偏移現象，並產生—種大於零之臨限電 壓，從而，可使增強型操作繼續執行 '同樣地，各該摻雜 層22亦可使一 Ρ型通道MOSFET之臨限電壓變成一正值，因 而，妨礙增強型操作之執行。如果’使用一種具備某一適 畐之低功函數之金屬閘極26，即可補償此種臨限電壓偏移 現象並了產生一低於零之臨限電壓，從而，可使增強型 操作繼續執行。 在不偈限於任一特定原理之原則下，在本發明之某一具 體貫例中’該金屬閘極26之功函數和各該摻雜層22之摻雜 程度之間的關係’可利用下列一次方程式求得之：
Ps = 1/QS χ μ x q . (i) 式中之Ps代表各該源極及没極存取區32之片阻率（歐姆7值/ 平方英吋），μ代表通道移動率，而q則代表電子之電荷值（i 6 χ 10'丨9 As)及
Qs = (εοχ x (Om-〇(0)))/(tox x q) > (2) 式中Qs代表在源極及汲極32内量得之該等摻雜層22之片電 4K)JJ7 doc • 10· 1333260 荷（⑽〜），^代表閘極氧化物層24之介質常數，^表閘極 氧化物層24之厚度’ (^代表金屬閘極％之功函數，。(〇)代 表金屬閘極26對某-特定臨界電塵且無換雜層時之參考功 函數’（Φ⑼可藉由：維裝置模擬法取得之）。讀者應瞭解， 雖然金屬閘極26之功函數和各摻雜層22之摻雜程度之間的 關係可由上述一次方裎式量得，但也可利用其他高次方程 式量得之。
附表1 附表1及附表2係用以說明某一 〇型_通道m〇sfet之金屬 閘極26之功函數和各該摻雜層22之摻雜程度二者之間的關 係範例。，在本範例中，其中之片電阻值片電荷Qs是以 :列各項參數之設定值為其計算之依據：繼數^為2〇 限電壓VT=().3伏特；m道移動常數以等於测 ⑽/Vs ; Φ(()Κ6 eV ;以及位於該氧化物含晶體層結構介 面之-種電荷質量中心。該項電荷質量中心的實際位置可 能因操作條件及該含晶體層結構型態之不同而有變動，因 和本範例中假設之位置稍有不同 ^)0447 doc -11 - 1333260
DjOhm/Square), VT=0.1V Φαι(εν) t〇x (nm) 50 40 30 20 10 957 4.7 4786 3829 2871 1914 4.8 2393 1914 1436 957 479 4.9 1595 1276 957 638 319 5.0 1196 957 718 479 ?3〇 5.1 957 766 574 383 1 Q I 5.2 798 638 _Jl9~ 3 19 160 5.3 684 547 4 10 273 137 5.4 598 479 359 239 120 5.5 532 425 2 1 3 1 479 383 287 191 •LUO 96 5.7 1 435 348 ___2^61 174 87 • lt/_L主勹 圖2所示係說明在五個不同的閘極氧化物厚度及Vt=0 3V之 設定條件下該金屬閘極％之功函數和源極及汲極存取區之 片阻率Ps:者之間的關係。圖中之曲線4〇代表厚度為5〇麵 ^閘極氧化物24之片阻率；曲線42代表厚度為4Qnm之問極 氧化物24之纽率；曲線44代表厚度為3Qnm之閘極氧化物 24之片阻率，曲線46代表厚度為2〇職之問極氧化物μ之片 阻率，曲線48代表厚度為1〇 nm之閘極氧化物24之片阻率。 該曲線圖所示足可證明，裝置1〇之金屬閘極％之功函數愈 高，其片阻率就愈低》同理，該裝置1〇之閘極24之厚度愈 薄’其片阻率就愈低。 附表3及附表4分別說明，在臨限電壓^^為〇5伏特介質 常數為〜為20,通道移動率為p59〇〇cm2/Vs，參考功函數 Φ(〇)為4.8 eV，及電荷質量中心位於該氧化物含晶體層結構 介面等設；ε條件下’所計算出來之片阻值〜和片電荷量 •12- 1333260 之數值。同樣地’ 1亥電荷質量中心之實際位址會因各種操 作條件和磊晶層結構型態之不同變更，因而可能與本範例 中所設定之位置之間有一差
附表3
下一個乾例係說明本發明某一具體實例所設計之可用以 製造一種類似圖1所示結構1〇之£]^〇317]£7半導體結構之方 法。參閱圖3 ,該方法係自步驟50開始，提供一個單晶體式 III-V半導體結構。依據本發明某一可採用具體實例之設 計，該半導體結構是—種單晶式鎵砷化合物（GaAs)基體。 1333260 其次，係將摻雜晶膜層結構14重疊在該—單晶式嫁神化 合物基體12上面。該晶膜層結構之形成是先產生一緩衝層 i 6(最好以GaAs為材料），再以銦鎵砰化合物（inGaAs)為材 料製作-通道層18’然後’利用A1GaAs化合物為材料製作 -間隔層20。磊晶層結構14之製作方法，包括但不限於分 子束外延生長技術（咖）以及金屬有機化學氣體沉積技術 (MOCVD)。王里想方法，是在一種超高度真空⑽^醜系 統内形成，以使形成後之半導體具有一種符合原子序列排 列以及化，學方面極為清潔等要求條件之表面。 在磊晶層結構14生長過程中，利用任何標準摻雜技術在 通道層18的上面、下面或中間生長一或多層摻雜層22。在 本發明某一可採用具體實例t，係採用半導體業界熟知且 常用之三角摻雜法來形成摻雜層22。因此，如步驟”中之 。尤明，生成某一厚度之蟲晶層結構14，並如步驟Μ中之說 明，再以二角摻雜法形成一第一三角摻雜層22。之後，可 繼續執行另一次三角摻雜程序，生長成另一槿厚度之第二 三角摻雜層。此一製造方法可繼續進行，一直到形成所需 數®之三角摻雜22時為止。在步驟56中，可使該磊晶層14 生長至最後之厚度。 形成三角摻雜層2 2時所使用之摻雜物之摻雜程度可利用 由上述各項公式算出之標準條件決定之。例如，如果是一 種需要將其臨限電壓值設定為0.3伏特之^型通道 EMOSFET，可利用附表1及2所列之標準條件，參閱附表i 及2，例如，該n型通道MOSFET之設計條件限定在閘極氧化 90447 doc -14- υυ 物26之厚度為3〇奈米，片卩且率為 方阻早為500歐姆/平方公分，以下， J由附表2之數據得知，即可採 c ^ 丨」妹用具有—功函數為5.2 eV至 •…之一種金屬閘㈣。如有現成的棒…ev)可資 利用製作金屬閘極26，則其片阻率如符合4iq歐姆/平方公 分之標準，即可採用。如此， 由附表1可知，如有一種厚度 為财米，功函數為〜=5.3eV之間極氧化物，則其三角捧 雜程度可能需要符合2.或以下之標準。因此， 可將摻雜層22摻雜至大約為2.“ 1〇1、_2或以下之程度即 可符合V….3V之標準條件，亦即，始可達到符合問極氧 化物24之厚度為3()奈米以及銦金屬開極柯準條件所製成 之可用η·型通道增強型M〇SFET。如果以㈣AM為金屬 閘極26之材料，則由附表2可知，其片阻率須能符合26 m 姆/平方公分之極低標準始可採用。由附表i可知，如果所 採用之閘極氧化物’其厚度為3〇奈米，功函數為φ, 5.7 eV’則其三角摻雜程度須符合大約為4丨X 1〇12啦2或 更低之標準條件始可採用。因此，須將摻雜層⑵參雜至大 ’勺為“⑽⑽彡更低之程度始能符合〜^❹”之伏特 之私準’’亦即’始可達到合有一厚度為3〇奈米之閘極氧化 物24與鉑金屬閘極％材料所製成之可用η型通道增強型 MOSFET。 再參閱圖3,如步驟58所示，有一閘極氧化物層24形成之 後係重在磊晶層結構14的上方。可用以形成與ΠΙ ν化合 物半導體基體重疊之閘極品質氧化物的各種方法，已為業 界熟知。其中之一種方法已於2〇〇〇年12月12日頒發給％等 90447 doc -15- 1333260 該項美國專利之 人之美國第6,159,834號專利中公開發表， 全部已列為本專利申請說明書之參考依據 如步驟60之說明，係利用半導體業界熟知之標準處理方 法將源極及沒極電阻性接點28及30以沉積方式番最石 八置$在έ亥蠢 晶層結構14的上方。 其次，如步驟62所示，金屬閘極26於形成之後，係重疊 在閘極氧化物層24之上方。該金屬閘極26之形成，係先二 一種金屬層以沉積處理方法覆蓋在閘極層24上方，然後再 利用半導;體業界熟知之標準石版印職，削切技術或㈣ 技術將該金屬層設定成一定之圖型。如以上之說明，可根 據摻雜層22之摻雜程度關係選定金屬閘極％應採用之材 料。 在本發明之某一具體實例，可利用簡化能量帶曲線圖說 明之。圖4所示係說明以先前技術所製造之em〇sfet(亦 即，含有離子植入式源極及汲極延伸部分之em〇sfet)之簡 化能量帶曲線圖7(^在該能量帶曲線圖7〇中，72係代表一 πι-ν化合物半導體基體72，74係代表一未摻雜式通道層， 76係代表一間隔層76，78係代表一閘極氧化物層，8〇係代 表一金屬閘極，84係代表一 Fermi準位，82係代表一個在關 閉狀態之導電帶邊緣，86係代表一個在接通狀態中之導電 帶邊緣86。如圖4所示’在閘極氧化物層和間隔層％之間 的介面處之Fermi準位，當該]^〇灯]£1：從關斷狀態被轉換至 接通狀態時’即會自大約位於該關斷狀態中間間隙之位置 移動至間隔層導電帶邊緣附件。在圖4所舉之特定具體實例 doc -16· 1333260 觀之’該導電帶邊緣處之電壓（Ee)僅比在接通狀態時之 Fermi準位高約〇2ev如參數數字88所示。 圖5所示乃是依據本發明某一具體實例所設計之一種 EMOSFET的簡化能量曲線圖90。在該圖5所示簡化能量曲 線圖90中，92係代表一個πΐ-ν化合物半導體基體，94係代 表一通道層’ 96係代表一間隔層，98係代表一閘極氧化物 層，100係代表一金屬閘極，104係代表一Fermi準位，106 係代表在關斷狀態時之一導電帶邊緣，1 〇8係代表在接通狀 態時之二導電帶邊緣。另亦有一摻雜層1 02。如圖5所示， 在閘極氧化物98和間隔層96之間的介面處之Fermi準位 1〇4 ’當該裝置從關斷狀態轉換至被接通狀態時，即會移動 至間隔層導電帶邊緣附近。在圖5所示本發明具體實例中， 該導電邊緣之電壓（Ee)比該Fermi準位電壓僅高出大約 〇.5(eV)伏特，如圖中以參考代號11〇處所代表之電壓。 圖6所示曲線圖係說明在陷阱能量Ετ和與一 Ga2〇3_GaAs "面之導電τρ·邊緣Ec有關之陷啡總密度之間所量得之關 係。因為該Fermi準位係朝向Ec移動，因而，凡與專供低於 能量Ετ準位使用之各陷阱，均會被填滿（充電），而專供高於 能量Ετ準位使用之各陷阱，均保持淨空（中性）狀態。如圖中 之曲線120所示，凡已填充低於匕準位（約為4 χ 1〇丨2 eV^O.〗eV之Fermi準位之各陷阱之總密度（如圖4所示與先 前技術有關之曲線圖）遠超過已填充低於 準位之各陷㈣密(度： 所示之曲線圖）。 -17- 1333260 圖7所示剖面簡圖係說明依據本發明一具體實例所設計 之-種增強型化合物半導體刪阳裝置i3Q之結構圖。圖 中以圖1所示相同元件參考代號之各元件，係與^中各該 元件相同之元件。該裝置13G包含：—合物半導體基 體12,以及與該基體12重疊之一層蟲晶層14。該蟲晶層二 則含有緩衝16,通道層18，—間隔層2()，和—或多層推雜 層22。裝置130另亦含有間極氧化物心’金屬問極％，以 及源極及汲極電阻性接點2 8及3 〇。
衣置1^0另亦包含一場屏132。場屏可用於各種裝置内， 包括但不限於需具備高崩潰電壓之供電裝[形成該場屏 b2BT可使其重疊在閘極氧化物層24上面，或如圖7所示， 使其部分陷入閘極氧化物24之内。該場屏132可設定一片盥 -輕度摻及極(LDD)區相㈣域。在該場屏下方之區域 中之自由載子之局部空乏可受控於閘極氧化物層24内之至 少局部陷人場屏132，及/或以適當功函數之金屬製造該場 屏 132。
參閱圖8，在本發明另一具體實例中，其中之裝置14〇可 採_用-種與前述各種摻雜屏22不同之導電性低摻雜植入物 之製法，以降低在該磊晶層結構丨4中LDD區144内之自由載 子氆度。各式LDD區域已為業界熟知並被廣泛採用於半導 體裝置例如M0SFET内之結構。在各式n型通道裝置内，低 雜質受體植入處理需要以大約6〇〇 口高溫執行一 理步驟，A -高溫與問極氧化物4結構介面之帛熱處理溫 度條件相若。 »«W4 7d〇c -18 - 1333260 應說明者乃係’可對本發明所揭露之EMOSFET之製造方 法進行任何不同之修改，以製造符合各種特定應用目的需 要之不同組態。例如，圖9所示剖面結構簡圖即係用以說明 依據本發明另一種具體實例所設計之一種增強型化合物半 導體MOSFET裝置150。圖9中以圖1中所用相同元件代號之 各種元件與圖1中所使用之各相關元件完全相同。裝置1 5 〇 包含一 III-V化合物半導體基體12及磊晶層結構14(係重疊 在該基體12上面）。該磊晶層結構14包含緩衝層16，通道層 18，間隔^層20 ’以及一或多層摻雜層22。裝置150另亦包含 閘極氧化物層24，和源極及汲極電阻性接點28及30。在本 具體範例中，裝置150另亦包含一金屬階梯式閘極152。如， 以上對金屬閘極26所提出之相關說明，金屬階梯式閘極152 之材料可選用一種具有一種可使某一特定MOSFET結構型 態能執行增強型操作功能之一種金屬材料。金屬階梯式閘 極152係藉由一介電層154形成之汲極存取區32而與隔離。 該介電層154可含有矽氮化合物，矽氧化物或任何其他適用 之絕緣材料。 在以上說明中，已對若干特定具體實例提供相關說明。 但是，對本技術具有普通技術背景者當可瞭解，在不偏離 本發明中w專利祀圍所載事項之原則下可對各種具體實例 進行不同的修改及變更。因&，可將本說明所載内容及各 項附圖視為具有說明性而非限制性之說明H，該等修 改内必應納入本發明適用範圍之内。 以上已就本發明之若干特定具體實例的各種益處，優 90447 doc -19- 點’以及各種問題之解決辦法提供詳細說明。但是，任何 ^些应處’優點，問題解決辦法，以及導致此等益處，優 二及問題解決辦法發生甚或更為明顯之任何元件，並非 ,、乃係任或全部申請專利範圍所涵蓋之最具關鍵 7最*要及最必要之特點或元件。在本說明書中所稱之 「包含」、「含有」，或任何其他不同表達方式之字辭，旨 在涵蓋-種非排他性包含的意義，含有某些元件之任一種 方法、程序、物品或裝置’並非只是包括該等元件，而係 可能也包括在該等程序、方法、物品或裝置内所包含之其鲁 他元件。 【圖式簡單說明】 本發月係以舉例方式說明，並不偈限於本說明書中檢附 之各種附圖，此等附圖，包括： - 圖1所示用以說明依據本說明某一具體實例所設計之_ 種增強型金屬氧化物半導體場效電晶體之刳面簡圍； 圖2所示用以表示依據本發明某—具體實例所設計之— 種增強型金屬氧化物半導體場效電晶體中金屬閘極之功函鲁 數及片阻率之間關係的曲線圖； 圖3所示用以說明依據本發明某一具體實例所設計之形 成一種增強型金屬氧化物半導體場效電晶體的製造方法之 作業流程圖； 圖4所示用以說明依據先前技術某一具體實例所設計之 一種增強型金屬氧化物半導體場效電晶體之能量帶曲線 rgi · 圖， 90447 d〇C -20- 1333260 圖5所示用以說明依據本發明某一 增強型金屬氧化物半導體場效電晶體之能量帶!曲又線十圖之種 ^所不係用以表示依據本發明某—具體實例設計之一 八，氧：物半導體電容器中於-鎵氧化物/鎵砷化合物 "面所量得之陷阱能量和總陷阱載子密度二者之 的曲線圖，· r' 圖7所示係'說明依據本發明某—具體實例所設計之—種 增強型金屬氧化物半導體場效電晶體之結構剖面圖； 圖8所#係說明依據本發明另一具體實例所設計之—種 增強型金屬氧化物場效電晶體之結構剖面圖；及 圖9所示係說明依據本發明另一具體實例所設計之—種 增強型金屬氧化物場效電晶體之結構剖面圖； 熟悉此項技術者當可瞭解，各附圖中之各種元件係以簡 單明確之目的繪製而並非依實體比例繪製。例如：各附圖 中某些元件之尺碼與其實際尺碼相較似嫌過份誇張但其 目的係幫助讀者更易於瞭解本發明之各種具體實例而已。 【圖式代表符號說明】 10, 130, 150 增強型化合物半導體MOSFET裝置 12 (半導體）基體 14 蠢晶層結構 16 緩衝層 18, 74, 94 通道層 20, 76, 96 間隔層 22, 102 摻雜層 90447.doc -21 - 1333260 24, 78, 98 閘極氧化物層 26, 80， 110 金屬閘極 28 源極電阻性接點 30 汲極電阻性接點 32 >及極存取區 70, 90 能量帶曲線圖 72, 92 III-V化合物半導體基體 82， 106 關斷狀態 84, 104 , Fermi準位 86, 108 接通狀態 110 傳導係數參考代號 132 場屏 152 金屬階梯式閘極 154 介電層 屮>*u7 doc -22 -

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1333260
第093100253號專利申請案 中文申請專利範圍替換本(99年5月） 拾、申請專利範圍： 1. 一種無植入物之增強型金屬氧化物半導體場效電晶體 (EMOSFET)，包含： 一 III-V化合物半導體基體； 一蠢晶層結構’重疊在該ΙΠ_ν化合物半導體基體上， 該蟲晶材料層包含一通道層，及至少一層摻雜層； —閘極氧化物層，重疊在該磊晶層結構上；及 —金屬閘極，重疊在該閘極氧化物層上；及源極及汲 極電阻接點’重疊在該磊晶層結構上，其中該增強型金 屬氧化物半導體場效電晶體沒有與該至少一層滲雜層相 同之摻雜物型式的源極與汲極延伸植入。 2. 如申請專利範圍第1項之無植入物增強型金屬氧化物半 導體％效電晶體，該至少一層之摻雜層含有一三角摻雜 層。 3. 如申專利範圍第1項之無植入物增強型金屬氧化物半 導體場效電晶體，該磊晶層結構包含重疊在該通道層上 面’並在該閘極氧化物層下方之一層間隔層。 4. 如申睛專利範圍第1項之無植入物增強型金屬氧化物半 導體场效電晶體，另亦含有至少一部分係位於該間極氧 化物層内之一層場屏層。 5. 如申凊專利範圍第丨項之無植入物增強型金屬氧化物半 V體場效電晶體，另亦包含_場屏，重疊在該層間極氧 化物上面。 6.如申凊專利範圍第i項之無植入物增強型金屬氧化物半 90447-990521.doc 1333260 導體場效電晶體，另亦包含一 石曰蛀a •払雜度植入區，位於該 麻日日層結構内，該一低搀雜 一 雜又植入區之傳導型式至少與 一層上述摻雜層之傳導型式相反。 7. 種用以製造無植入物增強 •金屬氧化物半導體場效電 曰日體之方法，其包含下列各項步驟·· 提供一種III_V化合物半導體基體； 生長-層具有苐-種厚度之一層蟲晶層結構，重疊在 該III-V化合物半導體基體上面；
、對該第-厚度之蟲晶層結構執行摻雜處理，以便在上 述磊晶層結構之第一種厚度範圍内形成一摻雜層； 生長該磊晶層結構，使其厚度到達一第二厚度； 形成一閘極氧化物層，以重疊在該磊晶層結構上； 形成源極及汲極電阻性接點並使其重疊在該磊晶層結 構上面； 形成一金屬閘極，重疊在該閘極氧化物層上面，及 用以在上述磊晶層結構内形成一低摻雜度植入區，且
使該低摻雜度植入區之傳導型式恰與上述摻雜層之傳導 型式相反。 90447-990521.doc 2-
TW093100253A 2003-01-09 2004-01-06 An enhancement mode metal-oxide-semiconductor field effect transistor and method for forming the same TWI333260B (en)

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Families Citing this family (77)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4601263B2 (ja) * 2003-04-25 2010-12-22 三菱電機株式会社 電界効果トランジスタ
US7119381B2 (en) * 2004-07-30 2006-10-10 Freescale Semiconductor, Inc. Complementary metal-oxide-semiconductor field effect transistor structure having ion implant in only one of the complementary devices
US20060102931A1 (en) * 2004-11-17 2006-05-18 Thomas Edward Kopley Field effect transistor having a carrier exclusion layer
US7548112B2 (en) * 2005-07-21 2009-06-16 Cree, Inc. Switch mode power amplifier using MIS-HEMT with field plate extension
US7432565B2 (en) * 2005-09-27 2008-10-07 Freescale Semiconductor, Inc. III-V compound semiconductor heterostructure MOSFET device
US7429506B2 (en) * 2005-09-27 2008-09-30 Freescale Semiconductor, Inc. Process of making a III-V compound semiconductor heterostructure MOSFET
US20070090405A1 (en) * 2005-09-27 2007-04-26 Matthias Passlack Charge compensated dielectric layer structure and method of making the same
TW200830550A (en) * 2006-08-18 2008-07-16 Univ California High breakdown enhancement mode gallium nitride based high electron mobility transistors with integrated slant field plate
US7682912B2 (en) 2006-10-31 2010-03-23 Freescale Semiconductor, Inc. III-V compound semiconductor device with a surface layer in access regions having charge of polarity opposite to channel charge and method of making the same
US9209246B2 (en) 2007-04-12 2015-12-08 The Penn State University Accumulation field effect microelectronic device and process for the formation thereof
US8569834B2 (en) * 2007-04-12 2013-10-29 The Penn State Research Foundation Accumulation field effect microelectronic device and process for the formation thereof
US7799647B2 (en) * 2007-07-31 2010-09-21 Freescale Semiconductor, Inc. MOSFET device featuring a superlattice barrier layer and method
US7692224B2 (en) * 2007-09-28 2010-04-06 Freescale Semiconductor, Inc. MOSFET structure and method of manufacture
JP5595685B2 (ja) * 2009-07-28 2014-09-24 パナソニック株式会社 半導体装置
WO2011027577A1 (ja) 2009-09-07 2011-03-10 住友化学株式会社 電界効果トランジスタ、半導体基板、電界効果トランジスタの製造方法及び半導体基板の製造方法
US20110068348A1 (en) * 2009-09-18 2011-03-24 Taiwan Semiconductor Manufacturing Company, Ltd. Thin body mosfet with conducting surface channel extensions and gate-controlled channel sidewalls
US8421162B2 (en) 2009-09-30 2013-04-16 Suvolta, Inc. Advanced transistors with punch through suppression
US8273617B2 (en) 2009-09-30 2012-09-25 Suvolta, Inc. Electronic devices and systems, and methods for making and using the same
US8304301B2 (en) * 2009-11-18 2012-11-06 International Business Machines Corporation Implant free extremely thin semiconductor devices
US8530286B2 (en) 2010-04-12 2013-09-10 Suvolta, Inc. Low power semiconductor transistor structure and method of fabrication thereof
US9490179B2 (en) 2010-05-21 2016-11-08 Semiconductor Energy Laboratory Co., Ltd. Semiconductor element and semiconductor device
US8569128B2 (en) 2010-06-21 2013-10-29 Suvolta, Inc. Semiconductor structure and method of fabrication thereof with mixed metal types
US8759872B2 (en) 2010-06-22 2014-06-24 Suvolta, Inc. Transistor with threshold voltage set notch and method of fabrication thereof
KR20130105804A (ko) 2010-08-31 2013-09-26 스미또모 가가꾸 가부시키가이샤 반도체 기판 및 절연 게이트형 전계 효과 트랜지스터
CN103069553B (zh) 2010-08-31 2015-08-19 住友化学株式会社 半导体基板、绝缘栅极型场效应晶体管以及半导体基板的制造方法
US8377783B2 (en) 2010-09-30 2013-02-19 Suvolta, Inc. Method for reducing punch-through in a transistor device
US8404551B2 (en) 2010-12-03 2013-03-26 Suvolta, Inc. Source/drain extension control for advanced transistors
US8461875B1 (en) 2011-02-18 2013-06-11 Suvolta, Inc. Digital circuits having improved transistors, and methods therefor
JP2012195579A (ja) 2011-03-02 2012-10-11 Sumitomo Chemical Co Ltd 半導体基板、電界効果トランジスタ、半導体基板の製造方法および電界効果トランジスタの製造方法
US8525271B2 (en) 2011-03-03 2013-09-03 Suvolta, Inc. Semiconductor structure with improved channel stack and method for fabrication thereof
US8400219B2 (en) 2011-03-24 2013-03-19 Suvolta, Inc. Analog circuits having improved transistors, and methods therefor
US8748270B1 (en) 2011-03-30 2014-06-10 Suvolta, Inc. Process for manufacturing an improved analog transistor
US8796048B1 (en) 2011-05-11 2014-08-05 Suvolta, Inc. Monitoring and measurement of thin film layers
US8999861B1 (en) 2011-05-11 2015-04-07 Suvolta, Inc. Semiconductor structure with substitutional boron and method for fabrication thereof
US8811068B1 (en) 2011-05-13 2014-08-19 Suvolta, Inc. Integrated circuit devices and methods
US8569156B1 (en) 2011-05-16 2013-10-29 Suvolta, Inc. Reducing or eliminating pre-amorphization in transistor manufacture
US8735987B1 (en) 2011-06-06 2014-05-27 Suvolta, Inc. CMOS gate stack structures and processes
US8995204B2 (en) 2011-06-23 2015-03-31 Suvolta, Inc. Circuit devices and methods having adjustable transistor body bias
US8629016B1 (en) 2011-07-26 2014-01-14 Suvolta, Inc. Multiple transistor types formed in a common epitaxial layer by differential out-diffusion from a doped underlayer
WO2013022753A2 (en) 2011-08-05 2013-02-14 Suvolta, Inc. Semiconductor devices having fin structures and fabrication methods thereof
US8748986B1 (en) 2011-08-05 2014-06-10 Suvolta, Inc. Electronic device with controlled threshold voltage
US8645878B1 (en) 2011-08-23 2014-02-04 Suvolta, Inc. Porting a circuit design from a first semiconductor process to a second semiconductor process
US8614128B1 (en) 2011-08-23 2013-12-24 Suvolta, Inc. CMOS structures and processes based on selective thinning
US8713511B1 (en) 2011-09-16 2014-04-29 Suvolta, Inc. Tools and methods for yield-aware semiconductor manufacturing process target generation
US8803242B2 (en) * 2011-09-19 2014-08-12 Eta Semiconductor Inc. High mobility enhancement mode FET
US9236466B1 (en) 2011-10-07 2016-01-12 Mie Fujitsu Semiconductor Limited Analog circuits having improved insulated gate transistors, and methods therefor
US8895327B1 (en) 2011-12-09 2014-11-25 Suvolta, Inc. Tipless transistors, short-tip transistors, and methods and circuits therefor
US8819603B1 (en) 2011-12-15 2014-08-26 Suvolta, Inc. Memory circuits and methods of making and designing the same
US8883600B1 (en) 2011-12-22 2014-11-11 Suvolta, Inc. Transistor having reduced junction leakage and methods of forming thereof
US8599623B1 (en) 2011-12-23 2013-12-03 Suvolta, Inc. Circuits and methods for measuring circuit elements in an integrated circuit device
CN102509702A (zh) * 2011-12-28 2012-06-20 上海贝岭股份有限公司 一种用于平面型功率mosfet的外延制作方法
US8970289B1 (en) 2012-01-23 2015-03-03 Suvolta, Inc. Circuits and devices for generating bi-directional body bias voltages, and methods therefor
US8877619B1 (en) 2012-01-23 2014-11-04 Suvolta, Inc. Process for manufacture of integrated circuits with different channel doping transistor architectures and devices therefrom
US9093550B1 (en) 2012-01-31 2015-07-28 Mie Fujitsu Semiconductor Limited Integrated circuits having a plurality of high-K metal gate FETs with various combinations of channel foundation structure and gate stack structure and methods of making same
US9406567B1 (en) 2012-02-28 2016-08-02 Mie Fujitsu Semiconductor Limited Method for fabricating multiple transistor devices on a substrate with varying threshold voltages
US8863064B1 (en) 2012-03-23 2014-10-14 Suvolta, Inc. SRAM cell layout structure and devices therefrom
US9299698B2 (en) 2012-06-27 2016-03-29 Mie Fujitsu Semiconductor Limited Semiconductor structure with multiple transistors having various threshold voltages
US8637955B1 (en) 2012-08-31 2014-01-28 Suvolta, Inc. Semiconductor structure with reduced junction leakage and method of fabrication thereof
US9112057B1 (en) 2012-09-18 2015-08-18 Mie Fujitsu Semiconductor Limited Semiconductor devices with dopant migration suppression and method of fabrication thereof
US9041126B2 (en) 2012-09-21 2015-05-26 Mie Fujitsu Semiconductor Limited Deeply depleted MOS transistors having a screening layer and methods thereof
JP2016500927A (ja) 2012-10-31 2016-01-14 三重富士通セミコンダクター株式会社 低変動トランジスタ・ペリフェラル回路を備えるｄｒａｍ型デバイス、及び関連する方法
US8816754B1 (en) 2012-11-02 2014-08-26 Suvolta, Inc. Body bias circuits and methods
US9093997B1 (en) 2012-11-15 2015-07-28 Mie Fujitsu Semiconductor Limited Slew based process and bias monitors and related methods
US9070477B1 (en) 2012-12-12 2015-06-30 Mie Fujitsu Semiconductor Limited Bit interleaved low voltage static random access memory (SRAM) and related methods
US9112484B1 (en) 2012-12-20 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit process and bias monitors and related methods
US9268885B1 (en) 2013-02-28 2016-02-23 Mie Fujitsu Semiconductor Limited Integrated circuit device methods and models with predicted device metric variations
US8994415B1 (en) 2013-03-01 2015-03-31 Suvolta, Inc. Multiple VDD clock buffer
US8988153B1 (en) 2013-03-09 2015-03-24 Suvolta, Inc. Ring oscillator with NMOS or PMOS variation insensitivity
US9299801B1 (en) 2013-03-14 2016-03-29 Mie Fujitsu Semiconductor Limited Method for fabricating a transistor device with a tuned dopant profile
US9449967B1 (en) 2013-03-15 2016-09-20 Fujitsu Semiconductor Limited Transistor array structure
US9112495B1 (en) 2013-03-15 2015-08-18 Mie Fujitsu Semiconductor Limited Integrated circuit device body bias circuits and methods
US9478571B1 (en) 2013-05-24 2016-10-25 Mie Fujitsu Semiconductor Limited Buried channel deeply depleted channel transistor
US8976575B1 (en) 2013-08-29 2015-03-10 Suvolta, Inc. SRAM performance monitor
US9710006B2 (en) 2014-07-25 2017-07-18 Mie Fujitsu Semiconductor Limited Power up body bias circuits and methods
US9319013B2 (en) 2014-08-19 2016-04-19 Mie Fujitsu Semiconductor Limited Operational amplifier input offset correction with transistor threshold voltage adjustment
WO2017189124A1 (en) * 2016-04-29 2017-11-02 Stc. Unm Wafer level gate modulation enhanced detectors
US10872772B2 (en) 2018-10-31 2020-12-22 Taiwan Semiconductor Manufacturing Company Limited Semiconductor arrangement and method of manufacture

Family Cites Families (131)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US438612A (en) * 1890-10-21 dins-moee
US21855A (en) * 1858-10-19 Umbrella
US526265A (en) * 1894-09-18 de rossetti
US179000A (en) * 1876-06-20 Improvement in devices for multiplying motion
US3617951A (en) 1968-11-21 1971-11-02 Western Microwave Lab Inc Broadband circulator or isolator of the strip line or microstrip type
US3758199A (en) 1971-11-22 1973-09-11 Sperry Rand Corp Piezoelectrically actuated light deflector
US3818451A (en) 1972-03-15 1974-06-18 Motorola Inc Light-emitting and light-receiving logic array
NL7710164A (nl) 1977-09-16 1979-03-20 Philips Nv Werkwijze ter behandeling van een eenkristal- lijn lichaam.
US4174504A (en) 1978-01-25 1979-11-13 United Technologies Corporation Apparatus and method for cavity dumping a Q-switched laser
FR2453423A1 (fr) 1979-04-04 1980-10-31 Quantel Sa Element optique epais a courbure variable
JPS5696834A (en) 1979-12-28 1981-08-05 Mitsubishi Monsanto Chem Co Compound semiconductor epitaxial wafer and manufacture thereof
GB2096785B (en) 1981-04-09 1984-10-10 Standard Telephones Cables Ltd Integrated optic device
US4626878A (en) 1981-12-11 1986-12-02 Sanyo Electric Co., Ltd. Semiconductor optical logical device
US4525871A (en) 1982-02-03 1985-06-25 Massachusetts Institute Of Technology High speed optoelectronic mixer
US5268327A (en) 1984-04-27 1993-12-07 Advanced Energy Fund Limited Partnership Epitaxial compositions
US4695120A (en) 1985-09-26 1987-09-22 The United States Of America As Represented By The Secretary Of The Army Optic-coupled integrated circuits
US5140387A (en) 1985-11-08 1992-08-18 Lockheed Missiles & Space Company, Inc. Semiconductor device in which gate region is precisely aligned with source and drain regions
US4804866A (en) 1986-03-24 1989-02-14 Matsushita Electric Works, Ltd. Solid state relay
US4866489A (en) 1986-07-22 1989-09-12 Matsushita Electric Industrial Co., Ltd. Semiconductor device
US4723321A (en) 1986-11-07 1988-02-02 American Telephone And Telegraph Company, At&T Bell Laboratories Techniques for cross-polarization cancellation in a space diversity radio system
JPH07120835B2 (ja) 1986-12-26 1995-12-20 松下電器産業株式会社 光集積回路
KR880010509A (ko) 1987-02-11 1988-10-10 오레그 이. 앨버 전계효과 트랜지스터
US4801184A (en) 1987-06-15 1989-01-31 Eastman Kodak Company Integrated optical read/write head and apparatus incorporating same
FI81926C (fi) 1987-09-29 1990-12-10 Nokia Oy Ab Foerfarande foer uppbyggning av gaas-filmer pao si- och gaas-substrater.
US5238869A (en) 1988-07-25 1993-08-24 Texas Instruments Incorporated Method of forming an epitaxial layer on a heterointerface
JP2770340B2 (ja) * 1988-09-06 1998-07-02 ソニー株式会社 半導体装置、絶縁ゲート型電界効果トランジスタ及びショットキーゲート型電界効果トランジスタ
US5087829A (en) 1988-12-07 1992-02-11 Hitachi, Ltd. High speed clock distribution system
US5028563A (en) 1989-02-24 1991-07-02 Laser Photonics, Inc. Method for making low tuning rate single mode PbTe/PbEuSeTe buried heterostructure tunable diode lasers and arrays
US5237233A (en) 1989-03-03 1993-08-17 E. F. Johnson Company Optoelectronic active circuit element
GB2230395B (en) 1989-03-15 1992-09-30 Matsushita Electric Works Ltd Semiconductor relay circuit
US5997638A (en) 1990-03-23 1999-12-07 International Business Machines Corporation Localized lattice-mismatch-accomodation dislocation network epitaxy
US5362972A (en) 1990-04-20 1994-11-08 Hitachi, Ltd. Semiconductor device using whiskers
US5188976A (en) 1990-07-13 1993-02-23 Hitachi, Ltd. Manufacturing method of non-volatile semiconductor memory device
US5585288A (en) 1990-07-16 1996-12-17 Raytheon Company Digital MMIC/analog MMIC structures and process
US5248631A (en) 1990-08-24 1993-09-28 Minnesota Mining And Manufacturing Company Doping of iib-via semiconductors during molecular beam epitaxy using neutral free radicals
JP3028840B2 (ja) 1990-09-19 2000-04-04 株式会社日立製作所 バイポーラトランジスタとｍｏｓトランジスタの複合回路、及びそれを用いた半導体集積回路装置
FR2670050B1 (fr) 1990-11-09 1997-03-14 Thomson Csf Detecteur optoelectronique a semiconducteurs.
US5216359A (en) 1991-01-18 1993-06-01 University Of North Carolina Electro-optical method and apparatus for testing integrated circuits
US5387811A (en) 1991-01-25 1995-02-07 Nec Corporation Composite semiconductor device with a particular bipolar structure
US5166761A (en) 1991-04-01 1992-11-24 Midwest Research Institute Tunnel junction multiple wavelength light-emitting diodes
US5523879A (en) 1991-04-26 1996-06-04 Fuji Xerox Co., Ltd. Optical link amplifier and a wavelength multiplex laser oscillator
JPH07187892A (ja) 1991-06-28 1995-07-25 Internatl Business Mach Corp <Ibm> シリコン及びその形成方法
US5148504A (en) 1991-10-16 1992-09-15 At&T Bell Laboratories Optical integrated circuit designed to operate by use of photons
US5404373A (en) 1991-11-08 1995-04-04 University Of New Mexico Electro-optical device
US5446719A (en) 1992-02-05 1995-08-29 Sharp Kabushiki Kaisha Optical information reproducing apparatus
US5488237A (en) * 1992-02-14 1996-01-30 Sumitomo Electric Industries, Ltd. Semiconductor device with delta-doped layer in channel region
US5238877A (en) 1992-04-30 1993-08-24 The United States Of America As Represented By The Secretary Of The Navy Conformal method of fabricating an optical waveguide on a semiconductor substrate
US5585167A (en) 1992-05-18 1996-12-17 Matsushita Electric Industrial Co., Ltd. Thin-film conductor and method of fabricating the same
US5365477A (en) 1992-06-16 1994-11-15 The United States Of America As Represented By The Secretary Of The Navy Dynamic random access memory device
US5262659A (en) 1992-08-12 1993-11-16 United Technologies Corporation Nyquist frequency bandwidth hact memory
JPH0667046A (ja) 1992-08-21 1994-03-11 Sharp Corp 光集積回路
US5642371A (en) 1993-03-12 1997-06-24 Kabushiki Kaisha Toshiba Optical transmission apparatus
US5315128A (en) 1993-04-30 1994-05-24 At&T Bell Laboratories Photodetector with a resonant cavity
US5578162A (en) 1993-06-25 1996-11-26 Lucent Technologies Inc. Integrated composite semiconductor devices and method for manufacture thereof
DE4323821A1 (de) 1993-07-15 1995-01-19 Siemens Ag Pyrodetektorelement mit orientiert aufgewachsener pyroelektrischer Schicht und Verfahren zu seiner Herstellung
US5693140A (en) 1993-07-30 1997-12-02 Lockheed Martin Energy Systems, Inc. Process for growing a film epitaxially upon a MgO surface
US5371621A (en) 1993-08-23 1994-12-06 Unisys Corporation Self-routing multi-stage photonic interconnect
JPH07114746A (ja) 1993-08-25 1995-05-02 Sony Corp 光学装置
JPH0766366A (ja) 1993-08-26 1995-03-10 Hitachi Ltd 半導体積層構造体およびそれを用いた半導体装置
JP3644980B2 (ja) 1993-09-06 2005-05-11 株式会社ルネサステクノロジ 半導体装置の製造方法
EP0721662A1 (en) 1993-09-30 1996-07-17 Kopin Corporation Three-dimensional processor using transferred thin film circuits
JPH07133192A (ja) 1993-11-04 1995-05-23 Sumitomo Electric Ind Ltd 成膜装置および成膜方法
JPH07253519A (ja) 1994-03-16 1995-10-03 Fujitsu Ltd 光接続装置
US6271069B1 (en) * 1994-03-23 2001-08-07 Agere Systems Guardian Corp. Method of making an article comprising an oxide layer on a GaAs-based semiconductor body
US5436181A (en) 1994-04-18 1995-07-25 Texas Instruments Incorporated Method of self aligning an emitter contact in a heterojunction bipolar transistor
US6064783A (en) 1994-05-25 2000-05-16 Congdon; Philip A. Integrated laser and coupled waveguide
US5559368A (en) 1994-08-30 1996-09-24 The Regents Of The University Of California Dynamic threshold voltage mosfet having gate to body connection for ultra-low voltage operation
US5754714A (en) 1994-09-17 1998-05-19 Kabushiki Kaisha Toshiba Semiconductor optical waveguide device, optical control type optical switch, and wavelength conversion device
US5635453A (en) 1994-12-23 1997-06-03 Neocera, Inc. Superconducting thin film system using a garnet substrate
US5772758A (en) 1994-12-29 1998-06-30 California Institute Of Technology Near real-time extraction of deposition and pre-deposition characteristics from rotating substrates and control of a deposition apparatus in near real-time
US5574589A (en) 1995-01-09 1996-11-12 Lucent Technologies Inc. Self-amplified networks
US5563428A (en) 1995-01-30 1996-10-08 Ek; Bruce A. Layered structure of a substrate, a dielectric layer and a single crystal layer
US5574744A (en) 1995-02-03 1996-11-12 Motorola Optical coupler
JP3557011B2 (ja) 1995-03-30 2004-08-25 株式会社東芝 半導体発光素子、及びその製造方法
US5919522A (en) 1995-03-31 1999-07-06 Advanced Technology Materials, Inc. Growth of BaSrTiO3 using polyamine-based precursors
US6140746A (en) 1995-04-03 2000-10-31 Seiko Epson Corporation Piezoelectric thin film, method for producing the same, and ink jet recording head using the thin film
US5528209A (en) 1995-04-27 1996-06-18 Hughes Aircraft Company Monolithic microwave integrated circuit and method
US5753934A (en) 1995-08-04 1998-05-19 Tok Corporation Multilayer thin film, substrate for electronic device, electronic device, and preparation of multilayer oxide thin film
US5760740A (en) 1995-08-08 1998-06-02 Lucent Technologies, Inc. Apparatus and method for electronic polarization correction
JP3137880B2 (ja) 1995-08-25 2001-02-26 ティーディーケイ株式会社 強誘電体薄膜、電子デバイスおよび強誘電体薄膜の製造方法
US5905571A (en) 1995-08-30 1999-05-18 Sandia Corporation Optical apparatus for forming correlation spectrometers and optical processors
DE19536753C1 (de) * 1995-10-02 1997-02-20 El Mos Elektronik In Mos Techn MOS-Transistor mit hoher Ausgangsspannungsfestigkeit
US5787175A (en) 1995-10-23 1998-07-28 Novell, Inc. Method and apparatus for collaborative document control
JP3435966B2 (ja) 1996-03-13 2003-08-11 株式会社日立製作所 強誘電体素子とその製造方法
JP3258899B2 (ja) 1996-03-19 2002-02-18 シャープ株式会社 強誘電体薄膜素子、それを用いた半導体装置、及び強誘電体薄膜素子の製造方法
US5729566A (en) 1996-06-07 1998-03-17 Picolight Incorporated Light emitting device having an electrical contact through a layer containing oxidized material
JP3082671B2 (ja) 1996-06-26 2000-08-28 日本電気株式会社 トランジスタ素子及びその製造方法
US5985404A (en) 1996-08-28 1999-11-16 Tdk Corporation Recording medium, method of making, and information processing apparatus
JP4114709B2 (ja) 1996-09-05 2008-07-09 株式会社神戸製鋼所 ダイヤモンド膜の形成方法
US5838053A (en) 1996-09-19 1998-11-17 Raytheon Ti Systems, Inc. Method of forming a cadmium telluride/silicon structure
DE69739387D1 (de) * 1996-10-29 2009-06-10 Panasonic Corp Tintenstrahlaufzeichnungsgerät und Verfahren zu seiner Herstellung
US5719417A (en) 1996-11-27 1998-02-17 Advanced Technology Materials, Inc. Ferroelectric integrated circuit structure
JPH10223901A (ja) * 1996-12-04 1998-08-21 Sony Corp 電界効果型トランジスタおよびその製造方法
KR100571071B1 (ko) 1996-12-04 2006-06-21 소니 가부시끼 가이샤 전계효과트랜지스터및그제조방법
GB2321114B (en) * 1997-01-10 2001-02-21 Lasor Ltd An optical modulator
JP3414227B2 (ja) 1997-01-24 2003-06-09 セイコーエプソン株式会社 インクジェット式記録ヘッド
US5937115A (en) 1997-02-12 1999-08-10 Foster-Miller, Inc. Switchable optical components/structures and methods for the fabrication thereof
JP3734586B2 (ja) 1997-03-05 2006-01-11 富士通株式会社 半導体装置及びその製造方法
US6022671A (en) 1997-03-11 2000-02-08 Lightwave Microsystems Corporation Method of making optical interconnects with hybrid construction
JPH10265948A (ja) 1997-03-25 1998-10-06 Rohm Co Ltd 半導体装置用基板およびその製法
CN1131548C (zh) 1997-04-04 2003-12-17 松下电器产业株式会社 半导体装置
US5906951A (en) 1997-04-30 1999-05-25 International Business Machines Corporation Strained Si/SiGe layers on insulator
US5998781A (en) 1997-04-30 1999-12-07 Sandia Corporation Apparatus for millimeter-wave signal generation
US5831960A (en) 1997-07-17 1998-11-03 Motorola, Inc. Integrated vertical cavity surface emitting laser pair for high density data storage and method of fabrication
US6020243A (en) * 1997-07-24 2000-02-01 Texas Instruments Incorporated Zirconium and/or hafnium silicon-oxynitride gate dielectric
US6204525B1 (en) 1997-09-22 2001-03-20 Murata Manufacturing Co., Ltd. Ferroelectric thin film device and method of producing the same
US6233435B1 (en) 1997-10-14 2001-05-15 Telecommunications Equipment Corporation Multi-function interactive communications system with circularly/elliptically polarized signal transmission and reception
US6181920B1 (en) 1997-10-20 2001-01-30 Ericsson Inc. Transmitter that selectively polarizes a radio wave
US5987196A (en) 1997-11-06 1999-11-16 Micron Technology, Inc. Semiconductor structure having an optical signal path in a substrate and method for forming the same
US6140696A (en) * 1998-01-27 2000-10-31 Micron Technology, Inc. Vertically mountable semiconductor device and methods
US5945718A (en) * 1998-02-12 1999-08-31 Motorola Inc. Self-aligned metal-oxide-compound semiconductor device and method of fabrication
US6110840A (en) 1998-02-17 2000-08-29 Motorola, Inc. Method of passivating the surface of a Si substrate
US6051874A (en) 1998-04-01 2000-04-18 Citizen Watch Co., Ltd. Diode formed in a surface silicon layer on an SOI substrate
JP2000022128A (ja) * 1998-07-06 2000-01-21 Murata Mfg Co Ltd 半導体発光素子、および光電子集積回路素子
US6392253B1 (en) * 1998-08-10 2002-05-21 Arjun J. Saxena Semiconductor device with single crystal films grown on arrayed nucleation sites on amorphous and/or non-single crystal surfaces
US6159781A (en) * 1998-10-01 2000-12-12 Chartered Semiconductor Manufacturing, Ltd. Way to fabricate the self-aligned T-shape gate to reduce gate resistivity
JP3408762B2 (ja) * 1998-12-03 2003-05-19 シャープ株式会社 Ｓｏｉ構造の半導体装置及びその製造方法
JP2000278085A (ja) * 1999-03-24 2000-10-06 Yamaha Corp 弾性表面波素子
JP2001138529A (ja) * 1999-03-25 2001-05-22 Seiko Epson Corp 圧電体の製造方法
US6862528B2 (en) * 1999-04-27 2005-03-01 Usengineering Solutions Corporation Monitoring system and process for structural instabilities due to environmental processes
US6326667B1 (en) * 1999-09-09 2001-12-04 Kabushiki Kaisha Toshiba Semiconductor devices and methods for producing semiconductor devices
US6362558B1 (en) * 1999-12-24 2002-03-26 Kansai Research Institute Piezoelectric element, process for producing the same and ink jet recording head
US6445724B2 (en) * 2000-02-23 2002-09-03 Sarnoff Corporation Master oscillator vertical emission laser
US6415140B1 (en) * 2000-04-28 2002-07-02 Bae Systems Aerospace Inc. Null elimination in a space diversity antenna system
US6501121B1 (en) * 2000-11-15 2002-12-31 Motorola, Inc. Semiconductor structure
KR100360413B1 (ko) * 2000-12-19 2002-11-13 삼성전자 주식회사 2단계 열처리에 의한 반도체 메모리 소자의 커패시터 제조방법
US6524651B2 (en) * 2001-01-26 2003-02-25 Battelle Memorial Institute Oxidized film structure and method of making epitaxial metal oxide structure
JP2002324813A (ja) * 2001-02-21 2002-11-08 Nippon Telegr & Teleph Corp <Ntt> ヘテロ構造電界効果トランジスタ
JP2002299603A (ja) * 2001-03-29 2002-10-11 Nec Corp 半導体装置
US6498358B1 (en) * 2001-07-20 2002-12-24 Motorola, Inc. Structure and method for fabricating an electro-optic system having an electrochromic diffraction grating
JP3673231B2 (ja) * 2002-03-07 2005-07-20 三菱電機株式会社 絶縁ゲート型半導体装置及びゲート配線構造の製造方法

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