TWI299575B - Nonvolatile memory device using semiconductor nanocrystals and method of forming same - Google Patents

Nonvolatile memory device using semiconductor nanocrystals and method of forming same Download PDF

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TWI299575B
TWI299575B TW093116874A TW93116874A TWI299575B TW I299575 B TWI299575 B TW I299575B TW 093116874 A TW093116874 A TW 093116874A TW 93116874 A TW93116874 A TW 93116874A TW I299575 B TWI299575 B TW I299575B
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floating gate
particles
effect transistor
nanoparticles
nano
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TW093116874A
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TW200518349A (en
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Charles T Black
Kathryn Wilder Guarini
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Ibm
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Description

1299575 九、發明說明： 【發明所屬之技術領域】 首本發明大體上侧於-觀㈣t置，尤其_—種使用 半導體晶體之非揮發性記憶體裝置及其製造方法。 【先前技術】 非揮發性記憶體在充斥科技的今日世界裡是無所不在 的。用來儲存資訊賊普遍裝置種類就是快閃記憶體。 远輯系統中除了需要用到積體非揮發性記憶體之外，作為 獨立儲存裝置的快閃記賴也有—魏大㈤時快速成長中) 的市場，如手機與數位減較惠於非揮發性記憶體卡。 有關於這種類型儲存襄置之未來市場，已有麵預測（參 見 P. P_, R· Bez，P 〇livi〇 與 E Zan〇ni，7肅户现幻 1248(1997)) 〇 快閃記憶體是根據場效電晶體(FET，field effect transi_ 之U心其閾—(ντ)在第—值與第二值之間可逆互換。 囷（）之侧剖面圖中所示，一種習用快閃記憶體裝置
4 旧 M/04055TW 1299575 100 ’包含一基板10卜形成於基板ιοί内之源極102與汲極 103 ’其間形成-通道104、形成於基板1〇1上之一規劃氧化 層105、形成於規劃氧化層1〇5上之一浮置閘1〇6、形成於浮 置閘106上之-控制氧化層1〇7、及形成於控制氧化層1〇7上 之一控制閘108。 協助這種多重狀態運作的快閃記憶體裝置1〇〇之主要部 分是在電晶體閘疊中的一導電浮置閘1〇6(見圖1(a))，導電浮 置閘106透過上面與下面的介電層（即1〇7、1〇5)而與周遭(控 制閘108，以及通道104/源極1〇2/沒極1〇3區)耦合。 裝置100藉由將電荷引入浮置閘1〇6(通過規劃氧化層1〇5) 而受規劃，將電荷自浮置閘106排除以消除規劃。裝置1〇〇 係藉一層夠厚的控制氧化層107，使浮置閘1〇6與源極1〇2/ 汲極103/通道1〇4以及控制閘108去耦合，使其具非揮發性。 跟其他半導體科技一樣，快閃記憶體不斷地調整使密度持 續增加。同時，在裝置速度、電力消耗，與耐久性(例如記憶 體壞掉之前可以被讀取/消除的次數)的改進都帶來明顯的好 處。
4IBM/04055TW 1299575 最後-點，有些_記憶體裝由每—個記憶體單元儲 存多位兀，以改善效能(最有名的就是英特爾# st論恤也观 科技目别母單元可儲存2位元，而且已經宣布未來計晝增加 每單元之位元數）。辆之所以可以制，是因為用不同量的 包荷把浮置閘106程式化，以達成在相同裝置中多重潛在閾電 壓(VT)轉變(shifts)。 要達成這些密度與效能的優點係與縮放(scaling)記憶體 FET有關，然這已經變得越來越困難。例如，為了改善封裝密 度與速度將裝置寬度縮小，卻增加來自汲極1〇3與浮置閘1〇6 之間電谷耦合的〉及極打開效應(drain仙仏⑽effect)。 此外，為了降低寫入/消除電壓(因而降低能源），而把規劃 氧化層105的厚度變薄’也造成了保留時間(retenti〇ntimes)與 可靠性之降低。 圖1(b)提出奈米晶體記憶體裝置作為改善快閃記憶體裝 置之縮放的方法，同時也作為達到健全多位元操作的一種可能 的手段或裝置(例如見 H. Hanafl，Dev. 43 4IBM/04055TW 7 1299575 1553 (1996) ; S· Tiwari，F· Rana，Η· Hanafi，A. Hartstein，E. Crabble，C· Chan,為咖· P/明· 68 1377 (1996);與 S· Tiwari， R Rana? K. Chan5 H. Hanafi, W. Chan, D. Buchanan, IEDM 521 (1995)) 〇 圖1(b)中顯示的傳統奈米晶體記憶體裝置150，結構跟圖 1(a)有點類似，只是原來的浮置閘1〇6現已被奈米晶體156取 代。 奈米晶體§己憶體裝置的一個基本概念，就是把一個連續的 導電浮置閘106分解成許多獨立的導電材料之小位元，這樣可 以幫助克服進一步縮放的一些障礙。 奈米晶體浮置閘156已把電容耦合降低到源極151/汲極 區152，這樣汲極打開效應就比較小。此外，奈米晶體浮置問 106應可以使裝置較不易受到應力誘引漏電流(stress_indueed leakage current)的影響。也就是說，有一個獨立的奈米晶體與 通道154發生短路，其他的奈米晶體並不會受到影響。一個桿 準浮置閘裝置中(例如裝置100)，通道104的任何短路都是很 嚴重的，因為浮置閘106就無法繼續維持電荷。
4IBM/04055TW A299575 '孕置氧⑽厚朗傳錄囉置味，奈米晶艘 中::考數字-表雨置⑽ 漏電繼膨兄的電荷 在快閃記憶體桊w + 應力誘引漏電流會危及裝 "，攻樣的漏電會使整個浮置閘電荷都 破耗m，¥致記憶體之喪失(例如， 置一樣）。 搞1W、、只曰曰體裝置中’因為這種漏電機制只有那些很接近續 不合極153的奈米晶體會喊失電荷，那齡得較遠制 曰(^錢裝置中心者）。這種論點是假設浮置閘156中奈却 之間沒有電的傳導(即透過奈米晶體密度來控制的㈣ 下）〇 居^曰曰體浮置閘裝置lso改良的保留特徵使得規劃氧化 二可以縮小成較薄，更有益處。較薄的氧化物⑸就可以 幸乂低甩【下’使用直接量子機械穿隧(quantum mechanical
tunnelmg)^tfl^^^^N^^ Fowler-Nordheimi##^t^l〇 4IBM/04055TW 1299575 除了明顯的低電壓操作以降低能源優點外，也有證據顯示 直接穿隧寫入/消除機制對規劃氧化層155的應力會較小，如 此一來，可以使裝置之回收使用性提高。模型也顯示較薄之氧 化物155可以更快速地被程式化(例如，見μ. She, Y.C. King， T.J. King, C. Hu? IEEE Device Research Conference, 139 (200”）。 奈米晶體記憶體150更令人著迷的特色之一就是具有把 數個離散的電子把浮置閘156程式化，然後形成多個離散的、 定義良好之裝置閾電壓(VT)轉變的潛能。這種理論在於，增加 一個單一電荷到一個夠小的奈米晶體所需之靜電能量可能變 得很重要。靜電充電能量計算如下： 其中e為電子電荷，CE是奈米晶體與其周遭之電容。Tiwari 等人估算出不同直徑奈米晶體的充電能量(在這種計算中，是 作又疋奈米晶體為圓的)(例如，&S Tiwari，J.A.Wahl，H.Silva，F.
Rana，J· J· Welser，却;7/·尸/^. a 71 403 (2000))。計算結果列於 表1。浮置閘中所儲存的電荷轉變成裝置νΊΓ，數量為：
4 旧 M/04055TW I299575 粒之一直徑平均值的約15%。 更進一步地，在本發明此示範型態中，自組合可以涉及一 區段共聚物薄膜σ例如，區段共聚物可包含一雙區段共聚物， 該雙區段共聚物包含一分子量在約5,〇〇〇 kg/m〇l至250,000 kg/mol的一範圍之間。 本發明的第三個示範型態為一種形成一場效電晶體之一 浮置閘的方法’包含使用一自組合材料形成複數個離散的奈米 顆粒，定義該奈米顆粒的尺寸以及分佈。 本發明的弟四個示範型態為一種製作一均勻性奈米顆粒 陣列的方法，包含在一介電層中複製一聚合物模板的一尺寸， 以形成-多孔介膜，共形地沈積—材料覆蓋該多孔介電薄 膜，以及異向性及選擇性地蝕刻該沈積的材料。
本發明的第五個示範型態為一種製作一均勻性奈米顆粒 陣列的方法，包含在-材料薄膜上自組合形成—雙區段共聚物 潯膜，自該區段共聚物薄膜建立一聚合物點狀陣列(购職 dot a卿)’個聚合無狀陣狀—聚合雜物料—钱刻罩 幕用於材料薄膜的奈米顆粒反應離子钱刻（R压）C 本發明的第六個示範型態為一㈣.均勻性奈米顆粒
4IBM/04055TW 16 1299575 陣列的方法，包含於石夕上自組合形成_雙區段共聚物薄膜，建 立夕孔聚合薄膜，方向性地沈積一第一材料覆蓋該多孔聚合 _膜’並溶解該聚合物以料⑽,覆蓋在多孔聚合物的 第一材料之至少一個區域。 本發明的第七個示範型態為—種製作—均勻性奈米顆粒 陣列的方法’包含在覆於-可氧化材料_之—第—介電層 上’自組合形成-频段絲物_，建立—多孔聚合物薄 膜嘴一圖案移轉到該第一介電層，_亥圖案到該材料中， 熱氧，該材料直到六方排列孔洞之間的—最窄材料區閉合為 止，藉此留下一奈米材料顆粒陣列。 本發_第人個示範型態為—種製作—均勻性奈米馳 ^列的方法，包含在-覆於歡—第—介騎上自組合形成雙 2共聚物賴’建立—多孔聚合物_，移轉—職至該第 :電層太自孔_選擇性地成錢砂，落到—錄板，以 建立一矽奈米顆粒陣列。 法0 卜本毛明提供-種製造_奈米晶體記憶體裝置的方 猎由本發明·特色之簡 一夺乎圮惰栌壯w注 I、貞之㈣-就可以形成 不木。己體衣置，使用自組合製 ^ r 才了加以疋義奈米晶體。 良好地 ’不未晶體記憶體裝置(及其形成的方法)可以
4IBM/04055TW 17 1299575 段共聚物的-自組合製程’包含示範性的聚苯乙烯(ps)與聚甲 基丙烯酸曱酯(PMMA)。 首先，PS-PMMA雙區段共聚物較佳係在一溶劑中先稀 釋，如甲苯或類似的，然後以薄膜旋鑄法於一樣品(例如，一 硬罩氧化層，如通常都是石夕上面熱成長的二氧化石夕，或類似物) 上形成一薄膜，此薄膜較佳厚度在大約幾奈米至幾百奈米之 間。 接著加熱此樣品(溫度在14〇°C至200°C之間，加熱數小 時），藉此促進示範聚合物之微相分離陣列(如圖2⑻所示範， 在薄膜中形成一種有次序的六方最密堆積陣列（hcp))。 要注思的疋，溫度讓這兩種聚合物可以彼此相互隔離，而 且給他們移動性。因此，溫度與時間是很重要的，但可能依聚 合物系統之特定厚度、濃度等而有所不同。 例如，分子重量67 kg/mol、質量比例PS : PMMA為7〇:3〇 之PS-PMMA共聚合物，其所形成的自組合薄膜(〜nm厚) 是由直徑為20-nm之PMMA圓柱組成，（例如，圖2(a)所示黑 圈，排列成六角形晶格（中心到中心間距4〇nm)，此六角形晶 格係彼設在一 PS基質中）。同樣地，溫度讓此一材料可以相分 離(phase-separate)以顯示有次序圖案。在被加熱之前，該薄膜 是這兩種尚未物理分離的聚合物之混合體。
4IBM/04055TW 23 1299575 基質。 圖2(b)顯示該PS-PMMA薄膜中的孔洞直經之長條圖。在 平均直徑20-nm兩旁的狹窄分佈(例如1〇%)，顯示這些薄膜是 非常均勻的。 自組合薄膜裡尺寸的特徵可以用不同的共聚合物分子量加 以調整，通常孔洞直徑在大約在1〇11111到100 —範圍内。 圖2⑻為由上而下掃瞄電子顯微照相(SEM)之影像，說明 在矽上以雙區段共聚物自組合所形成一多孔聚苯乙烯薄(PS) 薄膜。六角形排列的黑圈是PS薄膜裡面貫穿到基板的圓柱型 孔洞，其中PMMA已被選擇性移除。圖2(b)為一孔洞直徑之 長條圖，顯示分子重量為67 kg/mol之PS-PMMA以約20 nm 為中心，在左右約10%的窄分佈；由雙區段共聚物自組合所 形成的薄形孔洞聚合物模板與標準半導體製程是可以相提並 論的(例如，不會造成污染，而且可以採用與一聚合物光阻相 似的方式，被利用於反應離子蝕刻(RIE)之移轉），也可以被用 做一罩幕’用來轉移奈米尺度圖案到一底層薄膜或基板裡面 (如以下之說明）。（這樣做通常是需要的，因為該聚合物模板既 無熱穩定，亦無機械堅固性）。 上述步驟會被用來建立一本發明示範之重要裝置，說明如
下。 4IBM/04055TW 25 1299575 本發明示範方法 圖3(a)-(g)描繪根據雙區段共聚物自組合，以形成石夕奈米晶 體陣列之方法300的示意圖（見圖3(h)顯示該製程之流程）。也 就是，圖3(a)-圖3(g)圖示如何從一自組合PS-PMMA薄膜形 成一密集陣列之奈米晶體(如上述及圖2(&)之形成的示範說 明）。 首先，在一熱氧化矽晶圓301上(例如形成二氧化矽或3〇2 類似物)製備妥PS 303與PMMA 304的薄膜，如圖3(a)(亦即 圖3(h)中的步驟310)。 接著，將PMMA 304從孔洞中移除(如圖3(b)以及步驟320 所顯示），然後使用一反應性離子蝕刻製程(RIE)將圖案(例如 PS 3〇3)轉到氧化薄膜(如_ 3(c)或步驟33〇所示一方向性餘 刻’使用CHF3與氬或類似物）。 接著移除剩下的?κ合物(pS)3〇3(如圖3(d)與步驟所 示），留下-从紐_ 3G2，其尺稍f在纽聚合薄膜 中一樣。 參考步驟350與如圖3(e)，共形地沈積一材料(例如，石夕， 如多晶碎或非砂’或有可能形成奈米晶體的其他材料，像是 錄或石夕錯或金屬；在這個示範製程中假設用-非晶石夕層），以
4IBM/04055TW 26 1299575 形成薄臈306沉積在該多孔氧化物302上。此共形沈積薄膜 3〇6以連續的為較佳應該完全共形覆蓋表面較佳。因為· 這些洞孔必須被填滿，所以薄膜；306較佳係有一厚度大於大約 · 孔洞直徑的一半。 … 也就是說，為了可以填滿或「夾取」這些孔洞，薄膜3〇6 •‘ 應該確實是-共形的沈積，不管表面是垂直的或是平行的表 面’要以同樣厚度覆蓋每個表面，所沈積的厚度應該至少是孔❿ /同兩如任一^覓度的一半，才可以夾在一起。所以，所沈積的 厚度應該至少是孔洞直徑的一半。 由於-方向性侧接著就要執行，因此要注意，因為圖案 的尺寸，在孔洞裡面沈積矽層(例如非晶矽層）的垂直厚度，比 在该氧化物頂端上的大多了。本發明利用這種較大的厚度，把 材料留在這些孔洞裡’以成為石夕奈米晶體。接著，如步驟 360以及如圖3(f)所*，使用異向性的方向性侧舰製程，φ 蝕刻共形沈積矽306，並把矽306留在這些孔洞裡的。因此， 矽的方向蝕刻被執行並停止於石夕氧化物3〇2 (較佳係選擇性的 抵抗矽氧化物’但不是傳統方法的停止蝕刻步驟）。如前所述， 這並不是自然的停止，有可能繼續姓刻把孔洞裡面所有的石夕移 除。但是，這樣是不好的。 - 因此，必須要小心地蝕刻出一足夠數量的矽材料，使矽保 —
4 旧 M/04055TW 27 1299575 接著是步驟460，沈積一共形的石夕條(非晶石夕或多晶石夕之 類似物，與上述圖3(e)的步驟3s〇 一樣），如圖Μ骑示。 · 如步驟470與圖4(g)所示，以異向性石夕RIE定義奈米晶體. 407，亚使其彼此隔離，達到底下的氧化層術a時就· 停止。 · 在這個階段，奈米晶體之間的熱氧化物4〇2A可以視需 要使用選擇性濕化學品或钱刻，來力口以變薄或移除。_ 接下來步驟480與圖4(h)，沈積一氧化層4〇8於奈米晶體 (上面）。層408將會作為本裝置的控制氧化層（通常厚度為大 約4至l〇nm範圍内）。 控制氧化層較佳是藉由沈積低溫氧化物所形成，如低壓 CVD(LPCVD)氧化物，（或電漿—增強CVD(pECVD)，或快速熱 CVD (RTCVD)、或原子層沈積(ALD))。另外一種選擇，控制 氧化層可以藉由矽奈米晶體的熱氧化作用形成（較佳溫度在 鲁 700度至11〇〇度之間）。接下來沈積閘極材4〇9，較佳是由有 適當厚度的材料如多晶矽或金屬所形成。 奈米晶體可以視需要地，以高溫回火結晶成形。要注意的 疋，通常本發明是沈積一非晶矽層然後被蝕刻，所以通常材料 都是非晶系，不一定需要結晶狀的。不過，傳統裝置製造方法 大都使用夠高的溫度，使顆粒結晶。因此，用本發明方法，溫 _
4 旧 M/04055TW 32 1299575 圖2(b)為一孔洞直徑之長條圖，顯示分子重量為67 kg/mol之
P PS-PMMA以約20 nm為中心，在左右約10%的窄分佈； 圖3(aMh)描繪根據雙區段共聚物自組合成矽奈米晶體陣列之 , 示意圖，更明確地說明如下·· 圖3(a)說明步驟310，在一熱氧化矽基板上組合PS-PMMA雙 區段共聚物； 圖3(b)說明步驟320，移除PMMA區段，留下一多孔PS模 · 板； 圖3(c)說明步驟330，使用反應離子蝕刻(rie)之把PS圖案移 轉到氧化膜； 圖3(d)說明步驟340，剝離剩下之聚合物，留下一多孔氧化薄 膜； 圖3(e)說明步驟350，共形地沈積一材料(例如矽）； 圖3(f)說明步驟360，異向性地姓刻石夕；以及 馨 圖3(g)說明步驟370，剝離氧化物，留下在矽上面該矽奈米晶 體陣列；以及 圖3(h)說明®I 3(a)至圖3(g)所顯示的方法3〇〇的流程圖；以及 圖4⑻-圖4(j)顯示形成一奈米晶體記憶體裝置的製造流程· 400，更明確地說明如下： 圖4⑻說明在一熱氧化石夕基板上組成PS-PMMS雙區段共聚物 .
4IBM/04055TW 35 1299575 之步驟； 圖4(b)移除PMMA區段，留下多孔PS模板之步驟； 圖4(c)說明步驟43〇，使用反應離子蝕刻识正)移轉ps圖案至 氧化膜； 圖4(d)說明剝離剩下之聚合物，留下-多孔氧化膜之步驟； 圖4(e)”兒明共形地沈積一材料(例如石夕)之步驟； 圖4(f)說明異向性钱刻石夕之步驟，· 圖4(g)說明剝離氧化物， 驟； 圖4(h)說明剝離氧化物，
留下在矽上面之矽奈米晶體陣列之步 留下在石夕上面之梦奈米晶體陣列之步 圖4(〇說明剝離氧化物，留下在矽上 面之發奈米晶體陣列之步 圖4〇)說明圖4⑻至圖邮)所顯 方去400的流程 【主要元件符號說明】 圖
100傳統快閃記憶體裝置 101基板 102源極區 103汲極區
4 旧 M/04055TW 36 1299575 104通道 105規劃氧化物 106浮置閘 107控制氧化層 108控制閘 150傳統奈米晶體記憶體裝置 152源極 153汲極 154通道 155規劃氧化層 156奈米晶體浮置閘 157控制氧化層 158控制閘 300開始 310晶圓上製備薄膜 320移除孔洞中的材料 330移轉圖案到薄膜 340移除剩下的聚合物 350沈積薄膜 360蝕刻薄膜
4IBM/04055TW 1299575 370選擇性地移除氧化物 302二氧化矽
303 PS 304 PMMA 306矽 400開始 410提供基板 420熱成長氧化物 430雙區段共聚物製程在層上執行，且移轉圖案 440剝離聚合物及清洗晶圓 450熱成長氧化層 460沈積矽 470定義及隔離奈米晶體 480沈積氧化層 490裝置完成 401多晶石夕 402二氧化矽 402A多孔二氧化矽
403 PS 404孔洞
4IBM/04055TW 1299575 405規劃氧化層 406非晶矽 407矽奈米晶體 408控制氧化層 409閘極
4IBM/04055TW

Claims (1)

1299575 产12月曰修(更)正 號：93116874 來年12月29日修正 十、申請專利範圍： 一種浮置閘(floating gate)，係供使用於一場效電晶體，此 浮置閘包含·· 複數個離散的奈米顆粒，其中該等奈米顆粒的尺寸、間隔、 及密度中至少有一，係藉由一自組合材料(sdf：assembled materials)，將其至少一模板化(templated)，並加以定義 (defined)； 其中该專奈米顆粒有一實質上(substantiaiiy)均勻之直徑，該 等奈米顆粒直徑包含有約2奈米至約30奈米之間，尺寸分 佈不大於該奈米顆粒平均直徑的約15% ;且 其中該等奈米顆粒包含實質上均勻的顆粒中心對中心間隔 (Center_to center spacing between said nanoparticles )。 2·如申請專利範圍第1項中所述之浮置閘，其中該等奈米顆 粒間隔有一變異不大於2〇%。 3·如申請專利範圍第2項中所述之浮置閘，其中該等奈米顆 粒間隔有一變異不大於15%。 4.如申請專利範圍第3項中所述之浮置閘，其中該等奈米顆 4 旧 M04055TW-替換頁 _122906.doc YOR9-2003-0146(JHW) 40 1299575 案號：93116874 95年12月29日修正 粒間隔有一變異不大於1〇% 5.如申請補麵第h ’射相鄰奈米顆 …、u至中叫隔之變異係控制於1G%至約應範 圍之間。 6. 一種用於一場效電晶體之浮置閘，包含： 複數個離散的奈米顆粒， 其中该奈米顆粒之直徑係包含有約2奈米至約％奈米之 間，其尺寸分佈不大於該等奈米顆粒之平均直徑的約15 % ;以及 其中該奈米顆粒密度大於1〇i〇/cm2。 7· —種場效電晶體，包含： 一源極區及一汲極區，形成在一半導體材料中； 一通道區，沈積於該源極區與汲極區之間； 一電絕緣材料之絕緣層，位於該通道區上面； 一電傳導材料之浮置閘層，位於該絕緣層上面； 一電絕緣材料層，位於該浮置閘層上面；以及 一閘電極覆蓋該絕緣材料層， 4IBM04055TW-替換頁-122906.doc 41 YOR9-2003-0146(JHW) 1299575 案號：93116874 95年12月29日修正 其中該浮置閘層包含複數個離散的奈米顆粒，該奈米顆粒 的尺寸、間隔、及密度中至少有一，係藉由一自組合材料， 將其模板化(templated)，並加以定義； 其中該等奈米顆粒有一實質上(substantially)均勻之直徑，該 荨奈米顆粒直控包含有約2奈米至約30奈米之間，尺寸分 佈不大於該奈米顆粒平均直徑的約15% ;且 其中該等奈米顆粒包含實質上均勻的顆粒中心對中心間 隔0 8·如申請專利範圍第7項所述之場效電晶體，其中該自組人 涉及一區段共聚物(block copolymer)薄膜。 9·如申請專利範圍第8項所述之場效電晶體，其中該區段共 聚物包含一雙區段共聚物，該雙區段共聚物包含聚苯乙烯 (PS)以及聚(曱基丙烯酸甲酯)(pMMA)。 10·如申料利範圍第7酬述之場效電晶體，射該等奈米 顆粒包含石夕、鍺、及石夕-鍺中之至少一種材料。 11.如申請專利範圍第7項所述之場效電晶體，其中該奈米顆 4IBM04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 1299575 案號：93116874 95年12月29日修正 粒密度大於l〇1G/cm2。 12·如申請專利範圍第7項所述之場效電晶體，其中該等奈米 顆粒係安排於一最密堆積(close-packed)之二維六方晶格 (two_dimensional hexagonal lattice)中。 13·如申請專利範圍第12項所述之場效電晶體，其中該六方晶 格包括約為平均奈米顆粒直徑的1至2倍間之平均奈米顆 粒間距(average inter-nanoparticle distance)，而該奈米顆粒 間距的標準偏差實質上不大於該平均間距的20%。 14·如申請專利範圍第7項所述之場效電晶體，其中該浮置閘 中的忒專奈米顆粒包含第一不同尺寸(出组沉^ size)與第二 不同尺寸，其中每一尺寸之直徑標準偏差係小於該奈米顆 粒之一平均直徑的約15%。 15.如申請專利範®第7項所述之場效電晶體，其巾該區段共 聚物包含一雙區段共聚物，該雙區段共聚物包含至少一種 下列化合物： 聚苯乙烯(ps)、聚（曱基丙稀酸甲醋)(PMMA)、聚丁二稀- 4 旧 M04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 43 1299575 案號：93116874 95年12月29日修正 聚丁基甲基丙烯酸酯、聚丁二烯-聚曱基丙烯酸丁酯 、聚丁二烯-聚二曱基矽氧烷、 聚丁二烯-聚曱基丙烯酸曱酯、 聚丁二烯-聚乙烯吡啶、 聚異戊二烯-聚甲基丙烯酸甲酯、 聚異戊二烯-聚乙烯吼啶、 _ 聚丙烯酸丁酯-聚甲基丙烯酸曱酯、 聚丙烯酸丁酯·聚乙烯吡啶、 聚丙烯酸己酯-聚乙烯吡啶、 聚異丁烯-聚甲基丙烯酸丁酯、 聚異丁烯-聚二曱氧基矽氧烷、 聚異丁烯-聚曱基丙烯酸曱酯、 聚異丁稀-聚乙稀11比咬、 • 聚曱基丙烯酸丁酯聚丙烯酸丁酯、 聚甲基丙烯酸丁酯-聚乙烯吡啶、 聚乙烯-聚曱基丙烯酸曱酯、 聚甲基丙烯酸曱酯-聚丙烯酸丁酯、 聚曱基丙稀酸甲酯-聚曱基丙烯酸丁酯、 聚苯乙烯-聚丁二烯、 聚苯乙烯-聚丙烯酸丁酯、 4 旧 M04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 44 1299575 案號：93116874 95年12月29日修正 聚苯乙烯-聚甲基丙烯酸丁酯、 聚苯乙烯-聚丁苯乙烯、 聚苯乙烯-聚二甲氧基矽氧烷、 聚苯乙烯-聚異戊二烯、 聚苯乙烯-聚曱基丙烯酸甲酯、 聚本乙聚乙細^比ϋ定、 聚乙烯-聚乙烯吡啶、 聚乙烯吡啶-聚甲基丙烯酸曱酯、 聚氧化乙烯-聚異戊二烯、 聚氧化乙烯-聚丁二烯、 聚氧化乙烯-聚苯乙烯、以及 聚氧化乙烯-聚曱基丙烯酸甲酯。 16.如申請專利範圍第7項所述之場效電晶體，其中該奈米顆 粒被安排在一六方晶格(hexagonal lattic)或一立方晶格 (cubic lattice)中。 17.如申請專利範圍第8項所述之場效電晶體，其中該區段共 聚物包含一雙區段共聚物，該雙區段共聚物包含一分子量 在約 5,000kg/mol 至 250，(K)0kg/mol 的範圍之間。 4旧1\/104055丁\/7-替換頁-122906.〇1〇〇 YOR9-2003-0146(JHW) 45 1299575 案號：93116874 95年12月29日修正 18·如申請專利範圍第8項所述之場效電晶體，其中該區段共 聚物薄膜之分子量係經選擇，以決定該等奈米顆粒之尺寸。 19.如申請專利範圍第8項所述之場效電晶體，其中該區段共 聚物薄膜之分子量係經選擇，以決定該等奈米顆粒在該自 組合後的直徑，以及該等奈米顆粒中二相鄰奈米顆粒的間 隔0 20· —種形成一場效電晶體之一浮置閘的方法，包含： 使用一自組合材料以形成複數個離散的奈米顆粒，該等齐 米顆粒的尺寸、間隔、及密度中至少有一，係藉由此自組 合材料，將其模板化，並加以定義(defined);
其中該等奈米顆粒有一實質上均勻之直徑，該等太 、， 直徑在約2奈米至約30奈米之間，尺寸八 ';立 顆粒平均紐的約15% ; JL 奈米 其中該等奈米顆粒包含實質上均句 隔。 的顆粒中 心對中心間 其中該自組合材料 21·如申請專利範圍第1項所述之浮置閑 4 旧 M04055TW-替換頁-I22906.doc YOR9-2003-0146(JHW) 46 1299575 案號：93116874 95年12月29日修正 係使用會自然形成-規則性陣列的—種材料。 22. -種浮置閘’係供使用於—場效電晶體，此浮置閑包含： 複數個離散的奈米顆粒，其中該等奈米顆粒的尺寸、間隔、 及密度中至少有-，係藉由-自組合材料，將其至少一模 板化，並加以定義； • 其中該等奈米顆粒之直徑係在約2至約30奈米之間，尺寸 分佈不大於該奈米顆粒平均直徑的約15% ;以及 其中該等奈米顆粒中讀中心間隔，其變異係控制在約 10%至約20%之間。 23· —種場效電晶體，包含： 一源極區及一没極區，形成在一半導體材料中； 參 一通道區，位於該源極區與汲極區之間； 一電絕緣材料之絕緣層，位於該通道區上方； 一電傳導材料之浮置閘層，位於該絕緣層上方； 一電絕緣材料層，位於該浮置閘層上方；以及 一閘電極覆蓋該絕緣材料層， 其中該浮置閘層包含複數個離散的奈米顆粒，該奈# 的尺寸、間隔、及密度中至少有一，係藉由一自組合材料， 4 旧 M04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 47 1299575 案號：93116874 95年12月29日修正 將其至少一模板化，並加以定義；以及 其中该等奈米顆粒係安排於一最密堆積(close-packed)之二 維六方晶格(two-dimensional hexagonal lattice)中。 24· 一種場效電晶體，包含： 一源極區及一汲極區，形成在一半導體材料中； 一通道區’位於該源極區與没極區之間； 一電絕緣材料之絕緣層，位於該通道區上方； 一電傳導材料之浮置閘層，位於該絕緣層上方； 一電絕緣材料層，位於該浮置閘層上方；以及 一閘電極覆蓋該絕緣材料層， 其中該浮置閘層包含複數個離散的奈米顆粒，該奈米顆粒 的尺寸、間隔、及密度中至少有一，係藉由一自組合材料， 將其至少一模板化，並加以定義； 其中该等奈米顆粒係安排於一最密堆積之二維六方晶格 中；以及 其中該六方晶格包括約為平均奈米顆粒直徑的丨至2倍間 之平均奈米顆粒間距(average inter_nan〇partide di_ 該奈米顆粒間距的標準偏差實質上不大於該平均間距的沈 4旧|\/104055丁\/\/-替換頁-122906.加 Y O R9-2003-0146( J H W) 48 !299575 案號：93116874 95年12月29日修正 25· 一種場效電晶體，包含： 一源極區及一汲極區，形成在一半導體材料中； 一通道區，位於該源極區與汲極區之間； 一電絕緣材料之絕緣層，位於該通道區上方； ^ 一電傳導材料之浮置閘層，位於該絕緣層上方； 一電絕緣材料層，位於該浮置閘層上方；以及 一閘電極覆蓋該絕緣材料層， € 其中該浮置閘層包含複數個離散的奈米顆粒，該奈米顆粒 的尺寸、間隔、及⑨度中至少有一，係藉由一自組合材料， 將其至少一模板化，並加以定義；以及 其中該浮置閘中的該等奈米顆粒具有第_不同尺寸與第二 不同尺寸，其中每一尺寸之直徑標準偏差係小於該奈米顆 粒之一平均直徑的約15%。 26. 一種浮置間，係供使用於一場效電晶體，此浮置間包含： 複數個離散的奈米顆粒，並中球笙大 卡顆粒之直徑係在約2 :奈：間’尺寸分佈該奈米―的 〃中，亥等不米顆粒中％對中心間隔，其變異控制在不大於 4 旧 M04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 49 1299575 案號：93116874 95年12月29日修正 約 20%。 27· —種場效電晶體’包含： 一浮置閘，包含： 複數個離散的奈米顆粒，其中該等奈米顆粒之直徑係在約 2至約30奈米之間’尺寸分佈不大於該奈米顆粒平均直徑 • 的約15% ;以及 其中該等奈米顆粒中心對中心間隔，其變異控制在不大於 約 20%。 ’此浮置閘包含： 顆粒係安排於一最 28· —種浮置閘，係供使用於一場效電晶體 複數個離散的奈米顆粒，其中該等卡 遂、堆積之二維六方晶格中。
29· ^^種場效電晶體’包含： 一浮置閘，包含： 複數個離散的奈米顆粒，其中該 W 密堆積之二維六方晶格中。Λ _粒係安排於一最 30·如申請專利範圍第12項所述 丄 贫攻電晶體，其中該二維六 4 旧 M04055TW-替換頁-I22906.doc YOR9-2003-0146(JHW) 50 1299575 案號：93116874 95年12月29日修正 方晶格並不完美，有缺陷在晶粒邊界。 31·如申請專利範圍第1項所述之浮置閘，其中該等奈米顆粒 係安排於一二維矩陣(two-dimensional array)中。 32β如申請專利範圍第26項所述之浮置閘，其中該等奈米顆粒 鲁 係安排於一二維矩陣(two-dimensional array)中。 33·如申請專利範圍第27項所述之場效電晶體，其中該等奈米 顆粒係安排於一二維矩陣(two-dimensional array)中。 4 旧 M04055TW-替換頁-122906.doc YOR9-2003-0146(JHW) 51
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Families Citing this family (121)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7226966B2 (en) 2001-08-03 2007-06-05 Nanogram Corporation Structures incorporating polymer-inorganic particle blends
US6599631B2 (en) 2001-01-26 2003-07-29 Nanogram Corporation Polymer-inorganic particle composites
US8568684B2 (en) 2000-10-17 2013-10-29 Nanogram Corporation Methods for synthesizing submicron doped silicon particles
US20090075083A1 (en) 1997-07-21 2009-03-19 Nanogram Corporation Nanoparticle production and corresponding structures
US9139906B2 (en) 2001-03-06 2015-09-22 Asm America, Inc. Doping with ALD technology
US7491634B2 (en) 2006-04-28 2009-02-17 Asm International N.V. Methods for forming roughened surfaces and applications thereof
US7045851B2 (en) * 2003-06-20 2006-05-16 International Business Machines Corporation Nonvolatile memory device using semiconductor nanocrystals and method of forming same
US7052618B2 (en) * 2004-01-28 2006-05-30 Agilent Technologies, Inc. Nanostructures and methods of making the same
WO2005089165A2 (en) 2004-03-10 2005-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US7595528B2 (en) 2004-03-10 2009-09-29 Nanosys, Inc. Nano-enabled memory devices and anisotropic charge carrying arrays
US7776758B2 (en) 2004-06-08 2010-08-17 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US8563133B2 (en) 2004-06-08 2013-10-22 Sandisk Corporation Compositions and methods for modulation of nanostructure energy levels
US7968273B2 (en) * 2004-06-08 2011-06-28 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
WO2005122235A2 (en) * 2004-06-08 2005-12-22 Nanosys, Inc. Methods and devices for forming nanostructure monolayers and devices including such monolayers
US7813160B2 (en) * 2005-01-11 2010-10-12 The Trustees Of The University Of Pennsylvania Nanocrystal quantum dot memory devices
EP1848752A2 (en) * 2005-01-11 2007-10-31 University Of Massachusetts Lowell End-capped polymer chains and products thereof
TWI240426B (en) * 2005-01-13 2005-09-21 Chung-Hua Li Manufacturing method for laminated structure of solar cell, electrode of solar cell, and the solar cell
KR100682932B1 (ko) * 2005-02-16 2007-02-15 삼성전자주식회사 비휘발성 메모리 소자 및 그 제조방법
US7309650B1 (en) * 2005-02-24 2007-12-18 Spansion Llc Memory device having a nanocrystal charge storage region and method
DE102005018096B3 (de) * 2005-04-19 2007-01-11 Infineon Technologies Ag Herstellungsverfahren für ein nichtflüchtiges Speicherelement basierend auf zwei stabilen Widerstandszuständen in organischen Molekülen
JP5009549B2 (ja) * 2005-04-22 2012-08-22 エスケーハイニックス株式会社 フラッシュメモリ素子の製造方法
JP2006324501A (ja) * 2005-05-19 2006-11-30 Toshiba Corp 相変化メモリおよびその製造方法
US8709892B2 (en) * 2005-05-23 2014-04-29 Darpa Nanoparticles in a flash memory using chaperonin proteins
US7547599B2 (en) * 2005-05-26 2009-06-16 Micron Technology, Inc. Multi-state memory cell
US8110863B2 (en) 2005-06-01 2012-02-07 Sandisk 3D Llc TFT charge storage memory cell having high-mobility corrugated channel
KR100668846B1 (ko) 2005-06-10 2007-01-16 주식회사 하이닉스반도체 상변환 기억 소자의 제조방법
KR100842903B1 (ko) 2005-06-10 2008-07-02 주식회사 하이닉스반도체 상변환 기억 소자 및 그의 제조방법
US7391074B2 (en) * 2005-08-03 2008-06-24 International Business Machines Corporation Nanowire based non-volatile floating-gate memory
TWI288473B (en) * 2005-10-05 2007-10-11 Promos Technologies Inc Flash memory structure and method for fabricating the same
US7241695B2 (en) * 2005-10-06 2007-07-10 Freescale Semiconductor, Inc. Semiconductor device having nano-pillars and method therefor
JP2007149155A (ja) * 2005-11-24 2007-06-14 Hitachi Ltd 磁気記録媒体、その作製方法、及び磁気ディスク装置
KR100837413B1 (ko) * 2006-02-28 2008-06-12 삼성전자주식회사 나노결정을 포함하는 메모리 소자 제조 방법 및 이에 의해제조된 메모리 소자
EP2047502A4 (en) * 2006-06-30 2009-12-30 Applied Materials Inc NANO CRYSTAL EDUCATION
US7667260B2 (en) * 2006-08-09 2010-02-23 Micron Technology, Inc. Nanoscale floating gate and methods of formation
US20080121967A1 (en) * 2006-09-08 2008-05-29 Ramachandran Muralidhar Nanocrystal non-volatile memory cell and method therefor
US7517747B2 (en) * 2006-09-08 2009-04-14 Freescale Semiconductor, Inc. Nanocrystal non-volatile memory cell and method therefor
US20100090265A1 (en) * 2006-10-19 2010-04-15 Micron Technology, Inc. High density nanodot nonvolatile memory
US7384852B2 (en) 2006-10-25 2008-06-10 International Business Machines Corporation Sub-lithographic gate length transistor using self-assembling polymers
US7482270B2 (en) 2006-12-05 2009-01-27 International Business Machines Corporation Fully and uniformly silicided gate structure and method for forming same
US8686490B2 (en) 2006-12-20 2014-04-01 Sandisk Corporation Electron blocking layers for electronic devices
US7847341B2 (en) 2006-12-20 2010-12-07 Nanosys, Inc. Electron blocking layers for electronic devices
WO2008085806A1 (en) 2007-01-03 2008-07-17 Nanogram Corporation Nanoparticle inks based on silicon/germanium, doped particles, printing and processes for semiconductor applications
US20090136785A1 (en) * 2007-01-03 2009-05-28 Nanosys, Inc. Methods for nanopatterning and production of magnetic nanostructures
WO2008085813A2 (en) * 2007-01-03 2008-07-17 Nanosys, Inc, Et Al. Methods for nanopatterning and production of nanostructures
US8394483B2 (en) 2007-01-24 2013-03-12 Micron Technology, Inc. Two-dimensional arrays of holes with sub-lithographic diameters formed by block copolymer self-assembly
US7964107B2 (en) * 2007-02-08 2011-06-21 Micron Technology, Inc. Methods using block copolymer self-assembly for sub-lithographic patterning
US8083953B2 (en) 2007-03-06 2011-12-27 Micron Technology, Inc. Registered structure formation via the application of directed thermal energy to diblock copolymer films
US8557128B2 (en) * 2007-03-22 2013-10-15 Micron Technology, Inc. Sub-10 nm line features via rapid graphoepitaxial self-assembly of amphiphilic monolayers
US7959975B2 (en) 2007-04-18 2011-06-14 Micron Technology, Inc. Methods of patterning a substrate
US8097175B2 (en) 2008-10-28 2012-01-17 Micron Technology, Inc. Method for selectively permeating a self-assembled block copolymer, method for forming metal oxide structures, method for forming a metal oxide pattern, and method for patterning a semiconductor structure
US8294139B2 (en) * 2007-06-21 2012-10-23 Micron Technology, Inc. Multilayer antireflection coatings, structures and devices including the same and methods of making the same
US8372295B2 (en) 2007-04-20 2013-02-12 Micron Technology, Inc. Extensions of self-assembled structures to increased dimensions via a “bootstrap” self-templating method
KR100885666B1 (ko) * 2007-05-25 2009-02-25 한국과학기술원 유기단분자층 및 블록공중합체를 포함하는 나노구조체 및그 제조방법
US8404124B2 (en) 2007-06-12 2013-03-26 Micron Technology, Inc. Alternating self-assembling morphologies of diblock copolymers controlled by variations in surfaces
JP2008311585A (ja) * 2007-06-18 2008-12-25 Elpida Memory Inc 配線構造及び半導体装置、並びにそれらの製造方法
US8080615B2 (en) 2007-06-19 2011-12-20 Micron Technology, Inc. Crosslinkable graft polymer non-preferentially wetted by polystyrene and polyethylene oxide
US8283258B2 (en) * 2007-08-16 2012-10-09 Micron Technology, Inc. Selective wet etching of hafnium aluminum oxide films
US7732533B2 (en) * 2007-08-31 2010-06-08 Micron Technology, Inc. Zwitterionic block copolymers and methods
US7723186B2 (en) * 2007-12-18 2010-05-25 Sandisk Corporation Method of forming memory with floating gates including self-aligned metal nanodots using a coupling layer
US8193055B1 (en) * 2007-12-18 2012-06-05 Sandisk Technologies Inc. Method of forming memory with floating gates including self-aligned metal nanodots using a polymer solution
KR100941021B1 (ko) * 2008-01-21 2010-02-05 고려대학교 산학협력단 삼중블록공중합체를 이용한 태양전지 제조방법
US8215074B2 (en) * 2008-02-05 2012-07-10 International Business Machines Corporation Pattern formation employing self-assembled material
US8999492B2 (en) 2008-02-05 2015-04-07 Micron Technology, Inc. Method to produce nanometer-sized features with directed assembly of block copolymers
FR2927467B1 (fr) * 2008-02-08 2011-09-23 Commissariat Energie Atomique Procede de realisation d'une grille flottante ayant une alternance de lignes en premier et second materiaux
US8101261B2 (en) * 2008-02-13 2012-01-24 Micron Technology, Inc. One-dimensional arrays of block copolymer cylinders and applications thereof
US8426313B2 (en) 2008-03-21 2013-04-23 Micron Technology, Inc. Thermal anneal of block copolymer films with top interface constrained to wet both blocks with equal preference
US8425982B2 (en) * 2008-03-21 2013-04-23 Micron Technology, Inc. Methods of improving long range order in self-assembly of block copolymer films with ionic liquids
US8545936B2 (en) 2008-03-28 2013-10-01 Asm International N.V. Methods for forming carbon nanotubes
US8114300B2 (en) 2008-04-21 2012-02-14 Micron Technology, Inc. Multi-layer method for formation of registered arrays of cylindrical pores in polymer films
US8114301B2 (en) 2008-05-02 2012-02-14 Micron Technology, Inc. Graphoepitaxial self-assembly of arrays of downward facing half-cylinders
US8114468B2 (en) * 2008-06-18 2012-02-14 Boise Technology, Inc. Methods of forming a non-volatile resistive oxide memory array
US8169031B2 (en) 2008-08-26 2012-05-01 International Business Machines Corporation Continuous metal semiconductor alloy via for interconnects
KR101051570B1 (ko) * 2009-01-29 2011-07-22 주식회사 엘지실트론 선택적 에피택시를 이용하여 휨이 제어된 에피택셜 웨이퍼 및 그 제조 방법
JP5770717B2 (ja) * 2009-05-08 2015-08-26 １３６６ テクノロジーズ インク． 堆積膜の選択的除去のための多孔質リフトオフ層
US8680629B2 (en) 2009-06-03 2014-03-25 International Business Machines Corporation Control of flatband voltages and threshold voltages in high-k metal gate stacks and structures for CMOS devices
US8383479B2 (en) 2009-07-21 2013-02-26 Sandisk Technologies Inc. Integrated nanostructure-based non-volatile memory fabrication
US8446779B2 (en) 2009-08-21 2013-05-21 Globalfoundries Singapore Pte. Ltd. Non-volatile memory using pyramidal nanocrystals as electron storage elements
KR101175325B1 (ko) * 2009-08-24 2012-08-20 한국기초과학지원연구원 양자점 형성방법
US8274116B2 (en) 2009-11-16 2012-09-25 International Business Machines Corporation Control of threshold voltages in high-k metal gate stack and structures for CMOS devices
WO2011062791A2 (en) * 2009-11-17 2011-05-26 3M Innovative Properties Company Texturing surface of light-absorbing substrate
TWI408801B (zh) * 2009-12-30 2013-09-11 Univ Nat Taiwan 非揮發性記憶體元件及其製造方法
FR2959349B1 (fr) 2010-04-22 2012-09-21 Commissariat Energie Atomique Fabrication d'une memoire a deux grilles independantes auto-alignees
CN101866927A (zh) * 2010-05-12 2010-10-20 上海宏力半导体制造有限公司 共享字线的无触点纳米晶分栅式闪存
CN101863452B (zh) * 2010-06-10 2015-06-24 中国科学院苏州纳米技术与纳米仿生研究所 一种改善绝缘衬底上纳米阵列结构器件制作的方法
US8895962B2 (en) 2010-06-29 2014-11-25 Nanogram Corporation Silicon/germanium nanoparticle inks, laser pyrolysis reactors for the synthesis of nanoparticles and associated methods
US8535544B2 (en) 2010-07-26 2013-09-17 International Business Machines Corporation Structure and method to form nanopore
FR2963355B1 (fr) 2010-07-30 2013-07-12 Centre Nat Rech Scient Films minces nanoorganises a base de copolymeres a blocs polysaccharidiques pour des applications en nanotechnologie.
US8138068B2 (en) 2010-08-11 2012-03-20 International Business Machines Corporation Method to form nanopore array
US8304493B2 (en) 2010-08-20 2012-11-06 Micron Technology, Inc. Methods of forming block copolymers
TWI440218B (zh) * 2010-10-15 2014-06-01 Preparation of nanometer microstructure
CN102456547A (zh) * 2010-10-27 2012-05-16 和椿科技股份有限公司 纳米微结构的制造方法
WO2012071330A1 (en) 2010-11-24 2012-05-31 Dow Corning Corporation Controlling morphology of block copolymers
FR2971618B1 (fr) * 2011-02-11 2015-07-31 Commissariat Energie Atomique Procede d'obtention d'un reseau de plots nanometriques
US8900963B2 (en) 2011-11-02 2014-12-02 Micron Technology, Inc. Methods of forming semiconductor device structures, and related structures
CN103187245B (zh) * 2011-12-30 2015-06-17 中芯国际集成电路制造(上海)有限公司 一种通过定向自组装嵌段共聚物的光刻方法
WO2013158527A1 (en) * 2012-04-16 2013-10-24 Brewer Science Inc. Silicon hardmask layer for directed self-assembly
US9029936B2 (en) 2012-07-02 2015-05-12 Sandisk Technologies Inc. Non-volatile memory structure containing nanodots and continuous metal layer charge traps and method of making thereof
US9087699B2 (en) 2012-10-05 2015-07-21 Micron Technology, Inc. Methods of forming an array of openings in a substrate, and related methods of forming a semiconductor device structure
US8823075B2 (en) 2012-11-30 2014-09-02 Sandisk Technologies Inc. Select gate formation for nanodot flat cell
US8987802B2 (en) * 2013-02-28 2015-03-24 Sandisk Technologies Inc. Method for using nanoparticles to make uniform discrete floating gate layer
US9331181B2 (en) 2013-03-11 2016-05-03 Sandisk Technologies Inc. Nanodot enhanced hybrid floating gate for non-volatile memory devices
US9229328B2 (en) 2013-05-02 2016-01-05 Micron Technology, Inc. Methods of forming semiconductor device structures, and related semiconductor device structures
US9177808B2 (en) 2013-05-21 2015-11-03 Sandisk Technologies Inc. Memory device with control gate oxygen diffusion control and method of making thereof
JP6271716B2 (ja) 2013-05-24 2018-01-31 帝人株式会社 シリコン／ゲルマニウム系ナノ粒子及び高粘度アルコール溶媒を含有する印刷用インク
US8969153B2 (en) 2013-07-01 2015-03-03 Sandisk Technologies Inc. NAND string containing self-aligned control gate sidewall cladding
US9064821B2 (en) 2013-08-23 2015-06-23 Taiwan Semiconductor Manufacturing Co. Ltd. Silicon dot formation by self-assembly method and selective silicon growth for flash memory
US9281203B2 (en) * 2013-08-23 2016-03-08 Taiwan Semiconductor Manufacturing Co., Ltd. Silicon dot formation by direct self-assembly method for flash memory
US9177795B2 (en) 2013-09-27 2015-11-03 Micron Technology, Inc. Methods of forming nanostructures including metal oxides
US9228994B1 (en) 2014-08-06 2016-01-05 Globalfoundries Inc. Nanochannel electrode devices
CN104409460A (zh) * 2014-10-20 2015-03-11 中国科学院微电子研究所 闪存单元及闪存装置
US9812545B2 (en) 2014-10-30 2017-11-07 City University Of Hong Kong Electronic device for data storage and a method of producing an electronic device for data storage
US9991132B2 (en) * 2015-04-17 2018-06-05 Taiwan Semiconductor Manufacturing Company, Ltd. Lithographic technique incorporating varied pattern materials
US10720504B2 (en) * 2015-09-11 2020-07-21 Intel Corporation Transistor with dynamic threshold voltage for low-leakage standby and high speed active mode
CN105742289A (zh) * 2016-02-26 2016-07-06 上海华力微电子有限公司 闪存结构
CN107170744B (zh) * 2017-04-28 2019-10-29 中国科学院微电子研究所 一种闪存单元器件及闪存
CN108962899B (zh) * 2017-05-26 2021-12-17 智瑞佳（苏州）半导体科技有限公司 一种多次可编程(mtp)存储单元结构及其制作方法
CN108511604B (zh) * 2018-04-11 2021-12-10 苏州大学 基于多巴胺的自聚电存储材料及其制备方法与在电存储器件中的应用
US10483464B1 (en) 2018-05-31 2019-11-19 Uchicago Argonne, Llc Resistive switching memory device
CN109728076B (zh) * 2018-12-28 2020-12-29 电子科技大学 一种横向抗辐射功率器件结构
CN111863605A (zh) * 2020-07-31 2020-10-30 合肥维信诺科技有限公司 薄膜晶体管及其制备方法和显示器
KR20220131561A (ko) 2021-03-12 2022-09-29 조성진 오픈소스를 이용한 Big data 기반 원격 운전을 지원하는 감시제어 시스템을이용한 감시제어 방법

Family Cites Families (39)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4045302A (en) 1976-07-08 1977-08-30 Burroughs Corporation Multilevel metallization process
US5420067A (en) * 1990-09-28 1995-05-30 The United States Of America As Represented By The Secretary Of The Navy Method of fabricatring sub-half-micron trenches and holes
KR960005246B1 (ko) * 1992-10-21 1996-04-23 현대전자산업주식회사 캐패시터의 저장전극 제조방법
US5583069A (en) * 1994-07-08 1996-12-10 Hyundai Electronics Industries Co., Ltd. Method for making a fine annular charge storage electrode in a semiconductor device using a phase-shift mask
US5656205A (en) * 1994-12-29 1997-08-12 International Business Machines Corporation Optical components from phase separated block polymers
US5714766A (en) * 1995-09-29 1998-02-03 International Business Machines Corporation Nano-structure memory device
US6139713A (en) 1996-08-26 2000-10-31 Nippon Telegraph And Telephone Corporation Method of manufacturing porous anodized alumina film
KR100216605B1 (ko) * 1996-12-06 1999-08-16 정선종 원자력 현미경을 이용한 반도체 나노세선 형성방법
US5849215A (en) 1997-01-08 1998-12-15 The Regents Of The University Of California Highly ordered nanocomposites via a monomer self-assembly in situ condensation approach
US5852306A (en) * 1997-01-29 1998-12-22 Micron Technology, Inc. Flash memory with nanocrystalline silicon film floating gate
US5948470A (en) 1997-04-28 1999-09-07 Harrison; Christopher Method of nanoscale patterning and products made thereby
US6069380A (en) * 1997-07-25 2000-05-30 Regents Of The University Of Minnesota Single-electron floating-gate MOS memory
JP3727449B2 (ja) * 1997-09-30 2005-12-14 シャープ株式会社 半導体ナノ結晶の製造方法
JP3495889B2 (ja) * 1997-10-03 2004-02-09 シャープ株式会社 半導体記憶素子
TW386314B (en) * 1998-09-19 2000-04-01 United Microelectronics Corp Structure of low power, high efficiency programmable erasable non-volatile memory cell and production method thereof
US6313185B1 (en) 1998-09-24 2001-11-06 Honeywell International Inc. Polymers having backbones with reactive groups employed in crosslinking as precursors to nanoporous thin film structures
US6705152B2 (en) 2000-10-24 2004-03-16 Nanoproducts Corporation Nanostructured ceramic platform for micromachined devices and device arrays
US6214746B1 (en) 1999-05-07 2001-04-10 Honeywell International Inc. Nanoporous material fabricated using a dissolvable reagent
US6536604B1 (en) 1999-06-25 2003-03-25 C. Jeffrey Brinker Inorganic dual-layer microporous supported membranes
JP4586219B2 (ja) * 1999-09-17 2010-11-24 ソニー株式会社 不揮発性半導体記憶装置の消去方法
US6171687B1 (en) 1999-10-18 2001-01-09 Honeywell International Inc. Infiltrated nanoporous materials and methods of producing same
US6743406B2 (en) * 1999-10-22 2004-06-01 The Board Of Trustees Of The University Of Illinois Family of discretely sized silicon nanoparticles and method for producing the same
JP2001233674A (ja) 2000-02-24 2001-08-28 Fine Seru:Kk 無機質鋳型粒子を利用したナノ細孔を持つ炭素材料の製造方法
US6320784B1 (en) * 2000-03-14 2001-11-20 Motorola, Inc. Memory cell and method for programming thereof
AU2001249323A1 (en) * 2000-03-22 2001-10-03 University Of Massachusetts Nanocylinder arrays
US6586785B2 (en) * 2000-06-29 2003-07-01 California Institute Of Technology Aerosol silicon nanoparticles for use in semiconductor device fabrication
US6271273B1 (en) 2000-07-14 2001-08-07 Shipley Company, L.L.C. Porous materials
US6589629B1 (en) 2000-09-11 2003-07-08 Lucent Technologies Inc. Process for fabricating patterned, functionalized particles and article formed from particles
JP3848070B2 (ja) * 2000-09-27 2006-11-22 株式会社東芝 パターン形成方法
US6358813B1 (en) 2000-11-15 2002-03-19 International Business Machines Corporation Method for increasing the capacitance of a semiconductor capacitors
CN1305232A (zh) * 2001-02-27 2001-07-25 南京大学 锗/硅复合纳米晶粒浮栅结构mosfet存储器
KR100408520B1 (ko) 2001-05-10 2003-12-06 삼성전자주식회사 게이트 전극과 단전자 저장 요소 사이에 양자점을구비하는 단전자 메모리 소자 및 그 제조 방법
KR100450749B1 (ko) * 2001-12-28 2004-10-01 한국전자통신연구원 어븀이 도핑된 실리콘 나노 점 어레이 제조 방법 및 이에이용되는 레이저 기화 증착 장비
US6638441B2 (en) * 2002-01-07 2003-10-28 Macronix International Co., Ltd. Method for pitch reduction
KR100459895B1 (ko) * 2002-02-09 2004-12-04 삼성전자주식회사 퀀텀 도트를 가지는 메모리 소자 및 그 제조방법
US7045851B2 (en) * 2003-06-20 2006-05-16 International Business Machines Corporation Nonvolatile memory device using semiconductor nanocrystals and method of forming same
US7630777B2 (en) * 2006-07-06 2009-12-08 Honeywell International Inc. Apparatus and method for configurable process automation in a process control system
US7850941B2 (en) * 2006-10-20 2010-12-14 General Electric Company Nanostructure arrays and methods for forming same
US7544578B2 (en) * 2007-01-03 2009-06-09 International Business Machines Corporation Structure and method for stochastic integrated circuit personalization

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