TWI282118B - Dividing method of semiconductor wafer - Google Patents

Dividing method of semiconductor wafer Download PDF

Info

Publication number
TWI282118B
TWI282118B TW092103008A TW92103008A TWI282118B TW I282118 B TWI282118 B TW I282118B TW 092103008 A TW092103008 A TW 092103008A TW 92103008 A TW92103008 A TW 92103008A TW I282118 B TWI282118 B TW I282118B
Authority
TW
Taiwan
Prior art keywords
semiconductor wafer
light
shielding member
boundary
dividing
Prior art date
Application number
TW092103008A
Other languages
English (en)
Other versions
TW200303577A (en
Inventor
Kazuma Sekiya
Original Assignee
Disco Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Disco Corp filed Critical Disco Corp
Publication of TW200303577A publication Critical patent/TW200303577A/zh
Application granted granted Critical
Publication of TWI282118B publication Critical patent/TWI282118B/zh

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B28WORKING CEMENT, CLAY, OR STONE
    • B28DWORKING STONE OR STONE-LIKE MATERIALS
    • B28D5/00Fine working of gems, jewels, crystals, e.g. of semiconductor material; apparatus or devices therefor
    • B28D5/0058Accessories specially adapted for use with machines for fine working of gems, jewels, crystals, e.g. of semiconductor material
    • B28D5/0064Devices for the automatic drive or the program control of the machines
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K26/00Working by laser beam, e.g. welding, cutting or boring
    • B23K26/36Removing material
    • B23K26/40Removing material taking account of the properties of the material involved
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306Chemical or electrical treatment, e.g. electrolytic etching
    • H01L21/308Chemical or electrical treatment, e.g. electrolytic etching using masks
    • H01L21/3083Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
    • H01L21/3086Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane characterised by the process involved to create the mask, e.g. lift-off masks, sidewalls, or to modify the mask, e.g. pre-treatment, post-treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67069Apparatus for fluid treatment for etching for drying etching
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67017Apparatus for fluid treatment
    • H01L21/67063Apparatus for fluid treatment for etching
    • H01L21/67075Apparatus for fluid treatment for etching for wet etching
    • H01L21/6708Apparatus for fluid treatment for etching for wet etching using mainly spraying means, e.g. nozzles
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/67Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
    • H01L21/67005Apparatus not specifically provided for elsewhere
    • H01L21/67011Apparatus for manufacture or treatment
    • H01L21/67092Apparatus for mechanical treatment
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2101/00Articles made by soldering, welding or cutting
    • B23K2101/36Electric or electronic devices
    • B23K2101/40Semiconductor devices
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B23MACHINE TOOLS; METAL-WORKING NOT OTHERWISE PROVIDED FOR
    • B23KSOLDERING OR UNSOLDERING; WELDING; CLADDING OR PLATING BY SOLDERING OR WELDING; CUTTING BY APPLYING HEAT LOCALLY, e.g. FLAME CUTTING; WORKING BY LASER BEAM
    • B23K2103/00Materials to be soldered, welded or cut
    • B23K2103/50Inorganic material, e.g. metals, not provided for in B23K2103/02 – B23K2103/26

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Mechanical Engineering (AREA)
  • Plasma & Fusion (AREA)
  • Optics & Photonics (AREA)
  • Dicing (AREA)
  • Laser Beam Processing (AREA)
  • Weting (AREA)

Description

1282118 ⑴ 玖、發明說明 【發明所屬之技術領域】 本發明是關於一種藉由化學式蝕刻處理來分割半_ ® 晶圓而作成各個晶片的半導體晶圓之分割方法。 【先前技術】 表示於第1 〇圖的半導體晶圓W,是經由膠帶Τ而與 框架F成爲一體。在半導體晶圓W的表面,隔著一定間 隔而柵狀地排列有界道S,在藉由界道S被區劃的多數矩 形領域形成有電路。又,使用旋轉刀片來切削界道S ’則 成爲各個半導體晶片。 然而,在藉由旋轉刀片的切削,細小缺口或應力會發 生在半導體晶片的外周之故,因而該缺口或應力成爲原因 使得抗折強度降低,藉由外力或加熱周期而使半導體晶片 容易破損,有縮短壽命之問題。尤其是,在如厚度5 0 // m以下的半導體晶片,上述缺口或應力是成爲致命性問 題。 如此,檢討不使用旋轉刀片,藉由化學式蝕刻處理進 行分割半導體晶圓的方法。該方法,是首先在形成有電路 的半導體晶圓一 W表面形成光抗蝕劑膜,使用遮光罩曝 光界道之僅上部,除去藉由曝光而變質的光抗蝕劑膜,又 藉由鈾刻俾浸蝕界道而分割成各個晶片的方法。 然而,在上述方法中,爲了僅曝光被覆於界道上部的 光抗蝕劑膜,必須準備個別地對應於半導體晶圓 W的大 -5- (2) 1282118 小及界道間隔的複數種類遮光罩之故,因而有不經濟之同 時有管理上成爲煩雜的問題。 又’需要進行形成於半導體晶圓 W的表面的界道 S 與對應於此而形成在遮光罩的對應部分的精密對位並進行 曝光的曝光裝置’及用以除去藉由曝光被變質的光抗鈾劑 膜的除去裝置之故,因而也有設備投資增大的問題。 又’在半導體晶圓W的界道S以鈾刻處理無法除去 的材質形成有對準標記等圖案時,也有實質上無法分割半 導體晶圓W的問題。 爲了解決此些問題,如揭示於日本特開 2〇0 1 - 1 2700 1號公報的發明,也提案一種使用旋轉刀片 等機械式地除去被覆界道上部的抗鈾劑膜之後,經由化學 式蝕刻俾分割成半導體晶片的方法。 但是,利用此種方法時,除去界道上部的抗鈾刻膜之 際,旋轉刀片也切入半導體晶圓等而在半導體晶片發生缺 口等,而降低抗折強度。尤其是,在極薄層間絕緣膜(低 介質常數絕緣膜)複數累層於矽晶圓上的多層構造的半導 體晶圓時,若旋轉刀片的切入量變稍大,則旋轉刀片會切 入絕緣膜,而如雲母地剝落絕緣膜之虞。 本發明之目的是在藉由化學式鈾刻處理俾分割半導體 晶圓時,以經濟性方法形成沒有缺口或應力,剝離的高品 質晶片。 【發明內容】 -6- (4) 1282118 造的半導體晶圓時,藉由使用雷射光線不會有如切削的衝 擊力施加於層間絕緣膜之故,因而不會有如雲母地剝落層 間絕緣膜之虞。 又,在除去界道上的遮光構件之際,利用切削事先形 成切削溝之後形成切存部,然後,利用雷射光線除去切存 部,可將切存部的厚度成爲均勻之故,因而不會變更雷射 光線的掃描速度與電壓,而仍以一定値進行照射。 【實施方式】 首先,參照第1 A圖至第6圖說明實施本發明的最佳 形態的第一例。第1A圖、第1B圖、第1 C圖是工序順序 地表示本發明的半導體晶圓之分割方法者;第1 A圖是表 示被覆工序;第1B圖是表示遮光構件除去工序;第1C 圖是表示剛結束化學性鈾刻處理工序之後的半導體晶圓W 的狀態。 在被覆工序中,使用自旋式塗敷機1 0俾將遮光構件 形成在半導體晶圓W的表面。在自旋式塗敷機10中,保 持有半導體晶圓W的保持台1 1是被驅動部1 2驅動而成 爲旋轉之狀態,在能堵住環狀框架F的開口部地從背側黏 貼的膠帶T的黏貼面藉由黏貼有半導體晶圓W的背面, 經由膠帶T而與框架F成爲一體的半導體晶圓W,以電 路面作爲上面而被保持在保持台1 1。 之後,藉由一面高速旋轉保持台1 1 一面將抗蝕劑聚 合物1 4從滴下部1 3滴下至半導體晶圓W的電路面,如 -8- (5) 1282118 第1A圖所示地,遮光構件1 5被覆在電路面的一面(被 覆工序)。在這裏,爲了有效率地進行後續工序,遮光構 件1 5的厚度是較薄,例如作成1 〇至5 〇 # m以下較理想 〇 又,遮光構件15是並不被限定於如上述地藉由自旋 塗敷機所形成的抗蝕劑膜,黏貼於半導體晶圓w的型式 的膠帶等也可以。 之後在遮光構件除去工序中,在被覆工序被覆的遮光 構件1 5中,僅除去被覆被形成在半導體晶圓w的電路面 的界道上部的部分。 在遮光構件除去工序中,使用表示於如第3圖的雷射 加工裝置20。在該雷射加工裝置20中,經由膠帶T而與 框架F成爲一體並在表面被覆有遮光構件15的複數半導 體晶圓W被收容於晶圓匣盒2 1。 然後,與框架F成爲一體而遮光構件1 5被覆於表面 的半導體晶圓W藉由搬出入手段22 —個一個地取出在暫 時置放置領域23,並吸附在搬運手段24被搬運至夾盤台 25並被保持。 之後,藉由夾盤台25朝+ X方向移動,使得半導體 晶圓W首先位在對準手段2 6的正下方,在此被檢測界道 ,進行該界道與構成雷射照射手段27的照射部28的Y 軸方向的對位。又,遮光構件1 5爲半透明時,則使用紅 外線進行對位,即可透過遮光構件1 5而檢測界道。 如此地進行對位’則夾盤台2 5藉由再朝+ X方向移 -9- (6) 1282118 動’雷射光線從照射部28照射至所檢測的界道上部的遮 光構件1 5,而除去被照射的部分的遮光構件1 5。 然後’每一次界道間隔地一面朝γ軸方向送出雷射 照射手段2 7,一面朝X軸方向往復移動夾盤台2 5,則除 去相同方向的所有界道上部的遮光構件。 又’旋轉90度夾盤台25之後,與上述同樣地進行雷 射光線的照射’則如第1 B圖所示,一面地被覆在電路面 上的遮光構件1 5中,僅除去界道S上部的遮光構件1 5 ( 遮光構件除去工序)。 如此地使用雷射光線而藉由除去界道上部的遮光構件 ,而在依習知曝光方法所需要的專用光罩,曝光裝置,除 去裝置成爲不需要,具有經濟性之同時,可有效率地進行 工序。 對於所有半導體晶圓完成遮光構件除去工序,則每一 晶圓匣盒2 1地搬運至下一化學性鈾刻工序。在化學性蝕 刻工序中,使用如第4圖所示的乾蝕刻裝置3 0。 表示於第4圖的乾蝕刻裝置3 0是由:進行來自從雷 射加工裝置20所搬運的晶圓匣盒2 1的半導體晶圓W的 搬出及完成化學性蝕刻工序後的半導體晶圓 W搬入至晶 圓匣盒21的搬出入手段31,及收容有藉由搬出入手段31 被搬出入的半導體晶圓W的搬出入處理室3 2,及進行乾 鈾刻的處理室3 3,及將蝕刻氣體供給於處理室3 3內的氣 體供給部3 4所構成。 完成遮光構件除去工序的半導體晶圓W,是藉由搬出 -10- (7) 1282118 入手段3 1從晶圓匣盒2 1被搬出。之後,打開具備於搬出 入處理室3 2的第一閘門3 5,半導體晶圓W載置於位在表 示於第5圖的搬出入處理室3 2內的保持部3 6 ° 如第5圖所示,搬出入處理室32與處理室33是藉由 第二閘門3 7被遮斷,惟打開第二閘門3 7時,保持部3 6 成爲可移動在搬出入處理室32內部與處理室33內部之間 〇 如第6圖所示地,在處理室3 3,朝上下方向相對地 配設有被連接於高頻電源及調諧機3 8而發生電漿的一對 高頻電極39,在本實施形態中,一方的高頻電極39成爲 兼具保持部3 6的構成。又,在保持部3 6設置冷却半導體 晶圓的冷却部40。 另一方面,在氣體供給部3 4具備:儲存鈾刻氣體的 氣體槽4 1,及將被儲存在氣體槽4 1的蝕刻氣體供給於處 理室3 3的栗4 2,同時具備:將冷却水供給於冷却部4 0 的冷却水循環器43,將吸引力供給於保持部3 6的吸引泵 44,吸引處理室33內的蝕刻氣體的吸引泵45,中和吸引 泵45所吸引的蝕刻氣體並排出至排出部47的過濾器46 〇 擬乾蝕刻完成遮光構件除去工序的半導體晶圓W之 際,打開設在搬出入處理室3 2的第一聞門3 5 ’藉由搬出 入手段3 1保持半導體晶圓w而朝第5圖的箭號方向移動 ,半導體晶圓W以表面爲上面載置在位於搬出入處理室 3 2內的保持部3 6。之後,關閉第一閘門3 5,俾將搬出入 -11 - (8) 1282118 處理室32內成爲真空。 之後,打開第二閘門3 7,藉由保持部3 6移動至處理 室3 3內,使得半導體晶圓W被收容在處理室3 3內。在 處理室3 3內,藉由泵42供給例如稀薄的氟系氣體的鈾刻 氣體,同時將高頻電壓從高頻電源及調諧器3 8供給於高 頻電極39,而藉由電獎乾鈾刻半導體晶圓W的表面。這 時候,在冷却部4 0藉由冷却水循環器4 3供給冷却水。 如此地進行乾蝕刻,則半導體晶圓W的表面中被覆 在界道上部的遮光構件是在遮光構件除去工序中被除去, 惟其他部分是以遮光構件所覆蓋之故,因而僅界道藉由蝕 刻處理被浸蝕,如第1 〇圖所示地,被分割成各個半導體 晶片C (化學性蝕刻處理工序)。 完成蝕刻之後,藉由吸引泵45吸引被供給於處理室 3 3的蝕刻氣體,而在過濾器46進行中和後從排出部47 排出至外部。之後,將處理室3 3內成爲真空後打開第二 閘門3 7,使得保持已經蝕刻的半導體晶圓W的保持部3 6 移動至搬出入處理室3 2,關閉第二閘門3 7。 半導體晶圓W移動至搬出入處理室3 2,則打開第一 閘門3 5,使得搬出入手段3 1保持半導體晶圓W並從搬出 入處理室3 2搬出,被收容在晶圓匣盒2 1。 對於所有半導體晶圓進行如上述的工序,藉由化學性 鈾刻處理被分割的所有半導體晶圓被收容在晶圓匣盒2 1 。又被覆在各該半導體晶片C的表面的遮光構件,是須使 用適當溶劑加以除去。 -12- (9) 1282118 如此所形成的各該半導體晶片C,是並不是使用旋 刀片而利用切削所分割者之故,因而成爲沒有缺口或應 的_品質者。尤其是,厚度如50 //m以下的薄半導體 圓時,藉由切削所分割的方法,則容易產生缺口或應力 故,因而若利用本發明時特別有效果。 又,半導體晶圓W爲在半導體基板上累層複數極 的層間絕緣膜的多層構造的半導體晶圓時,則藉由使用 射光線,不會有如切削時的衝擊力施加於層間絕緣膜之 ,因而也沒有如雲母地剝落層間絕緣膜之虞。 又,乾鈾刻處理是半導體晶圓的厚度愈厚則成爲愈 時,惟若如厚度5 0 // m以下的較薄半導體晶圓,在乾 刻處理上並不需要較多時間之故,因而可確保生產性, 在此點上本發明也有用。 又,在鈾刻處理無法除去的圖案等被覆層形成於界 時,則在遮光構件除去工序中將雷射光線照射在該被覆 ,就可除去該被覆層之故,因而藉由鈾刻也可分割形成 此種圖案的半導體晶圓。 以下,參照第7A圖至第9圖說明用以實施本發明 最佳形態的第二例。第7 A圖是表示剛完成被覆工序之 的半導體晶圓W的狀態;第7B圖是表示遮光構件除去 序的途中的半導體晶圓W的狀態;第7C圖是表示剛完 遮光構件除去工序之後的半導體晶圓W的狀態;第7D 是表示剛完成化學性鈾刻處理工序之後的半導體晶圓 的狀態。
轉 力 晶 之 薄 雷 故 費 蝕 而 道 層 有 的 後 工 成 圖 W -13- (10) 1282118 在被覆工序中’藉由與表市於第2圖的方法冋 法而在半導體晶圓w的表面形成遮光構件1 5 ° 在遮光構件除去工序中,首先使用表示於第8 削裝置5 0,如第7 ( B )圖所示地,在界道上部的 件1 5形成切削溝1 5 a。
在該切削裝置5 0中,經由膠帶T而與框架F 體,遮光構件1 5被覆於表面的複數半導體晶圓W 於晶圓匣盒5 1。 然後,與框架F成爲一體而遮光構件1 5被覆 的半導體晶圓W藉由搬出入手段52 —個一個地取 時置放領域53,並吸附搬運手段54被搬運至夾| 並被保持。 之後,藉由夾盤台55朝+ X方向移動,使得 晶圓W首先位在對準手段5 6的正下方,在此被檢 ,進行該界道與構成切削手段5 7的旋轉刀片5 8 t 方向的對位。又,遮光構件1 5爲半透明時,則使 線進行對位,即可透過遮光構件1 5而檢測界道。 如此地進行對位,則夾盤台5 5朝+ X方向移 時一面使旋轉刀片5 8高速旋轉一面下降切削手段 使高速旋轉的旋轉刀片5 8切入所檢測的界道上部 構件1 5。 迨時候’藉由尚精確度地控制利用旋轉刀片5 入量,而不會除去界道上部的所有遮光構件1 5地 削溝1 5 a。亦即如第7 B圖所示地,形成有切存部 樣的方 圖的切 遮光構 成爲~* 被收容 於表面 出在暫 !台55 半導體 測界道 )Y軸 用紅外 動,同 57,並 的遮光 8的切 形成切 15b地 -14- (11) 1282118 進行切削。 如此,擬高精確度地控制依旋轉刀片5 8的切入量, 必須事先設定切削手段5 7的基準位置。所以如第9圖所 示地,徐徐地下降旋轉刀片5 8裝設於心軸5 9而藉由凸緣 60a、60b及螺帽61被固定的構成的切削手段57,而在檢 測部62檢測旋轉刀片5 8與夾盤台5 5周圍的金屬部5 5 a 時的導通,這時候的切削手段5 7的位置作爲Z軸方向的 基準位置。 金屬部55a的表面與夾盤台55的表面是在相同平面 上,半導體晶圓W的背面是無間隙地吸附在夾盤台5 5之 故,因而以上述基準位置作爲基準並將旋轉刀片58的Z 軸方向的位置與形成所有切削溝1 5 a時同樣地控制,則切 存部1 5 b的厚度是高精度地均成爲均勻。 將如上述地進行的切削,朝X軸方向往復移動夾盤 台5 5之同時,每隔界道間隔地一面朝Y軸方向送出切削 手段57,一面進行,則切削溝1 5 a形成在相同方向的所 有界道上部之同時,形成有切存部15b。 又,旋轉90度夾盤台25之後,與上述同樣地進行切 削,則切削溝1 5 a形成於所有界道上部的遮光構件1 5之 同時,形成有切存部1 5b (遮光構件除去工序)。 之後,藉由與表示於第3圖的方法同樣的方法,將雷 射光線照射在切削溝1 5a的底部亦即切存部1 5b,則如第 7 C圖所示地’除去切存部1 5 b (遮光構件除去工序)。 如此地在最初形成切削溝15a之後形成切存部15b, -15- (12) 1282118 若遮光構件15的表面未形成平滑,切存部15b的厚度是 高精確度地也成爲均勻之故,因而在不變更雷射光線的掃 描速度與電壓之下可有效率且順利地除去遮光構件1 5。 然後’使用表示於第4圖至第6圖的乾蝕刻裝置3 0 而藉由蝕刻半導體晶圓W的界道,如第7D圖所示地,被 分割成各個半導體晶片C。 又,在以上說明中,藉由乾蝕刻進行化學性蝕刻處理 工序之情形,惟並不被限定於鈾刻,也可藉由在氟酸系的 鈾刻液浸漬的濕蝕刻進行。 (產業上之利用可能性) 如上述地,本發明的半導體晶圓之分割方法,是以遮 光構件被覆半導體晶圓的電路面,利用雷射光線除去界道 上的遮光構件之後,利用化學性地蝕刻界道並分割成各個 半導體晶片之故,因而在製造沒有缺口等的高抗折強度又 高品質的半導體晶片。尤其是,在分割被累層有複數極薄 的層間絕緣膜的多層構造的半導體晶圓時,藉由使用雷射 光線不會有如切削的衝撃力施加於層間絕緣膜,不會有如 雲母地剝落絕緣膜之虞之故,因而成爲特別地有用。 【圖式簡單說明】 第1A圖是表示剛完成遮光工序之後的半導體晶圓W 的狀態的說明圖。 第1B圖是表示剛完成遮光構件除去工序之後的半導 -16 - (13) 1282118 體晶圓W的狀態的說明圖。 第1 C圖是表示剛完成化學性蝕刻處理工序之後的半 導體晶圓w的狀態的說明圖。 第2圖是表示使用於被覆工序的自旋塗敷機的一例的 立體圖。 第3圖是表示使用於遮光構件除去工序的雷射加工裝 置的一例的立體圖。 第4圖是表示使用於化學性蝕刻處理工序的乾鈾刻裝 置的一例的立體圖。 第5圖是表示該乾鈾刻裝置的搬出入處理室及處理室 的剖視圖。 第6圖是表示該乾鈾刻裝置的處理室及氣體供給部的 構成的說明圖。 第7A圖是表示剛完成被覆工序之後的半導體晶圓W 的狀態的說明圖。 第7B圖是表示剛完成遮光構件除去工序之後的切削 溝形成之後的半導體晶圓W的狀態的說明圖。 第7C圖是表示剛完成遮光構件除去工序之後的半導 體晶圓W的狀態的說明圖。 第7D圖是表示剛完成化學性鈾刻處理工序之後的半 導體晶圓W的狀態的說明圖。 第8圖是表示使用於形成遮光構件除去工序的切削溝 的切削裝置的一例的立體圖。 第9圖是表示設定構成該切削裝置的切削手段的基準 -17- (14) 1282118 位置的情形的說明圖。 第1 〇圖是表示經由保持膠帶成爲與框架成爲一體的 半導體晶圓的俯視圖。 【主要元件對照表】 10 白 旋 塗 敷 機 11 保 持 台 12 驅 動 部 13 滴 下 部 14 抗 蝕 劑 聚 合 物 15 遮 光 劑 構 件 20 雷 射 加 工 裝 置 21、 5 1 晶 圓 匣 合 Γ1 1 L 22 > 52 搬 出 入 手 段 23、 53 暫 時 置 放 領 域 24、 5 4 搬 送 手 段 25、 5 5 夾 盤 台 26、 5 6 對 準 手 段 27 雷 射 照 射 手 段 28 照 射 部 3 0 乾 鈾 刻 裝 置 3 1 搬 出 入 手 段 3 2 搬 出 入 處 理 室 3 3 處 理 室
-18- (15)1282118 3 4 氣體供給部 3 5 第一閘門 3 6 保持部 3 7 第二閘門 3 8 調諧機 3 9 高頻電極 40 冷却部 4 1 氣體槽 42 泵 43 冷却水循環器 44、4 5 吸引栗 46 過濾器 47 排出部 50 切削裝置 57 切削手段 5 8 旋轉刀片 59 心軸 60a、 60b 凸緣 6 1 螺帽 62 檢測部 C 半導體晶片 w 半導體晶圓 F 框架 T 膠帶
-19- 1282118

Claims (1)

1282118 拾、申請專利範圍 第92 1 03008號專利申請案 中文申請專利範圍修正本 民國95年6月12日修正 1 · 一種半導體晶圓之分割方法,屬於每一個電路的 半導體晶片地分割電路形成在藉由界道所區劃的多數領域 的半導體晶圓的半導體晶圓之分割方法,其特徵爲至少由
至少以遮光構件被覆該半導體晶圓的電路面的被覆工 序,及 藉雷射光線的照射除去被覆該界道上部的遮光構件的 遮光構件除去工序,及
在被覆該界道上部的遮光構件被除去的半導體晶圓施 以化學性蝕刻,俾浸蝕該界道而分割成各個半導體晶片的 化學性蝕刻處理工序 所構成; 在遮光構件除去工序中,藉雷射光線的遮光構件的除 去之前,將切削溝形成在界道上部的遮光構件而將該遮光 構件的切存部厚度作成均勻,之後,將雷射光線照射在該 切削溝的底部俾除去遮光構件。 2. 如申請專利範圍第1項所述的半導體晶圓之分割方 法,其中,半導體晶圓是多層配線形成在半導體基板上的 半導體晶圓,而在界道上,累層有層間絕緣膜。 3. 如申請專利範圍第1項所述的半導體晶圓之分割方 1282118 法,其中,藉由化學性蝕刻無法除去的被覆層形成在界道 上時,在遮光構件除去工序中將雷射光線照射在界道而除 去該被覆層。 4.如申請專利範圍第1項所述的半導體晶圓之分割方 法,其中,化學性蝕刻工序的化學性蝕刻處理,是利用氟 系氣體的乾式蝕刻處理。
5 .如申請專利範圍第1項所述的半導體晶圓之分割方 法,其中,半導體晶圓的厚度爲50 V m以下。
-2-
TW092103008A 2002-02-25 2003-02-13 Dividing method of semiconductor wafer TWI282118B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2002047864 2002-02-25

Publications (2)

Publication Number Publication Date
TW200303577A TW200303577A (en) 2003-09-01
TWI282118B true TWI282118B (en) 2007-06-01

Family

ID=27750719

Family Applications (1)

Application Number Title Priority Date Filing Date
TW092103008A TWI282118B (en) 2002-02-25 2003-02-13 Dividing method of semiconductor wafer

Country Status (8)

Country Link
US (1) US20040137700A1 (zh)
JP (1) JP4447325B2 (zh)
KR (1) KR20040086725A (zh)
CN (1) CN1515025A (zh)
AU (1) AU2003246348A1 (zh)
DE (1) DE10391811B4 (zh)
TW (1) TWI282118B (zh)
WO (1) WO2003071591A1 (zh)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8728915B2 (en) 2008-07-03 2014-05-20 Advanced Semiconductor Engineering, Inc. Wafer laser-making method and die fabricated using the same

Families Citing this family (118)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
ATE316691T1 (de) 2002-04-19 2006-02-15 Xsil Technology Ltd Laser-behandlung
ATE552934T1 (de) * 2003-06-06 2012-04-15 Electro Scient Ind Inc Laserbearbeitung mit hilfe eines tensidfilms
JP4456421B2 (ja) * 2004-06-22 2010-04-28 株式会社ディスコ 加工装置
JP4018088B2 (ja) * 2004-08-02 2007-12-05 松下電器産業株式会社 半導体ウェハの分割方法及び半導体素子の製造方法
JP4018096B2 (ja) 2004-10-05 2007-12-05 松下電器産業株式会社 半導体ウェハの分割方法、及び半導体素子の製造方法
GB2420443B (en) * 2004-11-01 2009-09-16 Xsil Technology Ltd Increasing die strength by etching during or after dicing
JP4769451B2 (ja) * 2004-12-01 2011-09-07 株式会社ディスコ 露光装置
JP4571870B2 (ja) * 2005-02-02 2010-10-27 株式会社ディスコ 露光装置
JP2006253402A (ja) * 2005-03-10 2006-09-21 Nec Electronics Corp 半導体装置の製造方法
JP4554419B2 (ja) * 2005-04-06 2010-09-29 株式会社ディスコ ウェーハの分割方法
JP2006294807A (ja) * 2005-04-08 2006-10-26 Disco Abrasive Syst Ltd ウエーハの分割方法
US7538295B2 (en) * 2005-04-21 2009-05-26 Hewlett-Packard Development Company, L.P. Laser welding system
JP4774852B2 (ja) * 2005-08-02 2011-09-14 セイコーエプソン株式会社 構造体の製造方法
JP5432481B2 (ja) 2008-07-07 2014-03-05 ルネサスエレクトロニクス株式会社 半導体装置の製造方法および半導体装置
JP5254733B2 (ja) * 2008-10-02 2013-08-07 株式会社ディスコ ウォータジェット加工方法
US8642448B2 (en) 2010-06-22 2014-02-04 Applied Materials, Inc. Wafer dicing using femtosecond-based laser and plasma etch
KR101222489B1 (ko) * 2011-03-09 2013-01-15 한국기계연구원 레이저를 이용한 웨이퍼의 국부적 비정질화를 선행한 이방성 에칭방법 및 이를 이용한 다이싱 방법 및 드릴링 방법
US9070760B2 (en) * 2011-03-14 2015-06-30 Plasma-Therm Llc Method and apparatus for plasma dicing a semi-conductor wafer
US8557683B2 (en) 2011-06-15 2013-10-15 Applied Materials, Inc. Multi-step and asymmetrically shaped laser beam scribing
US8759197B2 (en) 2011-06-15 2014-06-24 Applied Materials, Inc. Multi-step and asymmetrically shaped laser beam scribing
US8912077B2 (en) * 2011-06-15 2014-12-16 Applied Materials, Inc. Hybrid laser and plasma etch wafer dicing using substrate carrier
US20120322235A1 (en) * 2011-06-15 2012-12-20 Wei-Sheng Lei Wafer dicing using hybrid galvanic laser scribing process with plasma etch
US8507363B2 (en) 2011-06-15 2013-08-13 Applied Materials, Inc. Laser and plasma etch wafer dicing using water-soluble die attach film
US8557682B2 (en) * 2011-06-15 2013-10-15 Applied Materials, Inc. Multi-layer mask for substrate dicing by laser and plasma etch
US8598016B2 (en) * 2011-06-15 2013-12-03 Applied Materials, Inc. In-situ deposited mask layer for device singulation by laser scribing and plasma etch
US9029242B2 (en) 2011-06-15 2015-05-12 Applied Materials, Inc. Damage isolation by shaped beam delivery in laser scribing process
US8703581B2 (en) * 2011-06-15 2014-04-22 Applied Materials, Inc. Water soluble mask for substrate dicing by laser and plasma etch
US9126285B2 (en) * 2011-06-15 2015-09-08 Applied Materials, Inc. Laser and plasma etch wafer dicing using physically-removable mask
US9129904B2 (en) 2011-06-15 2015-09-08 Applied Materials, Inc. Wafer dicing using pulse train laser with multiple-pulse bursts and plasma etch
US8951819B2 (en) 2011-07-11 2015-02-10 Applied Materials, Inc. Wafer dicing using hybrid split-beam laser scribing process with plasma etch
US8652940B2 (en) 2012-04-10 2014-02-18 Applied Materials, Inc. Wafer dicing used hybrid multi-step laser scribing process with plasma etch
KR20130117474A (ko) * 2012-04-18 2013-10-28 서울바이오시스 주식회사 배면에 패턴을 갖는 기판을 구비하는 발광다이오드 및 그의 제조방법
US8946057B2 (en) 2012-04-24 2015-02-03 Applied Materials, Inc. Laser and plasma etch wafer dicing using UV-curable adhesive film
US8969177B2 (en) 2012-06-29 2015-03-03 Applied Materials, Inc. Laser and plasma etch wafer dicing with a double sided UV-curable adhesive film
US9048309B2 (en) 2012-07-10 2015-06-02 Applied Materials, Inc. Uniform masking for wafer dicing using laser and plasma etch
US8993414B2 (en) 2012-07-13 2015-03-31 Applied Materials, Inc. Laser scribing and plasma etch for high die break strength and clean sidewall
US8859397B2 (en) 2012-07-13 2014-10-14 Applied Materials, Inc. Method of coating water soluble mask for laser scribing and plasma etch
US8845854B2 (en) 2012-07-13 2014-09-30 Applied Materials, Inc. Laser, plasma etch, and backside grind process for wafer dicing
US8940619B2 (en) * 2012-07-13 2015-01-27 Applied Materials, Inc. Method of diced wafer transportation
US9159574B2 (en) 2012-08-27 2015-10-13 Applied Materials, Inc. Method of silicon etch for trench sidewall smoothing
CN102848084B (zh) * 2012-09-28 2015-09-16 合肥彩虹蓝光科技有限公司 一种具有不同切割深度的发光原件切割方法
US9252057B2 (en) 2012-10-17 2016-02-02 Applied Materials, Inc. Laser and plasma etch wafer dicing with partial pre-curing of UV release dicing tape for film frame wafer application
US8975162B2 (en) 2012-12-20 2015-03-10 Applied Materials, Inc. Wafer dicing from wafer backside
US8980726B2 (en) * 2013-01-25 2015-03-17 Applied Materials, Inc. Substrate dicing by laser ablation and plasma etch damage removal for ultra-thin wafers
US9236305B2 (en) 2013-01-25 2016-01-12 Applied Materials, Inc. Wafer dicing with etch chamber shield ring for film frame wafer applications
WO2014159464A1 (en) 2013-03-14 2014-10-02 Applied Materials, Inc. Multi-layer mask including non-photodefinable laser energy absorbing layer for substrate dicing by laser and plasma etch
US8883614B1 (en) 2013-05-22 2014-11-11 Applied Materials, Inc. Wafer dicing with wide kerf by laser scribing and plasma etching hybrid approach
JP6336719B2 (ja) 2013-07-16 2018-06-06 株式会社ディスコ プラズマエッチング装置
US20150037915A1 (en) * 2013-07-31 2015-02-05 Wei-Sheng Lei Method and system for laser focus plane determination in a laser scribing process
DE102013108583A1 (de) 2013-08-08 2015-03-05 Osram Opto Semiconductors Gmbh Verfahren zum Vereinzeln eines Verbundes in Halbleiterchips und Halbleiterchip
JP6113022B2 (ja) * 2013-08-13 2017-04-12 株式会社ディスコ プラズマエッチング装置
US9105710B2 (en) * 2013-08-30 2015-08-11 Applied Materials, Inc. Wafer dicing method for improving die packaging quality
JP6276947B2 (ja) * 2013-09-02 2018-02-07 株式会社ディスコ 加工方法
US9224650B2 (en) 2013-09-19 2015-12-29 Applied Materials, Inc. Wafer dicing from wafer backside and front side
US9460966B2 (en) 2013-10-10 2016-10-04 Applied Materials, Inc. Method and apparatus for dicing wafers having thick passivation polymer layer
US9041198B2 (en) 2013-10-22 2015-05-26 Applied Materials, Inc. Maskless hybrid laser scribing and plasma etching wafer dicing process
US9312177B2 (en) 2013-12-06 2016-04-12 Applied Materials, Inc. Screen print mask for laser scribe and plasma etch wafer dicing process
US9299614B2 (en) 2013-12-10 2016-03-29 Applied Materials, Inc. Method and carrier for dicing a wafer
US9293304B2 (en) 2013-12-17 2016-03-22 Applied Materials, Inc. Plasma thermal shield for heat dissipation in plasma chamber
JP2015138858A (ja) * 2014-01-22 2015-07-30 株式会社ディスコ ウェーハの加工方法
US8927393B1 (en) 2014-01-29 2015-01-06 Applied Materials, Inc. Water soluble mask formation by dry film vacuum lamination for laser and plasma dicing
US9012305B1 (en) 2014-01-29 2015-04-21 Applied Materials, Inc. Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate non-reactive post mask-opening clean
US9299611B2 (en) 2014-01-29 2016-03-29 Applied Materials, Inc. Method of wafer dicing using hybrid laser scribing and plasma etch approach with mask plasma treatment for improved mask etch resistance
US9018079B1 (en) 2014-01-29 2015-04-28 Applied Materials, Inc. Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate reactive post mask-opening clean
US9236284B2 (en) 2014-01-31 2016-01-12 Applied Materials, Inc. Cooled tape frame lift and low contact shadow ring for plasma heat isolation
US8991329B1 (en) 2014-01-31 2015-03-31 Applied Materials, Inc. Wafer coating
EP2908335B1 (en) * 2014-02-14 2020-04-15 ams AG Dicing method
US20150255349A1 (en) 2014-03-07 2015-09-10 JAMES Matthew HOLDEN Approaches for cleaning a wafer during hybrid laser scribing and plasma etching wafer dicing processes
US9130030B1 (en) 2014-03-07 2015-09-08 Applied Materials, Inc. Baking tool for improved wafer coating process
US9275902B2 (en) 2014-03-26 2016-03-01 Applied Materials, Inc. Dicing processes for thin wafers with bumps on wafer backside
US9076860B1 (en) 2014-04-04 2015-07-07 Applied Materials, Inc. Residue removal from singulated die sidewall
US8975163B1 (en) 2014-04-10 2015-03-10 Applied Materials, Inc. Laser-dominated laser scribing and plasma etch hybrid wafer dicing
US8932939B1 (en) 2014-04-14 2015-01-13 Applied Materials, Inc. Water soluble mask formation by dry film lamination
US8912078B1 (en) 2014-04-16 2014-12-16 Applied Materials, Inc. Dicing wafers having solder bumps on wafer backside
US8999816B1 (en) 2014-04-18 2015-04-07 Applied Materials, Inc. Pre-patterned dry laminate mask for wafer dicing processes
US8912075B1 (en) 2014-04-29 2014-12-16 Applied Materials, Inc. Wafer edge warp supression for thin wafer supported by tape frame
US9159621B1 (en) 2014-04-29 2015-10-13 Applied Materials, Inc. Dicing tape protection for wafer dicing using laser scribe process
US8980727B1 (en) 2014-05-07 2015-03-17 Applied Materials, Inc. Substrate patterning using hybrid laser scribing and plasma etching processing schemes
US9112050B1 (en) 2014-05-13 2015-08-18 Applied Materials, Inc. Dicing tape thermal management by wafer frame support ring cooling during plasma dicing
JP2015220240A (ja) * 2014-05-14 2015-12-07 株式会社ディスコ ウェーハの加工方法
US9034771B1 (en) 2014-05-23 2015-05-19 Applied Materials, Inc. Cooling pedestal for dicing tape thermal management during plasma dicing
US9093518B1 (en) 2014-06-30 2015-07-28 Applied Materials, Inc. Singulation of wafers having wafer-level underfill
US9165832B1 (en) 2014-06-30 2015-10-20 Applied Materials, Inc. Method of die singulation using laser ablation and induction of internal defects with a laser
US9142459B1 (en) 2014-06-30 2015-09-22 Applied Materials, Inc. Wafer dicing using hybrid laser scribing and plasma etch approach with mask application by vacuum lamination
US9130057B1 (en) 2014-06-30 2015-09-08 Applied Materials, Inc. Hybrid dicing process using a blade and laser
US9349648B2 (en) 2014-07-22 2016-05-24 Applied Materials, Inc. Hybrid wafer dicing approach using a rectangular shaped two-dimensional top hat laser beam profile or a linear shaped one-dimensional top hat laser beam profile laser scribing process and plasma etch process
US9196498B1 (en) 2014-08-12 2015-11-24 Applied Materials, Inc. Stationary actively-cooled shadow ring for heat dissipation in plasma chamber
US9117868B1 (en) 2014-08-12 2015-08-25 Applied Materials, Inc. Bipolar electrostatic chuck for dicing tape thermal management during plasma dicing
US9281244B1 (en) 2014-09-18 2016-03-08 Applied Materials, Inc. Hybrid wafer dicing approach using an adaptive optics-controlled laser scribing process and plasma etch process
US11195756B2 (en) 2014-09-19 2021-12-07 Applied Materials, Inc. Proximity contact cover ring for plasma dicing
US9177861B1 (en) 2014-09-19 2015-11-03 Applied Materials, Inc. Hybrid wafer dicing approach using laser scribing process based on an elliptical laser beam profile or a spatio-temporal controlled laser beam profile
US9196536B1 (en) 2014-09-25 2015-11-24 Applied Materials, Inc. Hybrid wafer dicing approach using a phase modulated laser beam profile laser scribing process and plasma etch process
US9130056B1 (en) 2014-10-03 2015-09-08 Applied Materials, Inc. Bi-layer wafer-level underfill mask for wafer dicing and approaches for performing wafer dicing
US9245803B1 (en) 2014-10-17 2016-01-26 Applied Materials, Inc. Hybrid wafer dicing approach using a bessel beam shaper laser scribing process and plasma etch process
US10692765B2 (en) 2014-11-07 2020-06-23 Applied Materials, Inc. Transfer arm for film frame substrate handling during plasma singulation of wafers
US9355907B1 (en) 2015-01-05 2016-05-31 Applied Materials, Inc. Hybrid wafer dicing approach using a line shaped laser beam profile laser scribing process and plasma etch process
US9330977B1 (en) 2015-01-05 2016-05-03 Applied Materials, Inc. Hybrid wafer dicing approach using a galvo scanner and linear stage hybrid motion laser scribing process and plasma etch process
US9159624B1 (en) 2015-01-05 2015-10-13 Applied Materials, Inc. Vacuum lamination of polymeric dry films for wafer dicing using hybrid laser scribing and plasma etch approach
US9601375B2 (en) 2015-04-27 2017-03-21 Applied Materials, Inc. UV-cure pre-treatment of carrier film for wafer dicing using hybrid laser scribing and plasma etch approach
US9721839B2 (en) 2015-06-12 2017-08-01 Applied Materials, Inc. Etch-resistant water soluble mask for hybrid wafer dicing using laser scribing and plasma etch
US9478455B1 (en) 2015-06-12 2016-10-25 Applied Materials, Inc. Thermal pyrolytic graphite shadow ring assembly for heat dissipation in plasma chamber
JP2017041587A (ja) * 2015-08-21 2017-02-23 株式会社ディスコ ウエーハの分割方法
JP6469854B2 (ja) * 2015-11-09 2019-02-13 古河電気工業株式会社 半導体チップの製造方法及びこれに用いるマスク一体型表面保護テープ
US9972575B2 (en) 2016-03-03 2018-05-15 Applied Materials, Inc. Hybrid wafer dicing approach using a split beam laser scribing process and plasma etch process
JP6575874B2 (ja) * 2016-03-09 2019-09-18 パナソニックIpマネジメント株式会社 素子チップの製造方法
US9852997B2 (en) 2016-03-25 2017-12-26 Applied Materials, Inc. Hybrid wafer dicing approach using a rotating beam laser scribing process and plasma etch process
US9793132B1 (en) 2016-05-13 2017-10-17 Applied Materials, Inc. Etch mask for hybrid laser scribing and plasma etch wafer singulation process
JP6887722B2 (ja) * 2016-10-25 2021-06-16 株式会社ディスコ ウェーハの加工方法及び切削装置
US11158540B2 (en) 2017-05-26 2021-10-26 Applied Materials, Inc. Light-absorbing mask for hybrid laser scribing and plasma etch wafer singulation process
US10363629B2 (en) 2017-06-01 2019-07-30 Applied Materials, Inc. Mitigation of particle contamination for wafer dicing processes
US10535561B2 (en) 2018-03-12 2020-01-14 Applied Materials, Inc. Hybrid wafer dicing approach using a multiple pass laser scribing process and plasma etch process
US11355394B2 (en) 2018-09-13 2022-06-07 Applied Materials, Inc. Wafer dicing using hybrid laser scribing and plasma etch approach with intermediate breakthrough treatment
JP7171138B2 (ja) 2018-12-06 2022-11-15 株式会社ディスコ デバイスチップの製造方法
US11011424B2 (en) 2019-08-06 2021-05-18 Applied Materials, Inc. Hybrid wafer dicing approach using a spatially multi-focused laser beam laser scribing process and plasma etch process
US11342226B2 (en) 2019-08-13 2022-05-24 Applied Materials, Inc. Hybrid wafer dicing approach using an actively-focused laser beam laser scribing process and plasma etch process
US10903121B1 (en) 2019-08-14 2021-01-26 Applied Materials, Inc. Hybrid wafer dicing approach using a uniform rotating beam laser scribing process and plasma etch process
US11600492B2 (en) 2019-12-10 2023-03-07 Applied Materials, Inc. Electrostatic chuck with reduced current leakage for hybrid laser scribing and plasma etch wafer singulation process
US11211247B2 (en) 2020-01-30 2021-12-28 Applied Materials, Inc. Water soluble organic-inorganic hybrid mask formulations and their applications

Family Cites Families (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4049944A (en) * 1973-02-28 1977-09-20 Hughes Aircraft Company Process for fabricating small geometry semiconductive devices including integrated components
JP4387007B2 (ja) * 1999-10-26 2009-12-16 株式会社ディスコ 半導体ウェーハの分割方法
JP2001144126A (ja) * 1999-11-12 2001-05-25 Matsushita Electric Ind Co Ltd 半導体装置の製造方法および半導体装置
US6642127B2 (en) * 2001-10-19 2003-11-04 Applied Materials, Inc. Method for dicing a semiconductor wafer
JP2003257896A (ja) * 2002-02-28 2003-09-12 Disco Abrasive Syst Ltd 半導体ウェーハの分割方法

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8728915B2 (en) 2008-07-03 2014-05-20 Advanced Semiconductor Engineering, Inc. Wafer laser-making method and die fabricated using the same

Also Published As

Publication number Publication date
TW200303577A (en) 2003-09-01
JPWO2003071591A1 (ja) 2005-06-16
KR20040086725A (ko) 2004-10-12
DE10391811T5 (de) 2005-04-14
DE10391811B4 (de) 2012-06-21
WO2003071591A1 (fr) 2003-08-28
JP4447325B2 (ja) 2010-04-07
AU2003246348A1 (en) 2003-09-09
CN1515025A (zh) 2004-07-21
US20040137700A1 (en) 2004-07-15

Similar Documents

Publication Publication Date Title
TWI282118B (en) Dividing method of semiconductor wafer
TWI259555B (en) Dividing method of semiconductor wafer
JP5023614B2 (ja) 半導体チップの製造方法及び半導体ウエハの処理方法
JP4387007B2 (ja) 半導体ウェーハの分割方法
KR100678753B1 (ko) 반도체 웨이퍼의 분할 방법
JP2008159985A (ja) 半導体チップの製造方法
US20130014905A1 (en) Film peeling apparatus and film peeling method
WO2006038699A1 (en) Method for dividing semiconductor wafer and manufacturing method for semiconductor devices
TW201834037A (zh) 晶圓的加工方法
JP2018041935A (ja) 分割方法
JP6994307B2 (ja) 基板処理装置および基板処理方法
JP2004096086A (ja) 処理装置及び処理方法
JP2006294807A (ja) ウエーハの分割方法
WO2004006318A1 (ja) 処理装置及び処理方法
CN113614889A (zh) 衬底处理方法及衬底处理装置
JPH1098090A (ja) 基板保持装置及び露光装置
JPH11323576A (ja) ウエットエッチング方法
JP2623495B2 (ja) 不要レジスト除去方法及び装置
JP3324008B2 (ja) 回転塗布によって形成された塗布基板の不要膜除去装置
JP7418535B2 (ja) 基板処理装置及び基板処理方法
JPH06302509A (ja) レジスト剥離方法およびその装置
JPH06202128A (ja) 薄膜加工方法
KR101009808B1 (ko) 검사 장치, 검사 방법 및 기억 매체
JP3663940B2 (ja) 微小構造体の製造装置、および微小構造体の製造方法
JP2884927B2 (ja) レジスト塗布装置

Legal Events

Date Code Title Description
MK4A Expiration of patent term of an invention patent