TWI259555B - Dividing method of semiconductor wafer - Google Patents
Dividing method of semiconductor wafer Download PDFInfo
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- TWI259555B TWI259555B TW092103690A TW92103690A TWI259555B TW I259555 B TWI259555 B TW I259555B TW 092103690 A TW092103690 A TW 092103690A TW 92103690 A TW92103690 A TW 92103690A TW I259555 B TWI259555 B TW I259555B
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- semiconductor wafer
- tape member
- boundary
- dividing
- cutting
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- 239000004065 semiconductor Substances 0.000 title claims abstract description 108
- 238000000034 method Methods 0.000 title claims abstract description 36
- 238000003486 chemical etching Methods 0.000 claims abstract description 13
- 238000005530 etching Methods 0.000 claims abstract description 12
- 235000012431 wafers Nutrition 0.000 claims description 108
- 229910052770 Uranium Inorganic materials 0.000 claims description 19
- JFALSRSLKYAFGM-UHFFFAOYSA-N uranium(0) Chemical compound [U] JFALSRSLKYAFGM-UHFFFAOYSA-N 0.000 claims description 18
- 238000001312 dry etching Methods 0.000 claims description 11
- 239000011248 coating agent Substances 0.000 claims description 4
- 238000000576 coating method Methods 0.000 claims description 4
- 239000000126 substance Substances 0.000 claims description 2
- 230000011218 segmentation Effects 0.000 claims 2
- 239000000463 material Substances 0.000 description 7
- 229920002120 photoresistant polymer Polymers 0.000 description 7
- 238000001816 cooling Methods 0.000 description 5
- 239000000498 cooling water Substances 0.000 description 5
- 238000005452 bending Methods 0.000 description 2
- 239000011247 coating layer Substances 0.000 description 2
- 229920000139 polyethylene terephthalate Polymers 0.000 description 2
- 239000005020 polyethylene terephthalate Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- YCKRFDGAMUMZLT-UHFFFAOYSA-N Fluorine atom Chemical compound [F] YCKRFDGAMUMZLT-UHFFFAOYSA-N 0.000 description 1
- KJTLSVCANCCWHF-UHFFFAOYSA-N Ruthenium Chemical compound [Ru] KJTLSVCANCCWHF-UHFFFAOYSA-N 0.000 description 1
- 239000000853 adhesive Substances 0.000 description 1
- 230000001070 adhesive effect Effects 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 230000000694 effects Effects 0.000 description 1
- 229910052731 fluorine Inorganic materials 0.000 description 1
- 239000011737 fluorine Substances 0.000 description 1
- 238000010438 heat treatment Methods 0.000 description 1
- 238000010030 laminating Methods 0.000 description 1
- 238000006386 neutralization reaction Methods 0.000 description 1
- -1 polyethylene terephthalate Polymers 0.000 description 1
- 229910052707 ruthenium Inorganic materials 0.000 description 1
- 238000004904 shortening Methods 0.000 description 1
Classifications
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/683—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L21/6835—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L21/6836—Wafer tapes, e.g. grinding or dicing support tapes
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67092—Apparatus for mechanical treatment
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/67—Apparatus specially adapted for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus specially adapted for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components ; Apparatus not specifically provided for elsewhere
- H01L21/67005—Apparatus not specifically provided for elsewhere
- H01L21/67011—Apparatus for manufacture or treatment
- H01L21/67132—Apparatus for placing on an insulating substrate, e.g. tape
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
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- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2221/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof covered by H01L21/00
- H01L2221/67—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere
- H01L2221/683—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping
- H01L2221/68304—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support
- H01L2221/68327—Apparatus for handling semiconductor or electric solid state devices during manufacture or treatment thereof; Apparatus for handling wafers during manufacture or treatment of semiconductor or electric solid state devices or components; Apparatus not specifically provided for elsewhere for supporting or gripping using temporarily an auxiliary support used during dicing or grinding
Landscapes
- Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Manufacturing & Machinery (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Dicing (AREA)
- Drying Of Semiconductors (AREA)
Description
1259555 (1) 玖、發明說明 【發明所屬之技術領域】 本發明是關於一種藉由化學式蝕刻處理來分割半導體 晶圓而作成各個晶片的半導體晶圓之分割方法。 【先前技術】 表示於第1 2圖的半導體晶圓W,是經由保持膠帶T 而與框架F成爲一體。在半導體晶圓W的表面,隔著一 定間隔而柵狀地排列有界道S,在藉由界道S被區劃的多 數矩形領域形成有電路。又,使用旋轉刀片來切削界道S ,則成爲各個半導體晶片C。 然而,在藉由旋轉刀片的切削,細小缺口或應力會發 生在半導體晶片的外周之故,因而該缺口或應力成爲原因 使得抗折強度降低,藉由外力或加熱周期而使半導體晶片 容易破損,有縮短壽命之問題。尤其是,在如厚度5 Ο β m以下的半導體晶片,上述缺口或應力是成爲致命性問題 〇 如此,檢討不使用旋轉刀片,藉由化學式蝕刻處理進 行分割半導體晶圓的方法。該方法,是首先在形成有電路 的半導體晶圓W表面黏貼膠帶構件而加被覆,使用遮光 罩曝光界道之僅上部,除去藉由曝光而變質的膠帶構件, 又藉由蝕刻俾浸蝕界道而分割成各個半導體晶片的方法。 然而,在上述方法中,爲了僅曝光黏貼於界道上部的 膠帶構件,必須準備個別地對應於半導體晶圓W的大小 -5- (2) (2)1259555 及界道間隔的複數種類遮光罩之故,因而有不經濟之同時 有管理上成爲煩雜的問題。 又,需要進行形成於半導體晶圓W的表面的界道S 與對應於此而形成在遮光罩的對應部分的精密對位並進行 曝光的曝光裝置,及用以除去藉由曝光被變質的膠帶構件 的除去裝置之故,因而也有設備投資增大的問題。 又,在半導體晶圓W的界道S以蝕刻處理無法除去 的材質形成有對準標記等累層體時,也有實質上無法分割 半導體晶圓W的問題。 一方面,以光抗鈾劑膜被覆半導體晶圓,如揭示於日 本特開200 1 — 1 270 1 1號公報的發明,也提案一種使用旋 轉刀片等機械式地除去被覆界道上部的光抗蝕劑膜之後, 經由化學式蝕刻俾分割成半導體晶片的方法。 但是,利用此種方法時,很難將被覆的光抗蝕劑膜的 厚度成爲均勻,同時無法形成較厚的光抗蝕劑膜之故,因 而在蝕刻會蝕刻止光抗蝕劑膜,有被分割之前光抗鈾劑膜 變成沒有的問題。 因此,在藉由化學式蝕刻處理俾分割半導體晶圓時, 藉由經濟性且確實的方法,欲形成沒有缺口或應力的高品 質半導體晶片上具有課題。 【發明內容】 本發明的半導體晶圓之分割方法,屬於每一個電路的 半導體晶片地分割電路形成在藉由界道所區劃的多數領域 -6 - (4) (4)1259555 乾蝕刻處理並不需太多時間。 又,在鈾刻處理無法除去的材質的圖案等累層體形成 於界道的半導體晶圓時,藉由將旋轉刀片切入數β m,除 去該累層體而可露出矽等所形成的半導體基板。 【實施方式】 作爲本發明的實施形態一例,說明表示於第1圖的半 導體晶圓W的方法。第1圖的半導體晶圓W,是以電路 面(表面)爲上面黏貼在能堵住框架F的開口部地從背側 黏貼的保持膠帶T的黏接面,經由保持膠帶T與框架F 成爲一體而被支持。 在該半導體晶圓W,如第1圖所示地,黏貼被覆半導 體晶圓W整體表面的膠帶構件1 0,如第2圖及第3圖所 示地,與半導體晶圓W成爲一體(被覆工序)。在圖示 例,膠帶構件1 〇是透明,惟半透明也可以。膠帶構件1〇 是抗蝕劑膠帶(形成所定厚度的片),惟一般使用作爲保 持膠帶的黏接膠帶也可以,或是將黏接劑塗布於聚對-酞 酸乙二酯(PET )等薄膜者也可以。 如第2圖及第3圖地黏貼有膠帶構件10的半導體晶 圓W,是在經由保持膠帶T而與框架F成爲一體的狀態 下,被搬運至如表示於第4圖的切割裝置2 0,而被收容 複數在晶圓匣盒2 1。 然後,半導體晶圓W藉由搬出入手段22 一個一個地 取出在暫時置放置領域2 3,並吸附在搬運手段24被搬運 -8- (5) 1259555 至夾盤台2 5並被保持。 之後,藉由夾盤台25朝+ X方向移動,使得半導體 晶圓W首先位在對準手段2 6的正下方,在此被檢測界道 ,進行該界道與構成切削手段27的旋轉刀片28的Y軸 方向的對位。又,在第2圖中膠帶構件1 0是透明,惟在 半透明時,則使用紅外線進行對位,即可透過膠帶構件 1 0而檢測界道。 如此地進行對位,則夾盤台2 5藉由再朝+ X方向移 動,同時一面旋轉刀片28高達旋轉一面切削手段27下降 ,使高速旋轉的旋轉刀片2 8切進所檢測的界道上部的膠 帶構件1 0。 如上所進行的切削,是朝X軸方向往復移動夾盤台 2 5,同時每一次界道間隔地一面朝Υ軸方向送出切削手 段2 7 —面進行切削,則如第5圖所示地,在相同方向的 所有界道上部形成切削溝1 1。 又,旋轉90度夾盤台25之後,與上述同樣地進行切 削,則如第6圖所示,切削溝1 1縱橫地形成在所有界道 上部的膠帶構件1 〇 (膠帶構件除去工序)。如此地,可 切削並除去界道上的膠帶構件1 〇之故,因而不必使用如 習知的遮光罩或曝光裝置等。 又,在膠帶構件除去工序中,若在旋轉刀片28的切 入量發生誤差時,則成爲有些切進半導體晶圓 W的界道 之情形,而發生一些缺口或應力,惟此些缺口或應力,是 藉由後續的分割工序的化學性蝕刻處理可加以除去之故, -9- (6) 1259555 因而不會成爲問題。 對於所有半導體晶圓完成遮光構件除去工序,則每一 晶圓匣盒2 1地搬運至下一分割工序。在分割工序中,使 用如第7圖所示的乾蝕刻裝置3 0。又,藉由濕鈾刻也可 進行分割工序。 表示於第7圖的乾蝕刻裝置3 0是由··進行來自從切 割裝置2 0所搬運的晶圓匣盒2 1的半導體晶圓w的搬出 及完成分割工序後的半導體晶圓W搬入至晶圓匣盒2 1的 搬出入手段31,及收容有藉由搬出入手段31被搬出入的 半導體晶圓W的搬出入處理室3 2,及進行乾蝕刻的處理 室3 3,及將鈾刻氣體供給於處理室3 3內的氣體供給部3 4 所構成。 完成膠帶構件除去工序的半導體晶圓W,是藉由搬出 入手段3 1從晶圓匣盒2 1被搬出。之後,打開具備於搬出 入處理室3 2的第一閘門3 5,半導體晶圓W載置於位在表 示於第8圖的搬出入處理室3 2內的保持部3 6。 如第8圖所示,搬出入處理室32與處理室33是藉由 第二閘門3 7被遮斷,惟打開第二閘門3 7時,保持部3 6 成爲可移動在搬出入處理室3 2內部與處理室3 3內部之間 〇 如第9圖所示地,在處理室3 3,朝上下方向相對地 配設有被連接於高頻電源及調諧機3 8而發生電漿的一對 高頻電極3 9,在本實施形態中,一方的高頻電極3 9成爲 兼具保持部3 6的構成。又,在保持部3 6設置冷却半導體 -10- (7) 1259555 晶圓的冷却部40。 另一方面,在氣體供給部3 4具備:儲存鈾刻氣體的 氣體槽4 1,及將被儲存在氣體槽4 1的鈾刻氣體供給於處 理室3 3的泵4 2,同時具備:將冷却水供給於冷却部4 0 的冷却水循環器43,將吸引力供給於保持部3 6的吸引泵 44,吸引處理室33內的鈾刻氣體的吸引泵45,中和吸引 泵4 5所吸引的鈾刻氣體並排出至排出部4 7的過濾器4 6 〇 擬乾蝕刻完成膠帶構件除去工序的半導體晶圓W之 際,打開設在搬出入處理室3 2的第一閘門3 5,藉由搬出 入手段3 1保持半導體晶圓W而朝第8圖的箭號方向移動 ,半導體晶圓W以表面爲上面載置在位於搬出入處理室 3 2內的保持部3 6。之後’關閉第一閘門3 5,俾將搬出入 處理室32內成爲真空。 之後,打開第二閘門3 7,藉由保持部3 6移動至處理 室3 3內,使得半導體晶圓W被收容在處理室3 3內。在 處理室3 3內,藉由泵4 2供給例如稀薄的氟系氣體的蝕刻 氣體,同時將高頻電壓從高頻電源及調諧器3 8供給於高 頻電極3 9,而藉由電漿乾鈾刻半導體晶圓W的表面。這 時候,在冷却部4 0藉由冷却水循環器4 3供給冷却水。 如此地進行乾蝕刻,則半導體晶圓W的表面中黏貼 在界道上部的膠帶構件1 0是在膠帶構件除去工序中被除 去,惟其他部分是以膠帶構件1 0所覆蓋之故,因而膠帶 構件1 0成爲遮光構件’界道藉由蝕刻處理被浸蝕,如第 -11 - (8) (8)1259555 1 〇圖所示地,被分割成各個半導體晶片C (分割工序)。 又,膠帶構件1 〇是藉由上述分割工序的乾鈾刻被浸 蝕的材質也可以,或不被浸鈾的材質也可以。若爲被浸鈾 的材質時,則對應於所浸鈾的半導體晶圓的界道深度來決 定膠帶構件的厚度,就不會傷及半導體晶圓W的表面。 亦即,界道S被浸蝕而被分割成半導體晶片C時,在半 導體晶片C上部留著膠帶構件10就可以。另一方面,藉 由乾蝕刻不會被浸蝕的材質時,則不考慮半導體晶圓的浸 蝕深度就可決定厚度。 完成蝕刻之後,藉由吸引泵4 5吸引被供給於處理室 3 3的鈾刻氣體,而在過濾器46進行中和後從排出部47 排出至外部。之後,將處理室3 3內成爲真空後打開第二 閘門3 7,使得保持已經蝕刻的半導體晶圓W的保持部3 6 移動至搬出入處理室3 2,關閉第二閘門3 7。 半導體晶圓W移動至搬出入處理室3 2,則打開第一 閘門3 5,使得搬出入手段3 1保持半導體晶圓W並從搬出 入處理室3 2搬出,被收容在晶圓匣盒2 1。 對於所有半導體晶圓進行如上述的工序,藉由化學性 蝕刻處理被分割成半導體晶片C,而藉由膠帶構件1 0以 維持半導體晶圓W的外形狀態被收容在晶圓匣盒2 1。 之後’錯由剝離黏貼在各個半導體晶片C表面的膠帶 構件1 0,如第1 1圖所示地,成爲各個半導體晶片c。 如此所形成的各該半導體晶片C,是並不是使用旋轉 刀片而利用切削所分割者,而是藉由化學性蝕刻處理所分 -12- 1259555 Ο) 割者之故,因而成爲沒有缺口或應力的高品質者。尤其是 ’厚度如5 0 // m以下的薄半導體晶圓時,藉由切削所分 割的方法,則容易產生缺口或應力之故,因而若利用本發 明時特別有效果。 又,在蝕刻處理無法除去的圖案等累層體形成於界道 時’則在膠帶構件除去工序中將旋轉刀片2 8切進至該被 覆層,就可除去該被覆層之故,因而藉由鈾刻也可分割形 成有此種累層體的半導體晶圓。 (發明的效果) 如上所述地,依照本發明的半導體晶圓之分割方法, 在半導體晶圓之電路面黏貼膠帶構件,利用切削除去界道 上的膠帶構件之後,藉由化學性蝕刻界道,分割成各個半 導體晶片之故,因而不使用遮光罩或曝光裝置等,可形成 沒有缺口等的高抗折強度的半導體晶片,可提高半導體晶 片之品質。尤其是在如厚度5 0 // m以下的薄半導體晶圓 時,若依切割並分割的方法,則容易產生缺口或應力,惟 依照化學性蝕刻,就不容易產生缺口或應力,具有效果。 又’半導體晶圓是使用切割裝置分割成各個半導體晶 片成爲主流,而在半導體製造廠商已備有分割裝置之故, 因而實施本發明並不需要大規模的設備投資,具有經濟性 〇 又’化學性蝕刻處理,是半導體晶圓的厚度愈厚會成 爲愈費時,惟如厚度5 0 // m以下的薄半導體晶圓,則在 -13- (10) 1259555 乾鈾刻處理並不需太多時間之故,因而可確保生產性。 又,在蝕刻處理無法除去的材質的累層體形成於界道 的半導體晶圓時,藉由將旋轉刀片切入數// m,除去該累 層體而可露出矽等所形成的半導體基板之故,因而即使爲 此種半導體晶圓,也可藉由化學性蝕刻進行分割。 又,如習知地,藉由光抗蝕劑膜被覆半導體晶圓表面 時,則光抗蝕劑膜的厚度不會成爲均勻,又,光抗蝕劑膜 是無法具有厚度之故,因而藉由化學性蝕刻使得光抗蝕劑 膜被蝕刻,而半導體晶圓被分割之前,會成爲沒有被覆 之問題,惟作爲被覆使用膠帶構件,並利用切削就能除去 界道上部的膠帶構件之故,因而在被覆上可確保充分厚度 ,而可解決上述缺點問題,可確實地分割半導體晶圓。 【圖式簡單說明】 第1圖是表示構成本發明的被覆工序的立體圖。 第2圖是表示膠帶構件黏貼於半導體晶圓的狀態的ίζ: 體圖。 第3圖是表示膠帶構件黏貼於半導體晶圓的狀態的前 視圖。 第4圖是表示使用於構成本發明的膠帶構件除去1序 的切割裝置的一例的立體圖。 第5圖是表示切削溝形成於界道上部的膠帶構件的狀 態的前視圖。 第6圖是表示黏貼有該切削溝縱橫地形成的膠帶構件 -14- (11) (11)1259555 的半導體晶圓的立體圖。 第7圖是表示使用於分割工序的乾蝕刻裝置的一例的 立體圖。 第8圖是表不該乾蝕刻裝置的搬出入處理室及處理室 的剖視圖。 第9圖是表示該乾蝕刻裝置的處理室及氣體供給部的 構成的說明圖。 第1 〇圖是表示剛完成分割工序之後的半導體晶圓及 膠帶構件的前視圖。 第1 1圖是表示剝離膠帶構件的半導體晶片的前視圖 〇 第1 2圖是表示經由保持膠帶與框架成爲一體的半導 體晶圓的俯視圖。 【主要元件對照表】 10 膠 帶 構 件 11 切 削 溝 20 分 割 裝 置 21 晶 圓 匣 盒 22 搬 出 入 手 段 23 暫 時 置 放 領域 24 搬 運 手 段 25 夾 t^rru 盤 台 26 對 準 手 段 -15- (12)1259555 27 切削手段 28 旋轉刀片 3 0 乾鈾刻裝置 3 1 搬出入手段 3 2 搬出入處理室 ο 處理室 34 氣體供給部 3 5 閘門 3 6 保持部 3 7 第二閘門 3 8 高頻電源及調諧機 3 9 高頻電極 40 冷却部 4 1 氣體槽 42 泵 43 冷却水循環器 44、4 5 吸弓[栗 46 過濾器 47 排出部 W 半導體晶圓 s 界道 c 半導體晶片 T 保持膠帶 F 框架 -16-
Claims (1)
1259555 拾、申請專利範圍 第9 2 1 03690號專利申請案 中文申請專利範圍修正本 民國95年3月1〇日修正 1 . 一種半導體晶圓之分割方法,屬於每一個電路的 半導體晶片地分割電路形成在藉由界道所區劃的多數領域 的半導體晶圓的半導體晶圓之分割方法,其特徵爲至少由 以膠帶構件被覆該半導體晶圓的電路面的被覆工序; 切割被覆該界道上部的膠帶構件並除去的膠帶構件除 去工序;及 在被覆該界道上部的膠帶構件被除去的半導體晶圓施 以化學性鈾刻處理,俾浸蝕界道而分割成各個半導體晶片 的分割工序,所構成。 2 ·如申請專利範圍第1項所述的半導體晶圓之分割方 法,其中,膠帶構件的厚度是依據浸蝕分割工序的半導體 晶圓的深度被決定。 3. 如申請專利範圍第1或第2項所述的半導體晶圓之 分割方法,其中,欲分割在界道上形成有藉由化學性蝕刻 處理無法除去的累層體的半導體晶圓時,藉由分割除去累 層體。 4. 如申請專利範圍第1項所述的半導體晶圓之分割方 法,其中,化學性蝕刻處理是乾蝕刻處理。
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-
2002
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US6803247B2 (en) | 2004-10-12 |
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CN1515026A (zh) | 2004-07-21 |
TW200303601A (en) | 2003-09-01 |
WO2003073488A1 (fr) | 2003-09-04 |
DE10391810T5 (de) | 2005-05-19 |
JP2003257896A (ja) | 2003-09-12 |
AU2003248339A1 (en) | 2003-09-09 |
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