TWI258814B - Electropolishing metal layers on wafers having trenches or vias with dummy structures - Google Patents

Electropolishing metal layers on wafers having trenches or vias with dummy structures Download PDF

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Publication number
TWI258814B
TWI258814B TW091107631A TW91107631A TWI258814B TW I258814 B TWI258814 B TW I258814B TW 091107631 A TW091107631 A TW 091107631A TW 91107631 A TW91107631 A TW 91107631A TW I258814 B TWI258814 B TW I258814B
Authority
TW
Taiwan
Prior art keywords
metal layer
layer
recessed
recessed area
dielectric
Prior art date
Application number
TW091107631A
Other languages
English (en)
Chinese (zh)
Inventor
Hui Wang
Peihaur Yih
Original Assignee
Acm Res Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Acm Res Inc filed Critical Acm Res Inc
Application granted granted Critical
Publication of TWI258814B publication Critical patent/TWI258814B/zh

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
    • H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/48—After-treatment of electroplated surfaces
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D5/00—Electroplating characterised by the process; Pretreatment or after-treatment of workpieces
    • C25D5/02—Electroplating of selected surface areas
    • C—CHEMISTRY; METALLURGY
    • C25—ELECTROLYTIC OR ELECTROPHORETIC PROCESSES; APPARATUS THEREFOR
    • C25D—PROCESSES FOR THE ELECTROLYTIC OR ELECTROPHORETIC PRODUCTION OF COATINGS; ELECTROFORMING; APPARATUS THEREFOR
    • C25D7/00—Electroplating characterised by the article coated
    • C25D7/12—Semiconductors
    • C25D7/123—Semiconductors first coated with a seed layer or a conductive layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H01L21/321—After treatment
    • H01L21/32115—Planarisation
    • H01L21/3212—Planarisation by chemical mechanical polishing [CMP]
    • H01L21/32125—Planarisation by chemical mechanical polishing [CMP] by simultaneously passing an electrical current, i.e. electrochemical mechanical polishing, e.g. ECMP
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76838—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the conductors
    • H01L21/7684—Smoothing; Planarisation

Landscapes

  • Engineering & Computer Science (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Electrochemistry (AREA)
  • Materials Engineering (AREA)
  • Organic Chemistry (AREA)
  • Metallurgy (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
TW091107631A 2001-04-24 2002-04-15 Electropolishing metal layers on wafers having trenches or vias with dummy structures TWI258814B (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US28627301P 2001-04-24 2001-04-24
US10/108,614 US6638863B2 (en) 2001-04-24 2002-03-27 Electropolishing metal layers on wafers having trenches or vias with dummy structures

Publications (1)

Publication Number Publication Date
TWI258814B true TWI258814B (en) 2006-07-21

Family

ID=26806086

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091107631A TWI258814B (en) 2001-04-24 2002-04-15 Electropolishing metal layers on wafers having trenches or vias with dummy structures

Country Status (7)

Country Link
US (2) US6638863B2 (enExample)
EP (1) EP1382065A4 (enExample)
JP (1) JP2004527126A (enExample)
KR (1) KR101018187B1 (enExample)
CN (1) CN100541746C (enExample)
TW (1) TWI258814B (enExample)
WO (1) WO2002086961A1 (enExample)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8791778B2 (en) 2009-04-20 2014-07-29 International Business Machines Corporation Vertical integrated circuit switches, design structure and methods of fabricating same
TWI872007B (zh) * 2024-07-05 2025-02-01 南亞科技股份有限公司 晶圓的加工方法

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JP5412517B2 (ja) * 2008-08-20 2014-02-12 エーシーエム リサーチ （シャンハイ） インコーポレーテッド バリア層除去方法及び装置
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* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8791778B2 (en) 2009-04-20 2014-07-29 International Business Machines Corporation Vertical integrated circuit switches, design structure and methods of fabricating same
TWI472475B (zh) * 2009-04-20 2015-02-11 萬國商業機器公司 垂直積體電路切換器、設計結構及其製造方法
TWI872007B (zh) * 2024-07-05 2025-02-01 南亞科技股份有限公司 晶圓的加工方法

Also Published As

Publication number Publication date
CN100541746C (zh) 2009-09-16
JP2004527126A (ja) 2004-09-02
EP1382065A4 (en) 2009-04-15
KR101018187B1 (ko) 2011-02-28
KR20030093327A (ko) 2003-12-06
US20040080053A1 (en) 2004-04-29
US20020175419A1 (en) 2002-11-28
US6638863B2 (en) 2003-10-28
CN1663036A (zh) 2005-08-31
WO2002086961A1 (en) 2002-10-31
EP1382065A1 (en) 2004-01-21

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