TWI255525B - Method of bonding and transferring a material to form a semiconductor device - Google Patents

Method of bonding and transferring a material to form a semiconductor device Download PDF

Info

Publication number
TWI255525B
TWI255525B TW091136258A TW91136258A TWI255525B TW I255525 B TWI255525 B TW I255525B TW 091136258 A TW091136258 A TW 091136258A TW 91136258 A TW91136258 A TW 91136258A TW I255525 B TWI255525 B TW I255525B
Authority
TW
Taiwan
Prior art keywords
substrate
donor
receiving
semiconductor
receiving substrate
Prior art date
Application number
TW091136258A
Other languages
English (en)
Chinese (zh)
Other versions
TW200302548A (en
Inventor
Robert E Jones
Sebastian Csutak
Original Assignee
Freescale Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Freescale Semiconductor Inc filed Critical Freescale Semiconductor Inc
Publication of TW200302548A publication Critical patent/TW200302548A/zh
Application granted granted Critical
Publication of TWI255525B publication Critical patent/TWI255525B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • H01L21/76254—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques with separation/delamination along an ion implanted layer, e.g. Smart-cut, Unibond

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Element Separation (AREA)
  • Light Receiving Elements (AREA)
TW091136258A 2001-12-17 2002-12-16 Method of bonding and transferring a material to form a semiconductor device TWI255525B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US10/022,711 US6616854B2 (en) 2001-12-17 2001-12-17 Method of bonding and transferring a material to form a semiconductor device

Publications (2)

Publication Number Publication Date
TW200302548A TW200302548A (en) 2003-08-01
TWI255525B true TWI255525B (en) 2006-05-21

Family

ID=21811041

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091136258A TWI255525B (en) 2001-12-17 2002-12-16 Method of bonding and transferring a material to form a semiconductor device

Country Status (8)

Country Link
US (1) US6616854B2 (enExample)
EP (1) EP1500132A2 (enExample)
JP (1) JP4554930B2 (enExample)
KR (1) KR20040079916A (enExample)
CN (1) CN1324674C (enExample)
AU (1) AU2002353020A1 (enExample)
TW (1) TWI255525B (enExample)
WO (1) WO2003052817A2 (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7078320B2 (en) * 2004-08-10 2006-07-18 International Business Machines Corporation Partial wafer bonding and dicing
US7288458B2 (en) * 2005-12-14 2007-10-30 Freescale Semiconductor, Inc. SOI active layer with different surface orientation
KR100755368B1 (ko) * 2006-01-10 2007-09-04 삼성전자주식회사 3차원 구조를 갖는 반도체 소자의 제조 방법들 및 그에의해 제조된 반도체 소자들
US7682930B2 (en) * 2006-06-09 2010-03-23 Aptina Imaging Corporation Method of forming elevated photosensor and resulting structure
US7432174B1 (en) * 2007-03-30 2008-10-07 Advanced Micro Devices, Inc. Methods for fabricating semiconductor substrates with silicon regions having differential crystallographic orientations
EP1993126B1 (en) * 2007-05-18 2011-09-21 Semiconductor Energy Laboratory Co., Ltd. Manufacturing methods of semiconductor substrate
US8201325B2 (en) 2007-11-22 2012-06-19 International Business Machines Corporation Method for producing an integrated device
US7842583B2 (en) * 2007-12-27 2010-11-30 Semiconductor Energy Laboratory Co., Ltd. Method for manufacturing semiconductor substrate and method for manufacturing semiconductor device
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
GB0914251D0 (en) * 2009-08-14 2009-09-30 Nat Univ Ireland Cork A hybrid substrate
KR101807777B1 (ko) * 2010-03-31 2017-12-11 소이텍 본딩된 반도체 구조들 및 이를 형성하는 방법
FR2965974B1 (fr) * 2010-10-12 2013-11-29 Soitec Silicon On Insulator Procédé de collage moléculaire de substrats en silicium et en verre
US8778737B2 (en) 2011-10-31 2014-07-15 International Business Machines Corporation Flattened substrate surface for substrate bonding
US9190379B2 (en) 2012-09-27 2015-11-17 Apple Inc. Perimeter trench sensor array package
US9209142B1 (en) * 2014-09-05 2015-12-08 Skorpios Technologies, Inc. Semiconductor bonding with compliant resin and utilizing hydrogen implantation for transfer-wafer removal
WO2017052646A1 (en) * 2015-09-25 2017-03-30 Intel Corporation Island transfer for optical, piezo and rf applications

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4966646A (en) 1986-09-24 1990-10-30 Board Of Trustees Of Leland Stanford University Method of making an integrated, microminiature electric-to-fluidic valve
US5389569A (en) * 1992-03-03 1995-02-14 Motorola, Inc. Vertical and lateral isolation for a semiconductor device
JP3114570B2 (ja) * 1995-05-26 2000-12-04 オムロン株式会社 静電容量型圧力センサ
JPH09127352A (ja) * 1995-10-30 1997-05-16 Hitachi Ltd 半導体装置およびその製造方法
JP3257624B2 (ja) * 1996-11-15 2002-02-18 キヤノン株式会社 半導体部材の製造方法
US6191007B1 (en) 1997-04-28 2001-02-20 Denso Corporation Method for manufacturing a semiconductor substrate
JPH1140823A (ja) * 1997-05-22 1999-02-12 Fujitsu Ltd 光検出器モジュール
JPH1145862A (ja) * 1997-07-24 1999-02-16 Denso Corp 半導体基板の製造方法
US6271101B1 (en) * 1998-07-29 2001-08-07 Semiconductor Energy Laboratory Co., Ltd. Process for production of SOI substrate and process for production of semiconductor device
US6093623A (en) 1998-08-04 2000-07-25 Micron Technology, Inc. Methods for making silicon-on-insulator structures
JP4313874B2 (ja) * 1999-02-02 2009-08-12 キヤノン株式会社 基板の製造方法
JP2001007362A (ja) * 1999-06-17 2001-01-12 Canon Inc 半導体基材および太陽電池の製造方法
JP2001102523A (ja) * 1999-09-28 2001-04-13 Sony Corp 薄膜デバイスおよびその製造方法
US6400009B1 (en) * 1999-10-15 2002-06-04 Lucent Technologies Inc. Hermatic firewall for MEMS packaging in flip-chip bonded geometry

Also Published As

Publication number Publication date
WO2003052817B1 (en) 2003-09-25
US6616854B2 (en) 2003-09-09
JP2005513781A (ja) 2005-05-12
EP1500132A2 (en) 2005-01-26
CN1324674C (zh) 2007-07-04
US20030114001A1 (en) 2003-06-19
CN1615543A (zh) 2005-05-11
WO2003052817A2 (en) 2003-06-26
AU2002353020A1 (en) 2003-06-30
JP4554930B2 (ja) 2010-09-29
WO2003052817A3 (en) 2003-08-21
AU2002353020A8 (en) 2003-06-30
TW200302548A (en) 2003-08-01
KR20040079916A (ko) 2004-09-16

Similar Documents

Publication Publication Date Title
TWI255525B (en) Method of bonding and transferring a material to form a semiconductor device
TW563248B (en) A demountable substrate of controlled mechanical strength and a method of production
US9922956B2 (en) Microelectromechanical system (MEMS) bond release structure and method of wafer transfer for three-dimensional integrated circuit (3D IC) integration
US10128142B2 (en) Semiconductor structures including carrier wafers and attached device wafers, and methods of forming such semiconductor structures
CN100358124C (zh) 用于同时得到一对由有用层覆盖的衬底的方法
TWI303474B (en) A wafer and a die having an integrated circuit and a layer of diamond
JP5462289B2 (ja) 熱膨張係数が局所的に適合するヘテロ構造の生成方法
CN103828036B (zh) 在3d集成处理中转移材料层的方法以及相关结构和装置
US7288458B2 (en) SOI active layer with different surface orientation
US20030077885A1 (en) Embrittled substrate and method for making same
TWI626713B (zh) 具有埋置介電層以防止銅擴散的ｓｏｉ晶圓
TWI241653B (en) SOI structure with recess resistant buried insulator and manufacture method thereof
CN102903610B (zh) 制造包括位于支撑衬底上的功能化层的半导体结构的工艺
TW201225220A (en) Method for manufacturing microelectronic device and integrated circuit to prevent metal pad damage in wafer level package
JP2001127149A (ja) 半導体装置およびその製造方法
CN102326230B (zh) 形成集成电路的方法及所得结构
JP2004158705A (ja) 微細孔への金属充填方法及びその方法により形成された金属が充填した微細孔を備えたワーク
EP1296368A3 (en) Semiconductor device including porous insulating material and manufacturing method thereof
JP5497626B2 (ja) 複合基板を製造するための工程
JP2006012914A (ja) 集積回路チップの製造方法及び半導体装置
JP3216535B2 (ja) Ｓｏｉ基板およびその製造方法
TW201347033A (zh) 提供結晶半導體材料薄層之方法及相關結構與裝置
TW200831724A (en) Method and structure for cleaning surfaces for bonding layer transfer substrates
JPH0482250A (ja) 半導体装置の製造方法

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees