TWI253120B - Semiconductor device and method of manufacturing the same - Google Patents

Semiconductor device and method of manufacturing the same Download PDF

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Publication number
TWI253120B
TWI253120B TW093126852A TW93126852A TWI253120B TW I253120 B TWI253120 B TW I253120B TW 093126852 A TW093126852 A TW 093126852A TW 93126852 A TW93126852 A TW 93126852A TW I253120 B TWI253120 B TW I253120B
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TW
Taiwan
Prior art keywords
interlayer insulating
insulating film
low
elasticity
layer
Prior art date
Application number
TW093126852A
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English (en)
Other versions
TW200518228A (en
Inventor
Masazumi Matsuura
Hiroshi Horibe
Susumu Matsumoto
Tsuyoshi Hamatani
Original Assignee
Renesas Tech Corp
Matsushita Electric Ind Co Ltd
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Application filed by Renesas Tech Corp, Matsushita Electric Ind Co Ltd filed Critical Renesas Tech Corp
Publication of TW200518228A publication Critical patent/TW200518228A/zh
Application granted granted Critical
Publication of TWI253120B publication Critical patent/TWI253120B/zh

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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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Description

1253120 九 、 ，發 明 說 明 • 春 [ 發 明 所 屬 之 技 術 領 本 發 明 係 關 於 半 導 採 用 機 械 強 度 較 低 的 較 可 靠 性 金 屬 焊 墊 [ 先 前 技 術 ] 在 0 • 1 8微 米 以. 後1 化 降 低 裝 置 的 信 號 係 由 電 晶 體 的 信 號 延 朝 配 線 間 距 縮 小 方 向 配 線 延 遲 影 響 有 增 加 間 電 容 (C )之乘積（ Rx 層 間 絕 緣 膜 電 容 之 事 為 求 解 決 上 述 問 題 點 所 構 成 之 低 介 電 係 數 金 屬 焊 墊 與 其 周 邊 合 的 鋁 焊 墊 或 鋁 銅 合 形 成 之 焊 墊 N 與 由 穿 金 屬 焊. 勢與其周邊部 的 Tech n i ( :a 1 D i ges t C )f 域】 體裝置及其製造方法 低介電係數層間絕緣 的半導體裝置及其製 白勺糸統L S I中’為求 延遲乃屬重要一環。 遲與配線延遲的總和 前進，因電晶體的信 現象。配線延遲乃因^ C )成正比，因此降低 ，對降低配線延遲頗 ，已正熱烈探討著利 層間絕緣膜、與銅配 部，一般乃屬於最上 金焊墊，並在下層配 孔插塞所支撐的疊層 構造已有揭示[參閱Μ · 2002 IEDM ρρ· 77〜80,"
Copper and Low-K Interconnect Technology to 90nm-Node SOC App 1 ication(CM0S4)M ] ° 如上述，在最尖端的系統L S I方面，為，；( 正熱烈的探討著導入低介電係數層間絕緣 ，特別係關於在 膜的前提下，具 造方法。 達成裝置的高速 裝置的信號延遲 表示，隨急遽的 號延遲而所造成 I與電阻（R )及層 配線電阻或降低 為有效。所以， 用埋設配線構造 線的組合方式。 層為施行打線接 置著由銅配線所 構造。此特別的 Inohara et. a 1. High Performance Fully Compatible :降低配線延遲， 膜事宜。此低介 312XP/發明說明書(補件)/93_ 12/93126852 5 1253120 電A數材料可適用的例子，有如：氫倍半氧石夕烧（H y d r 〇 g e η
Silsesquioxane)、曱基倍半氧石夕烧（Methyl Silsesquioxane)、 聚芳香驗（Poly Arylether)、聚苯聚合物（Polyphenylene Polymer)、苯環丁稀（genz〇CyCi〇butene)、聚四氟乙稀 (Polytetrafluoroethylene)、或中孔洞氧化矽（Mesoporous
Si 1 ica)的乾凝膠（xerogel)、氣凝膠（Aer〇gel)等，利用旋轉塗布 法所形成的材料’或者如：加氟氧化矽膜（s i 〇F膜）、加氟非晶質 石厌膜（CF膜）、聚對二曱苯基（pary iene)、加碳氧化矽膜（Si〇c膜） 荨’利用CVD法（化學氣相沉積法：chemical Vapor Deposition) 所形成的材料。 上述材料在相較於截至目前所使用的氧化矽膜之下，機 械強度將變為非常脆弱。表1中乃氧化石夕膜、與代表性低 介電係數層間絕緣膜所採用S i 0 C膜的硬度與彈性率之比 較0 [表1] 硬度 彈性率 氧化矽膜（非低彈性率） 9(GPa) 70〜lOO(GPa) 加碳氧化矽膜（低彈性率） 2 ( G p a ) 13(GPa) 依照表1中得知，經降低介電係數的S i 0C膜之硬度與 彈性率’已較習知的氧化矽膜大幅降低。在後述說明中， 將此種硬度與彈性率的降低，統稱為「機械強度降低」。 引起上述層間絕緣膜之機械強度降低現象，當為進行打 線接合、裝置測試而施行探針（針觸）時，在金屬焊墊下層 所配置的層間絕緣膜中將產生龜裂現象，且打線接合將發 312XP/發明說明書(補件)/93-12/93126852 1253120 生接合不良的情況。因而已有多數提案指出提高金屬焊墊 與其周邊部的可靠性（例如參照：曰本專利特開 2 0 0 0 - 3 4 0 5 6 9 號公報、特開 2 0 0 0 - 1 8 3 1 0 4 號公報、特開 2 0 0 1 - 3 0 8 1 0 0 號公報）。 【發明内容】 但是，隨金屬焊墊尺寸的極小化，在搭線焊接時所施加 的衝擊畸變將提高，因而將要求缓和更大的畸變，且能防 止龜裂、脫膜的金屬焊墊下端構造。 本發明之目的在於提供一種可防止當使用機械強度較 低之低介電係數層間絕緣膜時，造成問題之在金屬焊墊下 層所發生的層間絕緣膜龜裂、接合不良現象的半導體裝置 及其製造方法。 本發明的半導體裝置係具備有：形成於半導體基板上， 且彈性率互異的複數種層間絕緣膜，及配置於複數種層間 絕緣膜上的金屬焊墊。所以，此半導體裝置係具備有：具有 互異彈性率中之最小彈性率，並在上述金屬焊墊下方設置 開口部的低彈性率層間絕緣膜；具有較低彈性率層間絕緣 膜之彈性率更大的彈性率，且沿開口部與其周圍區域，連 續疊層銜接低彈性率層間絕緣膜的非低彈性率層間絕緣 膜；以及在金屬焊墊下方，埋設低彈性率層間絕緣膜的開 口部，且配置銜接非低彈性率層間絕緣膜的金屬配線層。 依照上述構造的話，金屬焊墊下端將配置著非低彈性率 層間絕緣膜與金屬配線層，但並未配置低彈性率層間絕緣 膜。所以，在打線接合中，有發生龜裂現象之可能性的低 7 312XP/發明說明書(補件)/93-12/93126852 1253120 彈性率層間絕緣膜，並未正面承受打線接合的衝擊畸變， 而防止發生龜裂情況。而且，在金屬配線層與非低彈性率 層間絕緣膜間之界面所發生的畸變將被緩和，亦可確實防 止偏離金屬焊墊正下方位置的低彈性率層間絕緣膜，發生 膜剝落情況。 本發明的半導體裝置之製造方法，係具有與外部間執行 電耦接的金屬焊墊，並形成於半導體基板上者。此製造方 法係包含有：在半導體基板上方，形成具有彈性率較小於氧 化矽膜之低彈性率絕緣層的步驟；以及在低彈性率絕緣層 中，於形成金屬焊墊的該部位設置開口部的步驟。此外， 尚包含有：形成埋設開口部，且覆蓋低彈性率絕緣層之金屬 層的步驟；以及對金屬層施行化學機械研磨處理，而裸露 出低彈性率絕緣層與開口部金屬層的步驟。然後，更包含 有：經施行化學機械研磨處理之後，利用具有彈性率較大於 低彈性率絕緣膜之彈性率的絕緣層，覆蓋金屬層與低彈性 率絕緣層的步驟；以及在包含低彈性率絕緣層、金屬層及 非低彈性率絕緣層的疊層構造上方，設置金屬焊墊的步驟。 藉由上述方法，便可簡單的形成可靠性較高的金屬焊墊 構造。 本發明的上述目的、特徵、佈局及優點，參照所附圖式 並經由下述詳細說明之後，應可清楚明瞭。 【實施方式】 其次，採用圖式，針對本發明實施形態進行說明。 (實施形態1 ) 8 312XP/發明說明書(補件)/93-12/93126852 1253120 圖1所示係本發明實施形態1的半導體裝置之金屬焊墊 周邊構造圖。在本實施形態中，在含有矽基板1上所形成 電晶體等元件的底層絕緣層2上，形成具有為抑制配線電 容而所選定之低介電係數的第 1低介電係數層間絕緣膜 3。低介電係數的大略標準係相當於較氧化矽膜為低的介電 係數。因為氧化矽膜的介質常數為 4. 3，因此標準便設定 為具有介質常數較小於此值。在為降低配線電容方面，最 好較小於上述值的介質常數。例如，更低的低介電係數材 料最好為介質常數在3以下的材料。 因為上述第1低介電係數層間絕緣膜3係彈性率等機械 強度較低，因此亦可謂第1低彈性率的詹間絕緣膜。低彈 性率的大略標準乃彈性率低於氧化矽膜，具體的數值係指 彈性率低於 5 0 G P a。上述所謂「非低彈性率層間絕緣膜」 係依此而指具有彈性率5 0 G P a以上的層間絕緣膜。當彈性 率非常大的情況時，便指彈性率1 0 OGPa以上。在本說明中 當指「非低彈性率層間絕緣膜」的情況時，在無特別限制 的情況下，大多係指彈性率非常大者。彈性率係可利用如 奈米壓痕（nano-indentation)法[微小壓入試驗法 (micro-pushing testing method)]進行求取。 其次，對第1低介電係數層間絕緣膜3利用微影與乾式 蝕刻而形成所需的配線圖案溝（開口部）3 a，並在此開口部 3 a中形成第1銅配線4。雖未圖示，但是在第1銅配線4 中防止銅擴散於層間絕緣膜中的涵義下，配置著屬於阻障 金屬的钽或氮化钽。所以，第1銅配線4的下面與二側面 9 312XP/發明說明書(補件)/93-〗2/93126852 1253120 便由此阻障金屬所覆蓋。即便後述所說明的銅 特別限制的前提下，亦是利用阻障金屬覆蓋著 在本實施形態中，第1低介電係數層間絕緣 由電漿C V D法所形成的加碳氧化矽膜（S i 0 C膜 實施形態中所使用的銅配線係依下述順序進 先，在由滅鍍法所形成的组或氮化艇之阻障金 濺鍍法形成薄膜的銅。其次，在其上利用電鍍 的銅。換句話說，銅配線係由依濺鑛法所形成 與由電鍍法所形成厚膜的銅所構成。 然後，利用化學機械研磨法（C h e m i c a 1 Polishing: CMP)，去除不需要部分的銅與阻障 在於溝（開口部）3 a中形成第1銅配線4。銅配 具孔或空隙等的普通薄膜，亦可為内部排列著 換句話說，沿第1銅配線4其中部分的I I - I I矣 乃如圖2 A或圖2 B所示，可為完全的薄膜，亦 孔4a的薄膜。在此孔4a中埋設著位於與銅配 絕緣層3。換句話說，孔4a係被第1低介電係 膜3所埋設。 其次，形成介電係數與彈性率均高於第1低 間絕緣膜3的第1非低介電係數層間絕緣膜5 低介電係數層間絕緣膜6。在本說明中，將（第 數層間絕緣膜3 /第1非低介電係數層間絕緣膜 介電係數層間絕緣膜6 )，稱為第1層。 接著，在其上形成低介電係數的第2低介電 312XP/發明說明書(補件)/93-12/93126852 配線，在無 〇 膜3係採用 )。此外，本 行製作。首 屬上，利用 法形成厚膜 薄膜的銅、 Mechanical 金屬，最後 線4可為未 孔的薄膜。 I之切剖圖， 可為排列著 線4同層的 數層間絕緣 介電係數層 、與第2非 1低介電係 5 /第2非低 係數層間絕 10 1253120 緣膜7。其次，對第2低介電係數層間絕緣膜7利用微影 與乾式蝕刻，而形成所需配線圖案的溝（開口部）7 a。其次， 利用C Μ P處理等，在此開口部7 a中形成第2銅配線8。在 第2銅配線8上，形成第3非低介電係數層間絕緣膜9、 及第4非低介電係數層間絕緣膜1 0。由（第2低介電係數 層間絕緣膜7 /第3非低介電係數層間絕緣膜9 /第4非低介 電係數層間絕緣膜1 0 )構成第2層。 在本實施形態所使用的第1與第3非低介電係數層間絕 緣膜5、9，可適用由電漿CVD法所形成的氮化矽膜、碳化 矽膜、或加氮碳化矽膜、加氧碳化矽膜等。在本實施形態 中乃採用碳化矽膜。此外，第2與第4非低介電係數層間 絕緣膜6、1 0，乃同樣的使用由電漿C V D法所形成的氧化 矽膜。此氧化矽膜矽如表1所示，硬度與彈性率均較大於 本實施形態之低介電係數層間絕緣膜的S i 0 C膜，所以不易 因探針或打線接合而發生龜裂情況。 其次，依照如同第2層的相同方法，形成第3層與第4 層的層間絕緣膜與銅配線。最後，形成第5層的低介電係 數層間絕緣膜1 9、與銅配線2 0。 在依如上述所形成的5層銅配線之上，形成第1保護膜 2 1。其次，利用配置有耦接孔2 1 a的圖案，對第1保護膜 2 1施行蝕刻處理，俾使第5層銅配線2 0表面裸露出。 第1保護膜2 1可使用由電漿C V D法所形成的氮化矽膜、 氧化石夕膜、氮氧化石夕膜等。此外，在其上利用滅鍍法形成 鋁焊墊2 2，並將其表面利用第2保護膜2 3覆蓋。第2保 11 3 ] 2XP/發明說明書(補件)/93-12/93126852 1253120 護膜2 3亦可使用由電漿C V D法所形成的氮化矽膜、氧 膜、氮氧化矽膜等。第2保護膜2 3係利用所需圖案施 刻成可打線接合的狀態，而裸露出鋁焊墊2 2。最後， 焊墊上形成打線接合部24。 習知的金屬焊墊構造係將彈性率降低的低彈性率 絕緣膜，配置於金屬焊墊下方。因此，當對鋁焊墊朝 下方施加畸變之情況時，在彈性率差異頗大的銅配 S i 0 C膜間之界面、或氧化矽膜與S i 0 C膜間之界面， 生較大的畸變量。結果，在該等界面中所蓄積的内部明 將局部性的增大。此内部畸變的增大將促進界面處的 情況，結果，便將在膜内部發生龜裂或打線接合部接 良（剝落）情況。 本實施形態的半導體裝置構造，係在鋁焊墊正下方 著彈性率較高的氧化矽膜或銅配線（銅的彈性 1 3 0 G P a，與氧化矽膜相同大小），並未配置著彈性率較 層間絕緣膜。結果，在本實施形態中，藉由在鋁焊墊 方埋設著彈性率較高的氧化矽膜與銅配線，而減輕彈 差。所以，在打線接合、測試探針時施加給鋁焊墊正 的垂直方向畸變量將減輕，俾防止因打線接合或測試 而所發生的龜裂情況、或打線接合時的接合不良情況 在本實施形態中，雖在具有5層的配線層中全部插 配線，但是即便僅在其中部分的層中插入銅配線，仍 得相同的效果。此情況下，最好將銅配線插入於較靠 焊墊的配線層中。 312XP/發明說明書(補件)/93-12/93126852 化矽 行蝕 在鋁 層間 垂直 線與 將產 r變， 剝落 合不 配置 率約 低的 正下 性率 下方 探針 〇 入銅 可獲 近鋁 12 1253120 再者，在本實施形態中，在耦接孔 2 1 a的層 2 1中配置 著彈性率較高的氧化矽膜。此情況下，除鋁焊墊以外的部 分，例如就連聯繫各元件間的金屬配線（銅配線）所配置部 分處，亦在耦）接孔的層中配置著氧化碎膜。即便此情況下， 因為在金屬配線間配置著低介電係數層間絕緣膜，所以因 氧化矽膜的配置而所增力Π的S己線間電容僅些微而已。此 外，在極力降低配線間電容之目的下，亦可在除鋁焊墊以 外的金屬配線部分，亦在耦接孔的層中配置著低介電係數 層間絕緣膜。此情況下，便可在鋁焊墊正下方與其周圍部 分，選擇性的在搞接孔的層中配置著氧化石夕膜。 (實施形態2 ) 圖3所示係本發明實施形態2的半導體裝置之金屬焊墊 構造圖。本實施形態的層間絕緣膜與銅配線之形成方法， 乃因為完全如同實施形態1，所以便不再贅述。 不同於本發明實施形態1的部分，乃在於各層的銅配線 係由埋設位於其下方的耦接孔而形成。換句話說，在第 2 層中，第2銅配線8係由埋設耦接孔5 a、6 a而形成；在第 3層中，第3銅配線1 2係由埋設耦接孔9 a、1 0 a而形成； 此夕卜，在第4層中則有由埋設耦接孔1 3 a、1 4 a所形成的第 4銅配線1 6 ;在第5層中則有由埋設耦接孔1 7 a、1 8 a所形 成的第5銅配線2 0。上述耦接孔亦可僅稱「孔」。 沿圖3中的I V - I V線之切剖圖係如圖4 A或圖4 B所示。 銅配線可如圖4 A所示，埋設著離散的孔1 4 a，亦可如圖4 B 所示埋設著條紋狀的孔1 4 a。二者的情況均依「孔」表示。 13 312XP/發明說明書(補件)/93-12/93126852 1253120 在本實施形態中，因為追加由銅所形成的耦接孔部分， 因而在相較於實施形態1的情況下，鋁焊墊正下方機械強 度將變大。故，將可更徹底的減輕因打線接合或測試探針 所產生的畸變。結果，便可防止因打線接合或測試探針所 發生的龜裂情況、或打線接合中的接合不良情況。 (實施形態3 ) 圖5所示係本發明實施形態3的半導體裝置之金屬焊墊 構造圖。本實施形態的層間絕緣膜與銅配線之形成方法， 乃因為完全如同實施形態 1，所以便不再贅述。不同於實 施形態 1的部分乃在於：在各層的低彈性率層間絕緣膜中 所設置的開口部3 a、7 a、1 1 a、1 5 a、1 9 a中，所配置銅配 線4、8、12、16、20的平面尺寸並未統一。更具體而言， 朝上下方向交叉的變化各層銅配線的平面尺寸。配置平面 尺寸大於第1銅配線4的第2層銅配線。第3層與第5層 則如同第1層般的縮小，而在其間的第4層則為如同第2 層的相同大小。 在本實施形態中，藉由交叉變化所配置銅配線4、8、1 2、 1 6、2 0的平面尺寸，便可減輕銅配線周圍附近的畸變集中 情況。當統一銅配線平面尺寸並插入的情況時，上下方向 的銅配線端將對齊，在低介電係數層間絕緣膜所銜接銅配 線端周邊處的畸變集中將變大。藉由如本實施形態，將銅 配線端的位置交叉錯開，便可減輕畸變集中情況。 再者，在上述銅配線大小交叉改變的構造中，即便如實 施形態2中說明般，設置埋設耦接孔的銅配線，便可除本 14 312XP/發明說明書(補件)/93-12/93126852 1253120 實施形態的效果之外，尚獲得如同實施形態2中所獲得的 相同效果。 最後，包含上述本發明實施形態中所說明例子在内，羅 列本發明實施形態的例子。 上述非低彈性率層間絕緣膜亦可由第1非低彈性率層間 絕緣膜，與位於銜接其上面，且材質不同於第1非低彈性 率層間絕緣膜的第2非低彈性率層間絕緣膜所構成。 藉由重疊2片非低彈性率層間絕緣膜，便可利用此強度 較高的2片層間絕緣膜之界面減弱衝擊能量，俾防止從其 他的畸變集中部發生龜裂情況。 再者，如重複說明般，非低彈性率層間絕緣膜的介電係 數，係以較大於低彈性率層間絕緣膜的介電係數為前提。 亦可採取在上述金屬焊墊下的開口部之非低彈性率層 間絕緣膜中設置孔，並在此孔中埋設金屬配線層的構造。 銅等金屬配線乃屬於彈性率非常高，達lOOGpa左右以上， 藉由此金屬配線埋設孔並上下延長連續，便可達成優越的 機械強度。此外，亦可期待層間絕緣膜的孔側面、與金屬 配線間之界面的衝擊能量衰減等情況。 亦可採取在上述金屬配線層中設置著孔，且與此金屬配 線層相同層的低彈性率層間絕緣膜埋設著孔的構造。此情 況下，在疊層界面處便不致發生彈性率較大差異，可達成 優越的機械強度。此外，亦可期待減弱金屬配線的孔側面、 與層間絕緣膜間之界面處的衝擊能量等。 上述開口部中包含有非低彈性率層間絕緣膜、與開口部 15 312XP/發明說明書(補件)/93-12/93126852 1253120 埋設於金屬配線層中之低彈性率層間絕緣膜的疊層 可採取2層以上重疊的構造。依此藉由多疊層層構 可在與形成供達成半導體裝置原本功能用構造之多 間，取得整合性。此外，多疊層層構造的各界面， 在施行打線接合等之時所發生的衝擊能量亦具有效 當上述開口部中包含有非低彈性率層間絕緣膜、 部埋設於金屬配線層中之低彈性率層間絕緣膜的 造，形成重疊2層以上構造的情況時，上下相鄰接 金屬配線層可採取平面尺寸互異的構造。藉此構造 配線端的上下便不致對齊，可減輕當金屬配線端對 發生的畸變集中情況。 上述雖詳細說明本發明，惟該等僅止於例示而已 限定，應可清楚理解本發明僅由發明精神、與所附 利範圍所界定。 【圖式簡單說明】 圖1為本發明實施形態1的半導體裝置之金屬焊 造圖。 圖2 A與圖2 B為沿圖1之I I - I I線的切剖圖；B 無孔的金屬配線層；圖2B為排列著孔的金屬配線j 圖3為本發明實施形態2的半導體裝置之金屬焊 造圖。 圖4 A與圖4 B為沿圖3之I V - I V線的切剖圖；β 在離散的孔中埋設著金屬配線層的狀態；圖4Β為在 孔中埋設著金屬配線層的狀態。 312ΧΡ/發明說明書(補件)/93-12/93126852 構造， 造，便 數部分 對吸收 果。 與開口 疊層構 層内的 ，金屬 齊時所 ，並非 申請專 墊部構 I 2Α為 \ 〇 墊部構 丨4Α為 條紋狀 16 1253120 圖5為本發明實施形態3的半導體裝置之金屬焊墊部構 造圖。 【主要元件符號說明】 1 2 3、7、1 1、1 5、1 9 3a、 7a、 11a、 15a、 19a 4 、 8 、 12 、 16 、 20 4 a、 1 4 a 矽基板 底層絕緣層 第1低介電係數層間絕緣膜 開口部（溝） 銅配線
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5、6、9、1 0、1 3、1 4、1 7、1 8 非低介電係數層間絕緣膜 5a、 6a、 9a、 10a、 13a、 14a、柄接孑L 17a、 18a、 21a 21 22 23 24
第1保護膜 鋁焊墊 第2保護膜 打線接合部 17 312XP/發明說明書(補件)/93-12/93126852

Claims (1)

1253120 十、申請專利範圍： 1 . 一種半導體裝置，係具備有： 複數種層間絕緣膜，其形成於半導體基板上，且彈性率 互異； 金屬悍墊，其配置於上述複數種層間絕緣膜上； 低彈性率層間絕緣膜，其具有上述互異彈性率中之最小 彈性率，並在上述金屬焊墊下方設置開口部； 非低彈性率層間絕緣膜，其具有較上述低彈性率層間絕 緣膜之彈性率更大的彈性率，且沿上述開口部與其周圍區 域，連續疊層銜接上述低彈性率層間絕緣膜；以及 金屬配線層，其在上述金屬焊塾下方，埋設上述低彈性 率層間絕緣膜的開口部，且配置銜接上述非低彈性率層間 絕緣膜。 2 .如申請專利範圍第1項之半導體裝置，其中，上述非 低彈性率層間絕緣膜係包含第1非低彈性率層間絕緣膜、 及不同於上述第1非低彈性率層間絕緣膜之材質的第2非 低彈性率層間絕緣膜。 3 .如申請專利範圍第2項之半導體裝置，其中，在上述 金屬焊墊下方開口部的上述非低彈性率層間絕緣膜中設置 孔，並在該孔中埋設金屬配線層。 4 .如申請專利範圍第2項之半導體裝置，其中，上述開 口部中，含有非低彈性率層間絕緣膜、與開口部埋設於金 屬配線層中的低彈性率層間絕緣膜之疊層構造，係重疊2 層以上。 18 312XP/發明說明書(補件)/93-12/93126852 1253120 5 .如申請專利範圍第2項之半導體裝置，其中，上述開 口部中，含有非低彈性率層間絕緣膜、與開口部埋設於金 屬配線層中的低彈性率層間絕緣膜之疊層構造，係重疊2 層以上，且上下相鄰接層的上述金屬配線層係形成平面尺 寸互異。 6。如申請專利範圍第2項之半導體裝置，其中，上述金 屬配線層中設有孔，且與該金屬配線層相同層的上述低彈 性率層間絕緣膜係埋設於上述孔。 7 .如申請專利範圍第6項之半導體裝置，其中，上述開 口部中，含有非低彈性率層間絕緣膜、與開口部埋設於金 屬配線層中的低彈性率層間絕緣膜之疊層構造，係重疊2 層以上，且上下相鄰接層的上述金屬配線層係形成平面尺 寸互異。 8 .如申請專利範圍第1項之半導體裝置，其中，上述非 低彈性率層間絕緣膜的介電係數，係較大於上述低彈性率 層間絕緣膜的介電係數。 9 .如申請專利範圍第8項之半導體裝置，其中，上述開 口部中，含有非低彈性率層間絕緣膜、與開口部埋設於金 屬配線層中的低彈性率層間絕緣膜之疊層構造，係重疊2 層以上，且上下相鄰接層的上述金屬配線層係形成平面尺 寸互異。 1 0 . —種半導體裝置之製造方法，係具有與外部間執行 電耦接的金屬焊墊，並形成於半導體基板上者，其包含有： 在上述半導體基板上方，形成具有彈性率較小於氧化矽 19
312XP/發明說明書(補件)/93-12/93126852 1253120 膜之低彈性率絕緣層的步驟； 在上述低彈性率絕緣層中，於形成上述金屬焊墊的該部 位設置開口部的步驟； 形成埋設上述開口部，且覆蓋上述低彈性率絕緣層之金 屬層的步驟； 對上述金屬層施行化學機械研磨處理，而裸露出上述低 彈性率絕緣層與開口部金屬層的步驟；
經施行上述化學機械研磨處理之後，利用具有彈性率較 大於上述低彈性率絕緣膜之彈性率的絕緣層，覆蓋上述金 屬層與低彈性率絕緣層的步驟；以及 在包含上述低彈性率絕緣層、金屬層及非低彈性率絕緣 層的疊層構造上方，設置金屬焊墊的步驟。
20 3 12XP/發明說明書(補件)/93-12/93126852
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