KR100812731B1 - 조화된 응력을 갖는 상호 접속물들 및 그의 제조 방법 - Google Patents
조화된 응력을 갖는 상호 접속물들 및 그의 제조 방법 Download PDFInfo
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- KR100812731B1 KR100812731B1 KR1020060050793A KR20060050793A KR100812731B1 KR 100812731 B1 KR100812731 B1 KR 100812731B1 KR 1020060050793 A KR1020060050793 A KR 1020060050793A KR 20060050793 A KR20060050793 A KR 20060050793A KR 100812731 B1 KR100812731 B1 KR 100812731B1
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
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- H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
- H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
- H01L23/5329—Insulating materials
- H01L23/53295—Stacked insulating layers
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- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
- H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
- H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
- H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
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Abstract
Description
Claims (10)
- 상호 접속물을 형성하는 방법으로서,도전성 부재를 가진 기판을 제공하는 단계;상기 기판 위에 놓이는, 내부에 적어도 하나의 응력-조화층(stress-harmonizing layer)이 개재된 복합 로우-케이 유전체 층(low-k dielectric layer)을 형성하는 단계;상기 응력-조화층을 관통하고 상기 도전성 부재의 일부를 노출시키는 개구를 상기 복합 로우-케이 유전체 층에 형성하는 단계; 및상기 도전성 부재를 전기적으로 접속시키는 도전 피쳐(conductive feature)를 형성하기 위해 도전성 재료로 상기 개구를 충전하는 단계;를 포함하고,상기 도전성 부재의 제1 면은 상기 기판의 상면과 함께 노출되어 있고, 상기 도전성 부재의 상기 제1 면을 제외한 나머지 면은 상기 기판과 접촉되어 있는 것을 특징으로 하는, 상호 접속물 형성방법.
- 제 1 항에 있어서,내부에 적어도 하나의 응력-조화층이 개재된 상기 복합 로우-케이 유전체 층을 형성하는 단계는:(a) 상기 기판 위에 로우-케이 유전체의 제 1 층을 형성하는 단계;(b) 상기 로우-케이 유전체의 제 1층 위에 응력-조화층을 형성하는 단계; 및(c) 상기 응력-조화층 위에 로우-케이 유전체의 제 2 층을 형성하는 단계;를 포함하는, 상호 접속물 형성 방법.
- 제 2 항에 있어서,복수의 응력-조화층들이 개재된 복합 로우-케이 유전체 층을 형성하기 위해 적어도 한번 동안 상기 단계들 (a)-(c)를 반복하는 단계를 더 포함하는, 상호 접속물 형성 방법.
- 제 2 항에 있어서,제 1 및 제 2 로우-케이 유전체 층들은 인장 응력(tensile stress)을 포함하고 상기 제 1 응력-조화층은 압축 응력(compressive stress)을 포함하는, 상호 접속물 형성 방법.
- 제 2 항에 있어서,단계들 (a)-(c)는 플라즈마 강화 화학적 기상 증착(plasma-enhanced chemical vapor deposition)에 의해 본래의 장소에서 수행되는, 상호 접속물 형성 방법.
- 상호 접속물로서,도전성 부재를 가진 기판;상기 기판 위에 놓이는, 적어도 하나의 응력-조화층이 내부에 개재된 복합 로우-케이 유전체 층; 및상기 적어도 하나의 응력-조화층을 관통하고 상기 도전성 부재를 전기적으로 접속시키는, 상기 복합 로우-케이 유전체 층내의 도전 피쳐;를 포함하고,상기 도전성 부재의 제1 면은 상기 기판의 상면과 함께 노출되어 있고, 상기 도전성 부재의 상기 제1 면을 제외한 나머지 면은 상기 기판과 접촉되어 있는 것을 특징으로 하는, 상호 접속물.
- 제 6 항에 있어서,상기 복합 로우-케이 유전체 층은 압축 응력이 있는 적어도 하나의 응력-조화층이 삽입된 인장 응력이 있는 복수의 로우-케이 유전체 부분들을 포함하는, 상호 접속물.
- 제 7 항에 있어서,상기 도전 피쳐의 상면 위에 선택적으로 형성되는 도전캡(conductive cap)을 더 포함하는, 상호 접속물.
- 이중 다마신 구조물(dual damascene structure)로서,도전성 부재를 가진 기판;상기 기판 위에 놓이는 적어도 하나의 응력 조화층이 개재된 복합 로우-케이 유전체 층; 및상기 적어도 하나의 응력-조화층을 관통하고 상기 도전성 부재를 전기적으로 접속시키는, 상기 복합 로우-케이 유전체 층내의 도전 피쳐를 포함하고,상기 도전 피쳐는 하부 도전 비어(underlying conductive via) 및 그 위에 적층된 상부 도전 라인(overlying conductive line);을 포함하고,상기 도전성 부재의 제1 면은 상기 기판의 상면과 함께 노출되어 있고, 상기 도전성 부재의 상기 제1 면을 제외한 나머지 면은 상기 기판과 접촉되어 있는 것을 특징으로 하는, 이중 다마신 구조물.
- 제 9 항에 있어서,상기 복합 로우-케이 유전체 층은 압축 응력이 있는 적어도 하나의 응력-조화층이 개재된 인장 응력이 있는 복수의 로우-케이 유전체 부분들을 포함하는, 이중 다마신 구조물.
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US11/144,742 US7638859B2 (en) | 2005-06-06 | 2005-06-06 | Interconnects with harmonized stress and methods for fabricating the same |
US11/144,742 | 2005-06-06 |
Publications (2)
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KR20060127805A KR20060127805A (ko) | 2006-12-13 |
KR100812731B1 true KR100812731B1 (ko) | 2008-03-12 |
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KR1020060050793A KR100812731B1 (ko) | 2005-06-06 | 2006-06-07 | 조화된 응력을 갖는 상호 접속물들 및 그의 제조 방법 |
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US (1) | US7638859B2 (ko) |
JP (1) | JP2006344965A (ko) |
KR (1) | KR100812731B1 (ko) |
CN (1) | CN100403517C (ko) |
FR (1) | FR2887368B1 (ko) |
SG (1) | SG127856A1 (ko) |
TW (1) | TWI319217B (ko) |
Families Citing this family (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
TWI278265B (en) * | 2006-01-09 | 2007-04-01 | Phoenix Prec Technology Corp | Method for fabricating circuit board with electrically conducting structure and the same |
US20070205507A1 (en) * | 2006-03-01 | 2007-09-06 | Hui-Lin Chang | Carbon and nitrogen based cap materials for metal hard mask scheme |
US7488984B2 (en) * | 2006-04-19 | 2009-02-10 | Flx Micro, Inc. | Doping of SiC structures and methods associated with same |
US8178436B2 (en) * | 2006-12-21 | 2012-05-15 | Intel Corporation | Adhesion and electromigration performance at an interface between a dielectric and metal |
WO2010035481A1 (ja) * | 2008-09-26 | 2010-04-01 | ローム株式会社 | 半導体装置および半導体装置の製造方法 |
US9754822B1 (en) | 2016-03-02 | 2017-09-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Interconnect structure and method |
US10199500B2 (en) | 2016-08-02 | 2019-02-05 | Taiwan Semiconductor Manufacturing Company, Ltd. | Multi-layer film device and method |
TWI632677B (zh) * | 2017-06-09 | 2018-08-11 | 世界先進積體電路股份有限公司 | 半導體結構及其製造方法 |
US10276493B2 (en) * | 2017-08-01 | 2019-04-30 | Vanguard Enternational Semiconductor Corporation | Semiconductor structure and method for fabricating the same |
US10886465B2 (en) * | 2018-02-28 | 2021-01-05 | Taiwan Semiconductor Manufacturing Co., Ltd. | Resistive random access memory device |
US11495658B2 (en) * | 2018-06-08 | 2022-11-08 | Texas Instruments Incorporated | Hybrid high and low stress oxide embedded capacitor dielectric |
CN111640756B (zh) * | 2020-03-23 | 2022-05-31 | 福建省晋华集成电路有限公司 | 存储器及其形成方法 |
CN114743952A (zh) * | 2022-06-14 | 2022-07-12 | 合肥晶合集成电路股份有限公司 | 半导体结构及其制作方法 |
Citations (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10189577A (ja) | 1996-12-25 | 1998-07-21 | Canon Sales Co Inc | 層間絶縁膜の形成方法、半導体装置及びその製造方法 |
US6362091B1 (en) | 2000-03-14 | 2002-03-26 | Intel Corporation | Method for making a semiconductor device having a low-k dielectric layer |
US6764958B1 (en) | 2000-07-28 | 2004-07-20 | Applied Materials Inc. | Method of depositing dielectric films |
KR20040084668A (ko) * | 2003-03-25 | 2004-10-06 | 가부시끼가이샤 르네사스 테크놀로지 | 반도체 장치 및 그 제조 방법 |
Family Cites Families (24)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6100184A (en) * | 1997-08-20 | 2000-08-08 | Sematech, Inc. | Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer |
US6001730A (en) * | 1997-10-20 | 1999-12-14 | Motorola, Inc. | Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers |
JP3719878B2 (ja) * | 1999-06-15 | 2005-11-24 | 株式会社東芝 | 半導体装置及びその製造方法 |
TW447075B (en) | 2000-03-31 | 2001-07-21 | Taiwan Semiconductor Mfg | Method for forming dielectric layer with low dielectric constant |
US6358839B1 (en) * | 2000-05-26 | 2002-03-19 | Taiwan Semiconductor Manufacturing Company | Solution to black diamond film delamination problem |
JP4350337B2 (ja) * | 2001-04-27 | 2009-10-21 | 富士通マイクロエレクトロニクス株式会社 | 半導体装置 |
US20020197852A1 (en) * | 2001-06-21 | 2002-12-26 | Ming-Shi Yeh | Method of fabricating a barrier layer with high tensile strength |
JP2003209111A (ja) * | 2002-01-17 | 2003-07-25 | Sony Corp | 半導体装置の製造方法 |
JP2003332422A (ja) * | 2002-05-13 | 2003-11-21 | Sony Corp | 半導体装置およびその製造方法 |
CN1218393C (zh) | 2002-06-14 | 2005-09-07 | 台湾积体电路制造股份有限公司 | 具有局部狭缝的金属内连线构造及其制造方法 |
KR100474857B1 (ko) * | 2002-06-29 | 2005-03-10 | 매그나칩 반도체 유한회사 | 반도체 소자의 구리 배선 형성방법 |
US8009327B2 (en) * | 2002-07-11 | 2011-08-30 | Canon Kabushiki Kaisha | Method and apparatus for image processing |
US6617690B1 (en) | 2002-08-14 | 2003-09-09 | Ibm Corporation | Interconnect structures containing stress adjustment cap layer |
CN1492496A (zh) | 2002-10-24 | 2004-04-28 | 旺宏电子股份有限公司 | 形成多层低介电常数双镶嵌连线的制程 |
US20040183202A1 (en) * | 2003-01-31 | 2004-09-23 | Nec Electronics Corporation | Semiconductor device having copper damascene interconnection and fabricating method thereof |
JP2004282040A (ja) * | 2003-02-24 | 2004-10-07 | Nec Electronics Corp | 半導体装置およびその製造方法 |
TW200428586A (en) * | 2003-04-08 | 2004-12-16 | Matsushita Electric Ind Co Ltd | Electronic device and the manufacturing method thereof |
US6890851B2 (en) * | 2003-05-29 | 2005-05-10 | United Microelectronics Corp. | Interconnection structure and fabrication method thereof |
US20040249978A1 (en) * | 2003-06-05 | 2004-12-09 | International Business Machines Corporation | Method and apparatus for customizing a Web page |
US20050037153A1 (en) | 2003-08-14 | 2005-02-17 | Applied Materials, Inc. | Stress reduction of sioc low k films |
US7352053B2 (en) * | 2003-10-29 | 2008-04-01 | Taiwan Semiconductor Manufacturing Company, Ltd. | Insulating layer having decreased dielectric constant and increased hardness |
US7049247B2 (en) * | 2004-05-03 | 2006-05-23 | International Business Machines Corporation | Method for fabricating an ultralow dielectric constant material as an intralevel or interlevel dielectric in a semiconductor device and electronic device made |
US20060027924A1 (en) * | 2004-08-03 | 2006-02-09 | Taiwan Semiconductor Manufacturing Co., Ltd. | Metallization layers for crack prevention and reduced capacitance |
KR20060035257A (ko) | 2004-10-22 | 2006-04-26 | 한국전기초자 주식회사 | 플런저용 핑거의 레벨 측정장치 |
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- 2006-06-06 JP JP2006157253A patent/JP2006344965A/ja active Pending
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Patent Citations (5)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPH10189577A (ja) | 1996-12-25 | 1998-07-21 | Canon Sales Co Inc | 層間絶縁膜の形成方法、半導体装置及びその製造方法 |
US6362091B1 (en) | 2000-03-14 | 2002-03-26 | Intel Corporation | Method for making a semiconductor device having a low-k dielectric layer |
US6914335B2 (en) | 2000-03-14 | 2005-07-05 | Intel Corporation | Semiconductor device having a low-K dielectric layer |
US6764958B1 (en) | 2000-07-28 | 2004-07-20 | Applied Materials Inc. | Method of depositing dielectric films |
KR20040084668A (ko) * | 2003-03-25 | 2004-10-06 | 가부시끼가이샤 르네사스 테크놀로지 | 반도체 장치 및 그 제조 방법 |
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CN100403517C (zh) | 2008-07-16 |
FR2887368B1 (fr) | 2009-10-30 |
CN1881558A (zh) | 2006-12-20 |
JP2006344965A (ja) | 2006-12-21 |
US7638859B2 (en) | 2009-12-29 |
TW200644159A (en) | 2006-12-16 |
FR2887368A1 (fr) | 2006-12-22 |
US20060276027A1 (en) | 2006-12-07 |
SG127856A1 (en) | 2006-12-29 |
KR20060127805A (ko) | 2006-12-13 |
TWI319217B (en) | 2010-01-01 |
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