TW447075B - Method for forming dielectric layer with low dielectric constant - Google Patents

Method for forming dielectric layer with low dielectric constant Download PDF

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TW447075B
TW447075B TW89105996A TW89105996A TW447075B TW 447075 B TW447075 B TW 447075B TW 89105996 A TW89105996 A TW 89105996A TW 89105996 A TW89105996 A TW 89105996A TW 447075 B TW447075 B TW 447075B
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forming
watts
layer
dielectric constant
dielectric layer
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TW89105996A
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Lian-Jung Li
Shuang-Ming Jeng
Syun-Ming Jang
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Taiwan Semiconductor Mfg
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Abstract

The present invention discloses a method for forming a dielectric layer with a low permittivity, which comprises providing a semiconductor substrate completed with a front stage process of an integrated circuit; forming a first silicon nitride layer with a high compression stress; using three steps to form a first black diamond film, which comprises using N2O, O2 and methylsilane as the reaction gases and a high power radio frequency (RF) to perform a deposition of a film rich in oxygen; using N2O and methylsilane as the reaction gases and a high power RF to deposite a first black diamond film; using NH3 to perform an ion bombardment; forming a second silicon nitride layer with a high compression stress; using N2O, O2 and methylsilane as the reaction gases and a high power RF to perform a deposition of a film rich in oxygen; using N2O and methylsilane as the reaction gases and a high power RF to perform a deposition of a second black diamond film to complete the deposition of a dielectric layer with a low permittivity.

Description

447075 五、發明說明(1) 詳細說明: 技術領域: 本發明係關於一種在積體電路中形成低介電常數之介 電層的方法,特別是關於一種形成氮化矽層/低介電常數 介電層/氮化矽層/低介電常數介電層之複層結構的方法° 發明背景: 為了追求更快的運作速率以及更大的集積密度’積體 電路之研究單位及製造業者無不竭盡心力.地設計及製造關 鍵尺寸(Critical Dimension; CD)更小的元件。根據實驗 顯示,當積體電路的製程進入0.18微米甚至〇.1 3微米的技 術領域之後,影響元件運作速率的關鍵因素已從閘極的寬 度轉換至金屬内連線(metal interconnection)的電阻 容遲滯(RC delay)效應。 因導線的 積密度的提高 此其阻值便隨 度的提高,亦 線之間的輕合 微米領域之後 也因此影響積 體電路的集積 下’更換金屬 在金屬内連線 阻值與 ,金屬 之提高 使金屬 電容升 ,金屬 體電路 密度, 内連線 方面, 其截面積 内連線的 ;尤有甚 内連線的 高。因此 内連線的 的運算速 在線寬和 和層間介 金屬材質 成反比,隨著積體電路之集 線寬和厚度都隨之縮小,因 者’隨著積體電路之集積密 線距隨之縮小,因而造成導 當積體電路的製程進入深+ 電阻-電容遲滞大幅提高,人 率和存取速率。為了接+ 代1¾稽 線距都不宜提尚的條件t ^ 電層的材質是最佳的 由原先的銘梦銦合金$ A A銘鋼447075 V. Description of the invention (1) Detailed description: Technical field: The present invention relates to a method for forming a dielectric layer with a low dielectric constant in an integrated circuit, in particular to a method for forming a silicon nitride layer / low dielectric constant. Method of multilayer structure of dielectric layer / silicon nitride layer / low dielectric constant dielectric layer ° Background of the invention: Research units and manufacturers of integrated circuits in order to pursue faster operating speeds and greater integrated density Work hard to design and manufacture smaller critical dimension (CD) components. According to experiments, when the integrated circuit manufacturing process enters the technical field of 0.18 microns or even 0.13 microns, the key factor affecting the operating speed of the component has been changed from the width of the gate to the resistance of the metal interconnection. RC delay effect. As the product density of the wire increases, its resistance value increases with the degree, and the light micron field between the wires also affects the integration of the integrated circuit. Increasing the metal capacitance, the density of the metal body circuit, and the internal wiring, its cross-sectional area is connected; especially the internal wiring is high. Therefore, the calculation speed of the interconnect is inversely proportional to the line width and the interlayer metal material. As the integrated line width and thickness of the integrated circuit are reduced, the 'closed line distance of the integrated circuit is reduced. As a result, the manufacturing process of the integrated circuit goes deep + resistance-capacitance hysteresis is greatly improved, and the human rate and access rate are greatly increased. In order to connect + generation 1 ¾ line conditions should not be improved t ^ the material of the electrical layer is the best from the original Mingmeng indium alloy $ A Aming steel

第4頁 447075 五、發明說明(2) - 合金換成銅金屬,除了具有低電阻的特性外,更具有良好 的抗電子遷移性和良好的抗應力性,除了可以提高元件的 操作速率外’同時可以提升元件的可靠度;在另一方面, 層間介電層則必須選擇低介電常數(Dielectric Constant)的材質以取代原有的二氧化矽,以降低金屬内 連線之間的耦合電容《二氧化矽的介電常數約為3 9,因 此必須選取介電常數小於3. 9的介電質做為層間介電層, 方可達到降低電阻-電容遲滯的功效,例如:氟摻雜之二 氧化矽(Si 0F)、有機旋塗玻璃(KSq)等等。另外一種有效 之低介電常數的材質為黑鐵石(black diamond),其係由 甲基矽烷(11^1;?171311&116)所形成,其成分為矽20%、氧 30%、碳9%、氫36%、及其他元素。因黑鑽石約有36%的體 積為孔洞’因此其介電常數僅約為2. 9,是一種很具潛力 的低介電常數材質。 在銅製程的技術中,因銅金屬無法如同鋁合金一般用 氣氣進行#刻’因此業界發展出一種鑲叙(damascene)的 製程方法β鑲谈的製程技術可參考Motorola公司Boeck; Bruce Allen等人在美國專利第588001 8號所揭露之 "Method for manufacturing a low dielectric constant inter-level integrated circuit structure"。請參考圖一,在一已完成前段製程的半導體 基板10上連績形成第一氮化矽層11、第一低介電常數介電 層12、第二氮化矽層13、和第二低介電常數介電層14’再 以連續兩道微影與蝕刻技術形成如圖一 A之開口 1 5。其中Page 4 447075 V. Description of the invention (2)-In addition to the characteristics of low resistance, the alloy is replaced with copper metal, which also has good resistance to electron migration and good stress resistance, in addition to increasing the operating speed of the component ' At the same time, the reliability of the component can be improved; on the other hand, the interlayer dielectric layer must be selected from a low dielectric constant material to replace the original silicon dioxide to reduce the coupling capacitance between the metal interconnects. "The dielectric constant of silicon dioxide is about 39, so a dielectric with a dielectric constant less than 3.9 must be selected as the interlayer dielectric layer to achieve the effect of reducing the resistance-capacitance hysteresis, such as fluorine doping Silicon dioxide (Si 0F), organic spin-on glass (KSq), etc. Another effective material with a low dielectric constant is black diamond, which is formed by methyl silane (11 ^ 1;? 171311 & 116). Its composition is 20% silicon, 30% oxygen, and 9 carbon. %, Hydrogen 36%, and other elements. Because about 36% of the volume of black diamonds is holes ’, its dielectric constant is only about 2.9, which is a low-dielectric constant material with great potential. In copper process technology, because copper metal cannot be engraved with gas like aluminum alloy, so the industry has developed a damascene process method. For beta process technology, please refer to Motorola's Boeck; Bruce Allen, etc. "Method for manufacturing a low dielectric constant inter-level integrated circuit structure" disclosed in U.S. Patent No. 588001 8. Please refer to FIG. 1, a first silicon nitride layer 11, a first low-k dielectric layer 12, a second silicon nitride layer 13, and a second low-silicon layer are successively formed on a semiconductor substrate 10 that has completed the previous process. The dielectric constant dielectric layer 14 'is formed by two successive lithography and etching techniques as shown in the opening 15 of Fig. 1A. among them

第5頁 447075 五、發明說明(3) 氮化矽層1 1,1 3的沉積,係以S i Η和NH為反應氣體,利用 電漿增強式化學汽相沉積法(PEC VD)在Ν妁環境之下沉 積而形成約5 0 0埃(Angstrom)的薄膜,所需RF的功率約為 40 0瓦。依一般製程條件所形成的氮化矽層有一 ιέ 9達因/ 平方公分左右的壓縮應力。第一低介電常數介電層12和第 二低介電常數介電層1 4的沉積步驟,則以N 20和甲基矽烷 (methylsi lane)為反應氣體,利用電漿增強式化學汽相沉 積法(PECVD)沉積而成,其中所需RF的功率約為70瓦, N2 0的流量約為370sccm,甲基矽烷的流量約為68sccm’反 應時間約為6 0秒以形成約5 0 0 0埃的黑鑽石薄膜。 接下來請參考圖一 B,以PVD、CVD、或電鍍方法形成 一層銅薄膜1 6。最後如圖一 C所示,利用化學機械研磨法 (Chemical Mechanical Polishing; CMP)對所述銅薄膜 1 6 進行研磨,以形成銅導線1 7。 惟,傳統的銅導線/低介電常數介電層的整合製程中 一直有一惱人的問題,因為低介電常數介電層的拉伸應力 極大而使基板產生一極大的應變(warpage),當利用化學 機械研磨法對銅薄膜進行研磨時很容易造成基板邊緣的剝 離(delamination)’以致使基板的對準記號(alignment mark)模糊,甚至造成基板邊緣(約〇. 5至2公分)的磨損, 嚴重影響製程的良率》 因此,為了提高產品的良率,發展出一種穩定之銅導 線/低介電常數介電層的整合製程以解決上述之剝離問 題,便成為半導體業界一項很重要的課題。Page 5 447075 V. Description of the invention (3) The deposition of silicon nitride layer 1 1, 13 is based on Si i Η and NH as the reaction gas. Plasma enhanced chemical vapor deposition (PEC VD) A thin film of about 500 angstroms (Angstrom) is deposited under a thallium environment, and the required RF power is about 400 watts. The silicon nitride layer formed under normal process conditions has a compressive stress of about 9 dyne / cm 2. In the deposition steps of the first low-k dielectric layer 12 and the second low-k dielectric layer 14, N 20 and methylsi lane are used as reaction gases, and a plasma-enhanced chemical vapor phase is used. Deposition (PECVD) deposition, in which the required RF power is about 70 watts, the flow rate of N2 0 is about 370 sccm, the flow rate of methyl silane is about 68 sccm, and the reaction time is about 60 seconds to form about 50 0 0 Angstrom Black Diamond Film. Next, referring to FIG. 1B, a copper thin film 16 is formed by PVD, CVD, or electroplating. Finally, as shown in FIG. 1C, the copper thin film 16 is polished by chemical mechanical polishing (CMP) to form a copper wire 17. However, there is always an annoying problem in the traditional copper wire / low-k dielectric integration process, because the tensile stress of the low-k dielectric layer is extremely large, which causes a great warpage of the substrate. When chemical mechanical polishing is used to polish a copper thin film, it is easy to cause delamination of the substrate edge, so that the alignment mark of the substrate is blurred, and even the substrate edge (about 0.5 to 2 cm) is abraded. It seriously affects the yield of the process. "Therefore, in order to improve the yield of the product, the development of a stable copper wire / low dielectric constant dielectric layer integrated process to solve the above-mentioned peeling problems has become a very important part of the semiconductor industry. Subject.

447075 五 '發明說明(4) 發明概述: 本發明的主要目的為提供一種形成低介電常數之介電 層的方法。 本發明的次要目的為提供一種形成氮化矽層/低介電 常數介電層/氮化矽層/低介電常數介電層之複層結構的方 法。 本發明揭露一種形成低介電常數之介電層的方法,其 步驟首先提供一已完成積體電路之前段製程的半導體基 板’並在所述半導體基板上形成一層具高壓縮應力第一氮 化矽層。接下來以三個步驟形成第一黑鑽石薄膜,首先以 N2〇、0和曱基矽烷為反應氣體’以高功率的射頻進行富 含氧(02-rich)薄膜之沉積;接下來以N 20和甲基矽烷為反 應氣體’以高功率的射頻RF沉積第一黑鑽石薄膜;最後以 NH槐行離子轟擊。接著形成一層具高壓縮應力的第二氣 化石夕層’再以N 2〇、0和甲基矽烷為反應氣體,以高功率的 射頻RF進行富含氧(〇2_ri ch)薄膜之沉積;最後以]\f20和甲 基石夕烷為反應氣體’以高功率的射頻RF進行第二黑鑽石薄 膜的沉積’以完成氮化矽層/低介電常數介電層/氮化矽層 /低介電常數介電層之複層結構的沉積。 本發明方法所形成之氮化矽層/低介電常數介電層/氮 化石夕層/低介電常數介電層之複層結構有下列的優點: 1.本發明將氮化矽層的壓縮應力提高,以平衡低介 電常數介電層的拉伸應力,使基板的應變大幅減小,可以447075 V. Description of the invention (4) Summary of the invention: The main object of the present invention is to provide a method for forming a dielectric layer with a low dielectric constant. A secondary object of the present invention is to provide a method for forming a multi-layer structure of a silicon nitride layer / low dielectric constant dielectric layer / silicon nitride layer / low dielectric constant dielectric layer. The invention discloses a method for forming a dielectric layer with a low dielectric constant. The steps are as follows: firstly providing a semiconductor substrate that has completed the pre-process of the integrated circuit and forming a first nitride layer with high compressive stress on the semiconductor substrate; Silicon layer. The next step is to form the first black diamond film in three steps. First, using N2O, 0 and fluorenylsilane as the reaction gases, the high-power radio frequency is used to deposit an oxygen-rich (02-rich) film; then N 20 The first black diamond film was deposited with high-power radio frequency RF with methylsilane as the reaction gas; finally, it was bombarded with NH locust ion. Next, a second gasified rock layer with high compressive stress is formed, and then N 2 0, 0 and methyl silane are used as reaction gases, and high-power radio frequency RF is used to deposit an oxygen-rich (0 2_ri ch) film; finally, Use] \ f20 and methyllithoxane as reaction gases to 'deposit the second black diamond film with high power radio frequency RF' to complete the silicon nitride layer / low dielectric constant dielectric layer / silicon nitride layer / low Deposition of a multi-layer structure of a dielectric constant dielectric layer. The multilayer structure of the silicon nitride layer / low dielectric constant dielectric layer / nitride nitride layer / low dielectric constant dielectric layer formed by the method of the present invention has the following advantages: 1. The present invention combines the silicon nitride layer with The compressive stress is increased to balance the tensile stress of the low dielectric constant dielectric layer, which greatly reduces the strain of the substrate, which can

第7頁 447 075 -r^-T* ....... _ 丨· - r-—---------------- -___^ 五、發明說明(5) 避免後績利用化學機械研磨法對銅薄膜進行研磨時發生剝 離現象而導致晶片的對準記號模糊,甚矣造成晶片邊緣 (約0. 5至2公分)的磨損。 2. 本發明在沉積黑鑽石薄膜之前以ν 20、0和甲基梦 烷為反應氣體’以高功率的射頻RF進行富含氧薄膜之沉 積’以提高氮化矽層與黑鑽石薄膜之介面的強度,可避免 剥離現象的發生。 3. 在本發明中’黑鑽石薄膜的沉積製程將射頻心的 功率由傳統的70瓦提高至8〇瓦至ι4〇瓦之間,最佳射頻rf 功率為110瓦’可提高晶片封裝之打線製程的蠢裂阻值。 4. 本發明在沉積黑鑽石薄膜之後,以NH推行離子轟 擊’可以提高第一黑鑽石薄膜和後續所形成之第二氮化矽 層之介面的強度,亦可進一步避免剝離現象的發生。 圖式的簡要說明: 圖一 A是習知雙鑲嵌製程中在—已完成前段製程的半 導體基板上連續形成第一氮化妙層、第一低介電常數介電 層、第二氣化石夕層、和第二低介電常數介電層,再以連續 兩道微影與餘刻技術形成開口之製程的剖面示意圖。 圖一 B是習知雙鑲嵌製程中形成一層銅薄膜之製程的 剖面示意圖。 圖一 C是習知雙鑲嵌製程中利兩化學機械研磨法對所 述銅薄膜進行研磨,以形成銅導線之製程的剖面示意圖。 圖二是本發明形成氮化矽層/低介電常數介電層/t/化Page 7 447 075 -r ^ -T * ....... _ 丨 ·-r ------------------- -___ ^ V. Description of the invention (5 ) To avoid the occurrence of peeling phenomenon when the copper film is polished by the chemical mechanical polishing method, which will cause the alignment marks of the wafer to be blurred, and even cause the wear of the wafer edge (about 0.5 to 2 cm). 2. The present invention uses ν 20, 0 and methyl dreamane as reaction gases to deposit an oxygen-rich film with high power radio frequency RF before the black diamond film is deposited to improve the interface between the silicon nitride layer and the black diamond film. Strength to avoid the occurrence of peeling. 3. In the present invention, 'the black diamond film deposition process will increase the power of the RF core from the traditional 70 watts to between 80 watts and ι40 watts, and the optimal RF rf power is 110 watts', which can improve the chip packaging wiring. The stupid resistance of the process. 4. After the black diamond film is deposited, the present invention promotes ion bombardment with NH to increase the strength of the interface between the first black diamond film and the second silicon nitride layer formed later, and further avoid the occurrence of peeling. Brief description of the drawings: Figure 1A is a conventional dual-damascene process in which a first nitride layer, a first low-k dielectric layer, and a second gasified stone are continuously formed on a semiconductor substrate that has completed the previous process. Layer, and a second low-k dielectric layer, and then a schematic cross-sectional view of a process of forming an opening by two successive lithography and post-etching techniques. FIG. 1B is a schematic cross-sectional view of a process for forming a copper film in a conventional dual damascene process. FIG. 1C is a schematic cross-sectional view of a process of grinding the copper thin film to form a copper wire in a conventional dual-damascene process by using a chemical mechanical polishing method. FIG. 2 shows the formation of a silicon nitride layer / low dielectric constant dielectric layer / t / of the present invention.

第8頁 447 0 75 五、發明說明(6) 矽層/低介電常數介電層之複層結構的製程流程圖。 圖三A是本發明製程中在一已完成前段製程的半導體 基板上連續形成第一氮化矽層、第一低介電常數介電層、 第二氮化矽層、和第二低介電常數介電層之製程的剖面示 意圖。 圖三B是本發明製程中以連續兩道微影與蝕刻技術形 成開口之製程的剖面示意圖。 圖三C是本發明製程中形成一層銅薄膜之製程的剖面 示意圖。 圖三D是本發明製程中利用化學機械研磨法對所述銅 薄膜進行研磨,以形成銅導線之製程的剖面示意圖。 11 -第一氮化矽層 1 3-第二氮化矽層 1 5 -開口 17-銅導線 3 1 -第一氮化石夕層 3 3-第二氣化矽層 3 5-開口 圖號說明 1 0 -半導體基板 1 2-第一低介電常數介電層 14-第二低介電常數介電層 1 6 -銅薄膜 3 0 -半導體基板 32-第一低介電常數介電層 34-第二低介電常數介電層 3 6 _銅薄膜 3 7-銅導線Page 8 447 0 75 V. Description of the invention (6) Process flow chart of multi-layer structure of silicon layer / low dielectric constant dielectric layer. FIG. 3A is the first silicon nitride layer, the first low-k dielectric layer, the second silicon nitride layer, and the second low-dielectric layer are continuously formed on a semiconductor substrate that has completed the previous process in the process of the present invention. A schematic cross-sectional view of a process for manufacturing a constant dielectric layer. Fig. 3B is a schematic cross-sectional view of a process for forming an opening by two successive lithography and etching techniques in the process of the present invention. FIG. 3C is a schematic cross-sectional view of a process of forming a copper thin film in the process of the present invention. FIG. 3D is a schematic cross-sectional view of a process of polishing the copper film to form a copper wire by using a chemical mechanical polishing method in the process of the present invention. 11-First silicon nitride layer 1 3- Second silicon nitride layer 1 5-Opening 17-Copper wire 3 1-First nitride layer 3 3- Second vaporized silicon layer 3 5- Description of opening number 1 0-semiconductor substrate 1 2-first low dielectric constant dielectric layer 14-second low dielectric constant dielectric layer 16-copper thin film 3 0-semiconductor substrate 32-first low dielectric constant dielectric layer 34 -Second low dielectric constant dielectric layer 3 6 _copper film 3 7-copper wire

447075 五、發明說明(7) 本發明#揭露一種形成低介電常數之介電層的方法, 特別是關於一種形成氮化矽層/低介電常數介電層/氮化石夕 層/低介電常數介電層之複層結構的方法,以適用於銅製 程之雙鑲嵌製程。本發明可適用於各種型態之邏輯元件及 記憶體元件的銅導線/低介電常數介電層的整合製程。 本發明的製程流程圖請參閱圖二,首先提供一已完成積體 電路之前段製程的半導體基板21,利用化學汽相沉積法形 成一層具咼壓縮應力的第一氮化石夕層22。接下來以三個步 聯形成第一黑鑽石薄膜,首先以~2〇、〇和甲基矽烷為反應 氣體’以高功率的射頰評進行富含氧⑺厂㈠^㈣膜之沉 積23;接下來以Nz0和曱基矽烷為反應氣體,以高功率的 射頻RF沉積第一黑鑽石薄膜24 ;最後以NH粦行離子轟擊 2 5。接著再次利用化學汽相沉積法形成一層具高壓縮應力 的第二氣化矽層26’再以n2〇、0和曱基矽烷為反應氣體, 以高功率的射頻RF進行富含氧薄膜之沉積2 7 ;最後以N 20 和甲基石夕烧為反應氣體,以高功率的射頻RF進行第二黑鑽 石薄膜的沉積28,以完成氮化矽層/低介電常數介電層/氮 化石夕層/低介電常數介電層之複層結構的沉積。 請一併參考圖三A,其中步驟2 2係以S i Η和NH為反應 氣體’利用電漿增強式化學汽相沉積法(PECVD)在Ν妁 環境之下在半導體基板3 〇上形成第一氮化矽薄膜31,其厚 度介於3 0 0埃至1 〇 〇 〇埃之間。與習知製程不同的是’本發 明改變製程的參數,特別是將射頻RF的功率(power)變更 為介於450瓦至65 0瓦之間,使得所形成的第一氮化矽層31447075 V. Description of the invention (7) This invention # discloses a method for forming a dielectric layer with a low dielectric constant, in particular, a method for forming a silicon nitride layer / low dielectric constant dielectric layer / stone nitride layer / low dielectric The multi-layer structure method of the dielectric constant dielectric layer is suitable for the dual damascene process of the copper process. The invention can be applied to the integration process of copper wires / low dielectric constant dielectric layers of various types of logic elements and memory elements. Please refer to FIG. 2 for the process flow chart of the present invention. First, a semiconductor substrate 21 having completed the previous process of the integrated circuit is provided, and a first nitrided layer 22 with compressive stress is formed by chemical vapor deposition method. The next step is to form the first black diamond film in three steps. First, use ~ 2, 0 and methyl silane as the reaction gas to perform a high-powered cheek evaluation for oxygen-rich ⑺ ⑺ ㈣ ㈣ film deposition 23; Next, Nz0 and fluorenylsilane are used as reaction gases, and a first black diamond film 24 is deposited with high-power radio frequency RF; finally, NH is used to bombard 25. Then, a second vaporized silicon layer 26 'having a high compressive stress is formed again by chemical vapor deposition method, and then n 2 0, 0, and fluorene-based silane are used as reaction gases, and high-power radio frequency RF is used to deposit an oxygen-rich film. 27; Finally, the second black diamond film was deposited with high power RF RF using N20 and methyl sinter as reaction gases to complete the silicon nitride layer / low dielectric constant dielectric layer / nitride. Deposition of a multi-layer structure of a wicker / low-k dielectric layer. Please refer to FIG. 3A together, in which step 2 2 uses S i Η and NH as reaction gases to form a first semiconductor substrate 3 0 by using plasma enhanced chemical vapor deposition (PECVD) under the NH environment. A silicon nitride film 31 has a thickness between 300 angstroms and 1,000 angstroms. What is different from the conventional process is that the present invention changes the process parameters, especially the power of the radio frequency (RF) is changed to between 450 watts and 650 watts, so that the first silicon nitride layer 31 is formed.

447075 五、發明說明(8) 有一介於5 E 9至1. 5 E1 0達因/平方公分之間的壓縮應力。 因後續沉積的低介電常數介電層本身有極大的拉伸應力, 因此本發明刻意將氮化矽層的壓縮應力提高,以平衡低介 電常數介電層的拉伸應力,使半導體基板的應變大幅減 小,以避免後績利用化學機械研磨法對銅薄膜進行研磨時 發生剝離現象,導致半導體基板的對準記號(ali gnment mark)模糊,甚至造成基板邊緣(約〇. 5至2公分)的磨損》 除了黑鑽石薄膜之外,其他種類的低介電常數介電層(例 如:氟摻雜之二氧化矽(Si 0F)、有機旋塗玻璃(HSQ)等等 )亦同樣具有極大的拉伸應力《在本發明的另一實施例 中’可以將上述形成具有大壓縮應力之氮化矽層的製程應 用在其他任何一種低介電常數介電層的製程上,以平衡低 介電常數介電層極大的拉伸應力,使半導體基板的應變大 幅減小。 接下來本實施例以三個步驟形成第一黑鑽石薄膜,首 先如步驟2 3所示’以N 2〇、0和甲基矽烷為反應氣體,以高 功率的射頻RF進行富含氧薄膜之沉積,以提高氮化矽層與 黑鑽石薄膜之介面的強度。其中所述N 2〇的流量介於3 5 〇至 40〇SCCm之間,最佳流量為37〇sccm; 〇钓流量介於1〇至 5 0sccm之間,最佳流量為3〇sccm;曱基矽烷的流量介於 50至lOOsccm之間,最佳流量為68sccm; RF射頻的功率介 於120至250瓦之間,最佳功率為2〇〇瓦;本步驟所進行時 間介於〇· 5至5秒之間,最佳時間為2秒。本步驟可以提高 氮化矽層與黑鑽石薄膜之介面的強度,可避免剝離現象的447075 V. Description of the invention (8) There is a compressive stress between 5 E 9 and 1.5 E1 0 dyne / cm 2. Because the subsequently deposited low dielectric constant dielectric layer has a great tensile stress, the present invention intentionally increases the compressive stress of the silicon nitride layer to balance the tensile stress of the low dielectric constant dielectric layer, so that the semiconductor substrate The strain is greatly reduced to avoid the peeling phenomenon that occurs when the copper film is polished by chemical mechanical polishing method, which causes the semiconductor substrate alignment mark (ali gnment mark) to be blurred, and even causes the substrate edge (about 0.5 to 2 In addition to the black diamond film, other types of low dielectric constant dielectric layers (such as fluorine-doped silicon dioxide (Si 0F), organic spin-on glass (HSQ), etc.) also have Extremely high tensile stress "In another embodiment of the present invention, the above-mentioned process for forming a silicon nitride layer with large compressive stress can be applied to any other process with a low dielectric constant dielectric layer to balance low The great tensile stress of the dielectric constant dielectric layer greatly reduces the strain of the semiconductor substrate. Next, in this embodiment, the first black diamond film is formed in three steps. First, as shown in step 23, using the N 2 0, 0, and methyl silane as the reaction gas, the high-power radio frequency RF is used to perform the oxygen-rich film. Deposition to increase the strength of the interface between the silicon nitride layer and the black diamond film. Wherein, the flow rate of N 2〇 is between 350 and 40 SCCm, and the optimal flow rate is 37 ° sccm; and the fishing flow rate is between 10 and 50 sccm, and the optimal flow rate is 30 sccm; 曱The flow rate of the silane is between 50 and 100 sccm, and the optimal flow rate is 68 sccm. The power of the RF radio frequency is between 120 and 250 watts, and the optimal power is 200 watts. The time of this step is between 0.5 and 5 Between 5 and 5 seconds, the optimal time is 2 seconds. This step can increase the strength of the interface between the silicon nitride layer and the black diamond film, and can avoid peeling.

第11頁 447075 五、發明說明(9) 發生。 接下來如步驟2撕示,以N 20和甲基矽娱;為反應氣 體’利用電漿增強式化學汽相沉積法以高功率的射頻RF進 行黑鑽石薄膜的沉積’以形成約5 〇 0 〇埃的第一黑鑽石薄膜 3 2。其中所述N 2〇的流量介於3 5 0至4 0 0 s c c m之間,最佳流 量為3 70sccm;甲基矽烷的流量介於50至1 00seem之間, 最佳流量為6 8 s c c m ;反應時間介於3 0秒至1 0 〇秒之間,最 佳反應時間約為6 0秒。特別重要的是,本發明將射頻r j?的 功率由傳統的70瓦提高至80瓦至140瓦之間,最佳射頻Rf 功率為11 0瓦,可提高晶片封裝之打線製程(w i re bonding)的龜裂阻值(cracking resistance)。 最後如步驟25所示,以NH粦行離子轟擊,以提高第 .一黑错石薄膜32和後續所形成之第二氮化矽層33之介面的 強度。其中射頻RF的功率介於瓦至2〇〇瓦之間,最佳射 頻RF功率為ι50瓦。 接著如步驟2 6所示,再次利用化學汽相沉積法形成 一層具高壓縮應力的第二氮化矽層33,再如步驟2 7所示以 NaO、〇和甲基矽烷為反應氣體’以高功率的射頻進行富 含氧薄膜之沉積;最後如步驟2 8所示以N 20和甲基矽烷為 反應氣體’以高功率的射頻RF進行第二黑鑽石薄臈34的沉 積’以完成低介電常數之介電層的沉積。其中步驟26至步 驟28的製程條件與步驟22至步驟24的製程條件完全相同, 不再贅述。同樣地’在形成第二氮化石夕層3 3時亦將射頻RF 的功率變更為介於450瓦至6 5 0瓦之間,使得所形成的第二Page 11 447075 V. Description of Invention (9) Happened. Next, as shown in step 2, using N 20 and methyl silicon as a reaction gas, 'depositing a black diamond thin film with high power radio frequency RF using plasma enhanced chemical vapor deposition method' to form about 5000 〇Angel's first black diamond film 3 2. Wherein, the flow rate of N 2〇 is between 350 and 400 sccm, and the optimal flow rate is 3 70 sccm; the flow rate of methyl silane is between 50 and 100 seem, and the optimal flow rate is 6 8 sccm; The reaction time is between 30 seconds and 100 seconds, and the optimal reaction time is about 60 seconds. It is particularly important that the present invention increases the power of RF rj? From the traditional 70 watts to between 80 watts and 140 watts, and the optimal RF Rf power is 110 watts, which can improve the wi re bonding process for chip packaging. Cracking resistance. Finally, as shown in step 25, ion bombardment with NH is performed to increase the strength of the interface between the first black alumina film 32 and the second silicon nitride layer 33 formed subsequently. The RF power is between watts and 200 watts, and the optimal RF power is 50 watts. Then, as shown in step 26, a second silicon nitride layer 33 with high compressive stress is formed again by the chemical vapor deposition method, and then NaO, 〇, and methylsilane are used as the reaction gases as shown in step 27. High power radio frequency is used for the deposition of oxygen-rich films; finally, as shown in step 2 8 using N 20 and methyl silane as the reaction gas 'deposit the second black diamond thin 臈 34 with high power radio frequency RF' to complete the low Deposition of a dielectric layer with a dielectric constant. The process conditions of steps 26 to 28 are exactly the same as the process conditions of steps 22 to 24, and details are not described again. Similarly, when the second nitride stone layer 33 is formed, the power of the radio frequency RF is changed to between 450 watts and 650 watts, so that the formed second

第12頁 447 0 75 五、發明說明(ίο) 氮化矽層3 3有一介於5 E 9至1. 5 E1 0達因/平方公分之間的壓 縮應力’以平衡低介電常數介電層的拉伸應力,使基板的 應變大幅減小。 接下來請參考圖三B,以連續兩道微影與蝕刻技術形 成開口 35。接下來請參考圖三〇以PVD、CVD、或電鍍方 法形成一層銅薄臈3 6。最後如圖三D所示,利用化學機械 研磨法對所述銅薄膜3 6進行研磨,以形成銅導線37β 利用本發明方法所形成之氮化矽層/低介電常數介電 層/氮化妙層/低介電常數介電層之複層結構有下列的優 點:Page 12 447 0 75 V. Description of the invention (ίο) The silicon nitride layer 3 3 has a compressive stress between 5 E 9 and 1.5 E1 0 dyne / cm² to balance the low dielectric constant dielectric The tensile stress of the layer greatly reduces the strain of the substrate. Referring next to FIG. 3B, the opening 35 is formed by two successive lithography and etching techniques. Next, please refer to FIG. 30 to form a thin copper layer 36 by PVD, CVD, or electroplating. Finally, as shown in FIG. 3D, the copper thin film 36 is polished by a chemical mechanical polishing method to form a copper wire 37β. The silicon nitride layer / low dielectric constant dielectric layer / nitridation formed by the method of the present invention The multilayer / low-k dielectric layer has the following advantages:

1.本發明將氤化矽層的壓縮應力提高,以平衡低介 電常數介電層的拉伸應力,使基板的應變大幅減小,可以 避免後續利用化學機械研磨法對銅薄膜進行研磨時發生剝 h 離現象而導致基板的對準記號模糊,甚至造成基板邊緣 (約0 5至2公分)的磨損。 —2 .本發明在沉積黑鑽石薄膜之前以ν 2〇、〇和甲基矽 ,為反應氣體’以高功率的射頻以進行結晶化製程,以提 高氮化矽層與黑鑽石薄臈之介面的強度’可避免剝離現象 的發生。1. The present invention increases the compressive stress of the tritiated silicon layer to balance the tensile stress of the low dielectric constant dielectric layer, so that the strain of the substrate is greatly reduced, which can avoid the subsequent polishing of the copper thin film by chemical mechanical polishing. The peeling-off phenomenon occurs and the alignment mark of the substrate is blurred, and even the edge of the substrate (about 0.5 to 2 cm) is worn. -2. Before the black diamond film is deposited, the present invention uses ν 2〇, 0 and methyl silicon as a reaction gas to perform a crystallization process with a high-power radio frequency to improve the interface between the silicon nitride layer and the black diamond thin film. 'Strength' can prevent the occurrence of peeling.

3. 在本發明中’黑鑽石薄膜的沉積製程將射頻RF的功 ,由傳統的70瓦提高至8〇瓦至ι4〇瓦之間,最佳射頻“功 率為11 0瓦’可提鬲晶片封裝之打線製程的龜裂阻值。 4. 本發明在沉積黑鑽石薄膜之後’以NH粦行離子轟 擊’可以提高第一黑鑽石薄膜和後續所形成之第二氮化矽3. In the present invention, the 'black diamond film deposition process increases the RF RF power from the traditional 70 watts to between 80 watts and ι40 watts, and the optimal RF "power is 110 watts" can lift the wafer. The crack resistance value of the packaged wire bonding process. 4. After the black diamond film is deposited in the present invention, the ion bombardment with NH can improve the first black diamond film and the second silicon nitride formed subsequently.

第13頁 447075 五、發明說明(11) 層之介面的強度,亦可進一步避免剝離現象的發生。 以上所述係利用較佳實施例詳細說明本發明,而非限 制本發明的範圍,而且熟知此技藝的人士亦能明瞭,適當 而作些微的改變與調整,仍將不失本發明之要義所在,亦 不脫離本發明之精神和範圍。Page 13 447075 V. Description of the invention (11) The strength of the interface of the layer can further avoid the occurrence of peeling. The above description uses the preferred embodiments to explain the present invention in detail, but not to limit the scope of the present invention, and those skilled in the art will also understand that making small changes and adjustments appropriately will still lose the essence of the present invention. Without departing from the spirit and scope of the invention.

第14頁 447075 圊式簡單說明 圖式的簡要說明: 圖一 A是習知雙鑲喪製程_在一已完成前段製程的半 導體基板上連續形成第一氮化矽層、第一低介電常數介電 層、第二氮化矽層、和第二低介電常數介電層,再以連續 兩道微影與蝕刻技術形成開口之製程的剖面示意圖。 圖一 B是習知雙鑲嵌製程中形成一層銅薄膜之製程的 剖面示意圖。 圖一 C是習知雙鑲嵌製程中利用化學機械研磨法對所 述铜薄膜進行研磨,以形成銅導線之製程的剖面示意圖β 圖二是本發明形成氮化矽層/低介電常數介電層/氮化 夕層/低介電常數介電層之複層結構的製程流程圖。 第二氮化梦層、 意圖。 圖三Α是本發明製程中在一已完成前段製程的半 J板f連續形成第一氮化矽層、$一體 第一一"第二低介電常數介電層之製程的^示 成開π 圓 三B是本發明製程中] 之製程的剖面示意圖。风於奸挪則技術开 示意圖?C是本發明製程中形成-層鋼薄膜之製程的剖3 圖三D是本發明製程中利用化學 推件i 罕機械研磨法斜所、七 進行研磨,以形成銅導線之製程 厅述命 机枉的剖面不意圖〇Page 14 447075 Simple description of the schematic diagram Brief description of the diagram: Figure 1A is a conventional dual damascene process _ a first silicon nitride layer and a first low dielectric constant are continuously formed on a semiconductor substrate that has completed the previous process A schematic cross-sectional view of a process in which a dielectric layer, a second silicon nitride layer, and a second low-k dielectric layer are formed by two successive lithography and etching techniques. FIG. 1B is a schematic cross-sectional view of a process for forming a copper film in a conventional dual damascene process. FIG. 1C is a schematic cross-sectional view of a process for forming a copper wire by grinding the copper thin film by a chemical mechanical polishing method in a conventional dual damascene process. Β FIG. 2 is a silicon nitride layer / low dielectric constant dielectric according to the present invention. Process flow chart of the multilayer structure of the layer / nitride layer / low dielectric constant dielectric layer. Second nitride dream layer, intention. FIG. 3A is a diagram showing a process of continuously forming a first silicon nitride layer and a first low-dielectric constant second dielectric layer on a half-J plate f that has completed the previous process in the process of the present invention. Open π circle three B is a schematic cross-sectional view of the process in the process of the present invention. The wind is treacherous and the technology is opened. C is a sectional view of the process of forming a layer of steel film in the process of the present invention. FIG. 3D is a process in the process of the present invention using a chemical pusher, mechanical grinding method, and grinding to form a copper wire. The cross section of 枉 is not intended.

Claims (1)

447075 一 7~ 六、申請專利範圍 1. 一種形成低介電常數之介電層的方法,其製程步驟包 括有: a. 提供一已完成積體電路之前段製程的半導體基板; b. 在所述半導體基板上形成第一氮化矽層,其壓縮應 力大於5 E 9達因/平方公分; c. 以付20、〇和甲基矽烷為反應氣體,以射頻RF進行富 含氧薄膜之沉積; d. 沉積第一黑鑽石薄膜; e. 對所述第一黑鑽石薄膜進行離子轟擊; f. 在所述第一黑鑽石薄膜上形成第二氮化矽層,其壓 縮應力大於5 E 9達因/平方公分; g. 以N 20、〇和甲基矽烷為反應氣體,以射頻RF進行富 含氧薄膜之沉積;以及 h. 沉積第二黑鑽石薄骐。 2. 如申請專利範圍第1項所述之形成低介電常數之介電層 的方法’其中步驟(b)所述之第一氮化矽層係利用電漿增 強式化學汽相沉積法’將射頻RF的功率設定為介於45〇瓦 至650瓦之間’使得所形成的第一氮化矽層有一介於5E9 至I. 5E10達因/平方公分的壓縮應力。 3·如申請專利範圍第1項所述之形成低介電常數之介電層 的方法’其中步驟(c )中富含氧薄膜之沉積之n 2〇的流量 介於35 0至400seem之間;0的流量介於1〇至5〇sccm之 間,曱基石夕烧的流量介於5 0至loosccm之間;射頻r ρ的功 率介於120至2 5 0瓦之間。447075-7 ~ 6. Patent application scope 1. A method for forming a dielectric layer with a low dielectric constant, the process steps include: a. Providing a semiconductor substrate that has completed the previous stage of the integrated circuit; b. Forming a first silicon nitride layer on the semiconductor substrate, the compressive stress of which is greater than 5 E 9 dyne / cm 2; c. Using Fu 20, 0 and methyl silane as a reactive gas, and using radio frequency RF to deposit an oxygen-rich film D. Depositing a first black diamond film; e. Subjecting the first black diamond film to ion bombardment; f. Forming a second silicon nitride layer on the first black diamond film with a compressive stress greater than 5 E 9 Dyne / cm 2; g. Deposition of an oxygen-rich film using N 20, 0 and methyl silane as a reaction gas and radio frequency RF; and h. Deposition of a second black diamond thin film. 2. The method for forming a low dielectric constant dielectric layer as described in item 1 of the scope of the patent application, wherein the first silicon nitride layer described in step (b) is a plasma enhanced chemical vapor deposition method. The power of the radio frequency RF is set to be between 45 and 650 watts' so that the first silicon nitride layer formed has a compressive stress between 5E9 and 1.5E10 dyne / cm 2. 3. The method of forming a dielectric layer with a low dielectric constant as described in item 1 of the scope of the patent application, wherein the flow of n 2 in the oxygen-rich film deposition in step (c) is between 35 0 and 400 seem ; The flow rate of 0 is between 10 and 50 sccm, the flow rate of sillstone sintering is between 50 and loosccm; the power of radio frequency r ρ is between 120 and 250 watts. 第16頁 4 47 0 75 六、申請專利範圍 4.如申請專利範圍第1項所述之形成低介電常數之介電層 的方法,其中所述第一黑鑽石薄膜係以N 2〇和曱基矽烷為 反應氣體’利用電漿增強式化學汽相沉積法以功率介於8 〇 瓦至140瓦之間的射頻RF進行黑鑽石薄膜的沉積。 5 ·如申請專利範圍第4項所述之形成低介電常數之介電層 的方法’其中所述N 2〇的流量介於3 5 0至400sccm之間,甲 基矽烷的流量介於50至1 〇〇seem之間。 6,如申請專利範圍第1項所述之形成低介電常數之介電層 的方法’其中步驟(e)所述的離子轟擊係以NH3離子進 行,射頻RF的功率介於10()瓦至 2 0 0瓦之間β 7‘如申請專利範圍第1項所述之形成低介電常數之介電層 的方法’其中步驟(f)所述之第二氮化矽層係利用電漿增 強式化學汽相沉積法,將射頻評的功率設定為介於4 5 0瓦 至65 0瓦之間’使得所形成的第二氮化矽層有一介於5E9至 1. 5 E 1 0達因/平方公分的壓縮應力。 8‘如申請專利範圍第1項所述之形成低介電常數之介電層 的方法’其中步驟(g)中富含氧薄臈之沉積之N 2〇的流量 介於35 0至400sccm之間;〇約流量介於1〇至50sccm之 間;甲基矽烷的流量介於50至100seem之間;RF射頻的功 率介於120至250瓦之間。 •如申請專利範圍第1項所述之形成低介電常數之介電層 的方法,其中所述第二黑鑽石薄膜係以N 2〇和曱基矽烷為 反應氣體’利用電漿增強式化學汽相沉積法以功率介於8 〇 瓦至1 40瓦之間的射頻RF進行黑鑽石薄膜的沉積。Page 16 4 47 0 75 VI. Patent Application Range 4. The method for forming a dielectric layer with a low dielectric constant as described in item 1 of the patent application range, wherein the first black diamond thin film is made of N 2 0 and The fluorenyl silane is a reactive gas. The black diamond film is deposited using RF-RF between 80 watts and 140 watts using plasma enhanced chemical vapor deposition. 5. The method of forming a dielectric layer with a low dielectric constant as described in item 4 of the scope of the patent application, wherein the flow rate of N 2 0 is between 3 50 and 400 sccm, and the flow rate of methyl silane is 50 To 100 ohm. 6. The method of forming a dielectric layer with a low dielectric constant as described in item 1 of the scope of the patent application, wherein the ion bombardment described in step (e) is performed with NH3 ions, and the power of the radio frequency RF is between 10 () watts Β 7 to 200 watts as described in item 1 of the patent application for a method for forming a dielectric layer with a low dielectric constant ', wherein the second silicon nitride layer described in step (f) is a plasma The enhanced chemical vapor deposition method sets the power of the RF evaluation to between 450 and 650 watts, so that the formed second silicon nitride layer has a distance between 5E9 and 1.5 E 1 0 达Due to compressive stress per square centimeter. 8'The method for forming a low-dielectric-constant dielectric layer as described in item 1 of the scope of the patent application ', wherein the flow rate of the N 2 0 deposited in the step (g) rich in oxygen is between 350 and 400 sccm. 0; the flow rate is between 10 and 50 sccm; the flow rate of methyl silane is between 50 and 100 seem; the power of the RF radio frequency is between 120 and 250 watts. • The method for forming a low-dielectric-constant dielectric layer as described in item 1 of the scope of the patent application, wherein the second black diamond film is made of N 2 0 and fluorenyl silane as a reaction gas' using a plasma enhanced chemistry Vapor phase deposition uses radio frequency (RF) power between 80 watts and 140 watts to deposit black diamond films. 第17頁 447075 六、申請專利範圍 10. 如申請專利範圍第9項所述之形成低介電常數之介電 層的方法,其中所述N2〇的流量介於35 0至400sccm之間, 甲基矽烷的流量介於50至1 OOsccm之間。 11. 一種形成低介電常數之介電層的方法,其製程步驟包 括有: a. 提供一已完成積體電路之前段製程的半導體基板; b. 在所述半導體基板上形成第一氮化矽層,其壓縮應 力介於5E9至1. 5E10達因/平方公分之間; c. 以N 20、0和甲基矽烷為反應氣體,以射頻RF進行結 晶化製程; d. 以N20^甲基矽烷為反應氣體,利用電漿增強式化 學汽相沉積法以功率介於80瓦至1 40瓦之間的射頻rf沉積 第一黑鑽石薄膜; e. 對所述第一黑鑽石薄膜進行離子轟擊; f. 在所述第一黑鑽石薄膜上形成第二氮化矽層,其壓 縮應力介於5 E 9至1. 5 E 1 0達因/平方公分之間; g·以N2〇、0和甲基石夕烧為反應氣體’以射頻r f進行結 晶化製程:以及 h.以N 2〇和甲基矽烷為反應氣體’利用電漿増強式化 學汽相沉積法以功率介於80瓦至1 40瓦之間的射頻RF沉積 第二黑鑽石薄膜。 12. 如申請專利範圍第11項所述之形成低介電常數之介電 層的方法,其中步驟(b)所述之第一氮化矽層係利用電聚 增強式化學汽相沉積法,將射頻RF的功率設定為介於$ § 〇Page 17 447075 6. Application for patent scope 10. The method for forming a dielectric layer with a low dielectric constant as described in item 9 of the scope of patent application, wherein the flow rate of N20 is between 350 and 400 sccm. The flow of silanes is between 50 and 100 sccm. 11. A method for forming a dielectric layer with a low dielectric constant, the process steps of which include: a. Providing a semiconductor substrate that has completed the previous process of the integrated circuit; b. Forming a first nitride on the semiconductor substrate Silicon layer with compressive stress between 5E9 and 1.5E10 dyne / cm 2; c. Crystallization process using N 20, 0 and methyl silane as the reaction gas and RF; d. N20 ^ form Silane is a reactive gas, and a plasma enhanced chemical vapor deposition method is used to deposit a first black diamond film with a radio frequency rf between 80 watts and 140 watts; e. Ionizing the first black diamond film Bombarding; f. Forming a second silicon nitride layer on said first black diamond film, the compressive stress of which is between 5 E 9 and 1.5 E 1 0 dyne / cm 2; g · N2〇, 0 and methyllithium sintering as the reaction gas 'Crystalization process with radio frequency rf: and h. Using N 2 0 and methyl silane as the reaction gas' using plasma tough chemical vapor deposition with a power between 80 watt A second black diamond film is deposited with radio frequency RF between 1 and 40 watts. 12. The method for forming a low-dielectric-constant dielectric layer according to item 11 of the scope of the patent application, wherein the first silicon nitride layer described in step (b) uses an electro-enhanced chemical vapor deposition method, Set the RF RF power to between $ § 〇 第18頁 447075 六、申請專利範圍 瓦至6 5 0瓦之間,使得所形成的第一氮化石夕層有一介於 5 E 9至1. 5 E1 0達因/平方公分的壓縮應力。 1 3.如申請專利範圍第1 1項所述之形成低介電常數之介電 層的方法,其中步驟(c)中富含氧薄膜之沉積之N20的流量 介於35 0至400sccm之間;0的流量介於10至50sccm之 間;甲基矽烷的流量介於5 0至1 0 0 s c c m之間;R F射頻的功 率介於120至2 5 0瓦之間。 1 4.如申請專利範圍第11項所述之形成低介電常數之介電 層的方法,其中步驟(〇所述N20的流量介於3 5 0至400sccm 之間,甲基硬烧的流量介於5 0至lOOsccm之間° 15. 如申請專利範圍第11項所述之形成低介電常數之介電 層的方法,其中步驟(e)所述的離子轟擊係以NH雜子進 行,射頻RF的功率介於1 0 0瓦至2 0 0瓦之間β 16. 如申請專利範圍第11項所述之形成低介電常數之介電 層的方法,其中步驟(f)所述之第二氮化矽層係利用電漿 增強式化學汽相沉積法,將射頻RF的功率設定為介於450 瓦至6 5 0瓦之間,使得所形成的第二氮化矽層有一介於 5E9至1. 5E10達因/平方公分的壓縮應力。 17. 如申請專利範圍第11項所述之形成低介電常數之介電 層的方法,其中步驟(g)中富含氧薄膜之沉積之N 2〇的流量 介於35 0至400sccm之間;0妁流量介於10至50sccin之 間;甲基矽烷的流量介於5 0至1 〇 Osccm之間;射頻rf的功 率介於120至2 5 0瓦之間。 18. 如申請專利範圍第11項所述之形成低介電常數之介電Page 18 447075 VI. The scope of the patent application is between watts and 650 watts, so that the first nitride layer formed has a compressive stress between 5 E 9 and 1.5 E10 0 dyne / cm 2. 1 3. The method for forming a dielectric layer with a low dielectric constant as described in item 11 of the scope of patent application, wherein the flow rate of the N20 deposited in the oxygen-rich film in step (c) is between 350 and 400 sccm ; The flow rate of 0 is between 10 and 50 sccm; the flow rate of methyl silane is between 50 and 100 sccm; the power of the RF radio frequency is between 120 and 250 watts. 1 4. The method for forming a dielectric layer with a low dielectric constant as described in item 11 of the scope of the patent application, wherein in the step (0, the flow rate of N20 is between 350 and 400 sccm, and the flow rate of methyl hard burn Between 50 and 100 sccm ° 15. The method for forming a dielectric layer with a low dielectric constant as described in item 11 of the scope of patent application, wherein the ion bombardment described in step (e) is performed with NH heterodons, The power of radio frequency RF is between 100 watts and 200 watts. Β 16. The method for forming a low dielectric constant dielectric layer as described in item 11 of the scope of patent application, wherein The second silicon nitride layer uses a plasma-enhanced chemical vapor deposition method to set the power of the radio frequency RF to between 450 watts and 650 watts, so that the second silicon nitride layer formed has an interval between 5E9 to 1. 5E10 dyne / cm 2 compressive stress. 17. The method for forming a low dielectric constant dielectric layer as described in item 11 of the scope of patent application, wherein the step (g) is an oxygen-rich film deposition The flow rate of N 2〇 is between 35 0 and 400 sccm; the flow rate of 0 妁 is between 10 and 50 sccin; the flow rate of methyl silane is 50 Between 1 billion Osccm;. Radiofrequency rf power ranged between 120 and 250 watts 18. Item 11 is formed of the patent application range of the low-k dielectric 第19頁 447075 ΐ~~^-- 六、申請專利範圍 層的方法,其中步驟(h)所述Ν20的流量介於35 0至400sccm 之間,曱基矽烷的流量介於5 0至1 0 〇 s c c m之間。 19·—種形成低介電常數之介電層的方法,在一已完成積 $電路前段製程的半導體基板上形成氮化矽層/低介電常 介電層/氮化矽層/低介電常數介電層之複層結構,以利 層$種中雙鑲嵌製程的使用;其特徵在於所形成的氮化矽 Μ有—5E& uuo達因/平方公分之間的壓縮應力。 層的^申請專利範圍第19項所述之形成低介電常數之介電 沉積+法故其中所述氮化矽層係利用電漿增強式化學汽相 ’射頰RF的功率設定為介於45 0瓦至6 5 0瓦之間。Page 19, 447075 ΐ ~~ ^-6. The method of applying for a patent scope layer, wherein the flow rate of N20 in step (h) is between 350 and 400 sccm, and the flow rate of fluorenylsilane is between 50 and 10 〇sccm. 19 · —A method of forming a dielectric layer with a low dielectric constant, forming a silicon nitride layer / low dielectric constant dielectric layer / silicon nitride layer / low dielectric on a semiconductor substrate that has completed the pre-process of a circuit The multi-layer structure of the dielectric constant dielectric layer is used to facilitate the use of the dual damascene process; it is characterized in that the silicon nitride M formed has a compressive stress between -5E & uuo dyne / cm2. The dielectric deposition + method for forming a low dielectric constant as described in item 19 of the patent application range of the layer, wherein the silicon nitride layer uses a plasma-enhanced chemical vapor phase 'radio cheek RF power setting is between Between 450 watts and 650 watts. 第20冑Article 20
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Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638859B2 (en) 2005-06-06 2009-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnects with harmonized stress and methods for fabricating the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US7638859B2 (en) 2005-06-06 2009-12-29 Taiwan Semiconductor Manufacturing Co., Ltd. Interconnects with harmonized stress and methods for fabricating the same

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