FR2887368B1 - Interconnexions avec la contrainte harmonisee et procedes de fabrication de celles-ci - Google Patents

Interconnexions avec la contrainte harmonisee et procedes de fabrication de celles-ci

Info

Publication number
FR2887368B1
FR2887368B1 FR0605035A FR0605035A FR2887368B1 FR 2887368 B1 FR2887368 B1 FR 2887368B1 FR 0605035 A FR0605035 A FR 0605035A FR 0605035 A FR0605035 A FR 0605035A FR 2887368 B1 FR2887368 B1 FR 2887368B1
Authority
FR
France
Prior art keywords
harmonized
interconnections
constraint
methods
manufacturing same
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR0605035A
Other languages
English (en)
Other versions
FR2887368A1 (fr
Inventor
Yung Cheng Lu
Ming Hsing Tsai
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Original Assignee
Taiwan Semiconductor Manufacturing Co TSMC Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Taiwan Semiconductor Manufacturing Co TSMC Ltd filed Critical Taiwan Semiconductor Manufacturing Co TSMC Ltd
Publication of FR2887368A1 publication Critical patent/FR2887368A1/fr
Application granted granted Critical
Publication of FR2887368B1 publication Critical patent/FR2887368B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205—Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76829—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing characterised by the formation of thin functional dielectric layers, e.g. dielectric etch-stop, barrier, capping or liner layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76835—Combinations of two or more different dielectric layers having a low dielectric constant
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/5329—Insulating materials
    • H01L23/53295—Stacked insulating layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H01L21/76801—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing
    • H01L21/76802—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics
    • H01L21/76807—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics characterised by the formation and the after-treatment of the dielectrics, e.g. smoothing by forming openings in dielectrics for dual damascene structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Laminated Bodies (AREA)
  • Multi-Conductor Connections (AREA)
FR0605035A 2005-06-06 2006-06-06 Interconnexions avec la contrainte harmonisee et procedes de fabrication de celles-ci Active FR2887368B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US11/144,742 US7638859B2 (en) 2005-06-06 2005-06-06 Interconnects with harmonized stress and methods for fabricating the same

Publications (2)

Publication Number Publication Date
FR2887368A1 FR2887368A1 (fr) 2006-12-22
FR2887368B1 true FR2887368B1 (fr) 2009-10-30

Family

ID=37494709

Family Applications (1)

Application Number Title Priority Date Filing Date
FR0605035A Active FR2887368B1 (fr) 2005-06-06 2006-06-06 Interconnexions avec la contrainte harmonisee et procedes de fabrication de celles-ci

Country Status (7)

Country Link
US (1) US7638859B2 (fr)
JP (1) JP2006344965A (fr)
KR (1) KR100812731B1 (fr)
CN (1) CN100403517C (fr)
FR (1) FR2887368B1 (fr)
SG (1) SG127856A1 (fr)
TW (1) TWI319217B (fr)

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TWI278265B (en) * 2006-01-09 2007-04-01 Phoenix Prec Technology Corp Method for fabricating circuit board with electrically conducting structure and the same
US20070205507A1 (en) * 2006-03-01 2007-09-06 Hui-Lin Chang Carbon and nitrogen based cap materials for metal hard mask scheme
US7488984B2 (en) * 2006-04-19 2009-02-10 Flx Micro, Inc. Doping of SiC structures and methods associated with same
US8178436B2 (en) * 2006-12-21 2012-05-15 Intel Corporation Adhesion and electromigration performance at an interface between a dielectric and metal
WO2010035481A1 (fr) * 2008-09-26 2010-04-01 ローム株式会社 Dispositif à semi-conducteurs et procédé de fabrication de dispositif à semi-conducteurs
US9754822B1 (en) * 2016-03-02 2017-09-05 Taiwan Semiconductor Manufacturing Company, Ltd. Interconnect structure and method
US10199500B2 (en) 2016-08-02 2019-02-05 Taiwan Semiconductor Manufacturing Company, Ltd. Multi-layer film device and method
TWI632677B (zh) * 2017-06-09 2018-08-11 世界先進積體電路股份有限公司 半導體結構及其製造方法
US10276493B2 (en) * 2017-08-01 2019-04-30 Vanguard Enternational Semiconductor Corporation Semiconductor structure and method for fabricating the same
US10886465B2 (en) 2018-02-28 2021-01-05 Taiwan Semiconductor Manufacturing Co., Ltd. Resistive random access memory device
US11495658B2 (en) * 2018-06-08 2022-11-08 Texas Instruments Incorporated Hybrid high and low stress oxide embedded capacitor dielectric
CN111640756B (zh) * 2020-03-23 2022-05-31 福建省晋华集成电路有限公司 存储器及其形成方法
CN114743952A (zh) * 2022-06-14 2022-07-12 合肥晶合集成电路股份有限公司 半导体结构及其制作方法

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JP3226816B2 (ja) * 1996-12-25 2001-11-05 キヤノン販売株式会社 層間絶縁膜の形成方法、半導体装置及びその製造方法
US6100184A (en) * 1997-08-20 2000-08-08 Sematech, Inc. Method of making a dual damascene interconnect structure using low dielectric constant material for an inter-level dielectric layer
US6001730A (en) * 1997-10-20 1999-12-14 Motorola, Inc. Chemical mechanical polishing (CMP) slurry for polishing copper interconnects which use tantalum-based barrier layers
JP3719878B2 (ja) * 1999-06-15 2005-11-24 株式会社東芝 半導体装置及びその製造方法
US6362091B1 (en) * 2000-03-14 2002-03-26 Intel Corporation Method for making a semiconductor device having a low-k dielectric layer
TW447075B (en) 2000-03-31 2001-07-21 Taiwan Semiconductor Mfg Method for forming dielectric layer with low dielectric constant
US6358839B1 (en) * 2000-05-26 2002-03-19 Taiwan Semiconductor Manufacturing Company Solution to black diamond film delamination problem
US6764958B1 (en) * 2000-07-28 2004-07-20 Applied Materials Inc. Method of depositing dielectric films
JP4350337B2 (ja) * 2001-04-27 2009-10-21 富士通マイクロエレクトロニクス株式会社 半導体装置
US20020197852A1 (en) * 2001-06-21 2002-12-26 Ming-Shi Yeh Method of fabricating a barrier layer with high tensile strength
JP2003209111A (ja) * 2002-01-17 2003-07-25 Sony Corp 半導体装置の製造方法
JP2003332422A (ja) * 2002-05-13 2003-11-21 Sony Corp 半導体装置およびその製造方法
CN1218393C (zh) 2002-06-14 2005-09-07 台湾积体电路制造股份有限公司 具有局部狭缝的金属内连线构造及其制造方法
KR100474857B1 (ko) * 2002-06-29 2005-03-10 매그나칩 반도체 유한회사 반도체 소자의 구리 배선 형성방법
US8009327B2 (en) * 2002-07-11 2011-08-30 Canon Kabushiki Kaisha Method and apparatus for image processing
US6617690B1 (en) 2002-08-14 2003-09-09 Ibm Corporation Interconnect structures containing stress adjustment cap layer
CN1492496A (zh) 2002-10-24 2004-04-28 旺宏电子股份有限公司 形成多层低介电常数双镶嵌连线的制程
US20040183202A1 (en) * 2003-01-31 2004-09-23 Nec Electronics Corporation Semiconductor device having copper damascene interconnection and fabricating method thereof
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US7352053B2 (en) * 2003-10-29 2008-04-01 Taiwan Semiconductor Manufacturing Company, Ltd. Insulating layer having decreased dielectric constant and increased hardness
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Also Published As

Publication number Publication date
CN100403517C (zh) 2008-07-16
CN1881558A (zh) 2006-12-20
TWI319217B (en) 2010-01-01
KR100812731B1 (ko) 2008-03-12
FR2887368A1 (fr) 2006-12-22
JP2006344965A (ja) 2006-12-21
SG127856A1 (en) 2006-12-29
US7638859B2 (en) 2009-12-29
US20060276027A1 (en) 2006-12-07
KR20060127805A (ko) 2006-12-13
TW200644159A (en) 2006-12-16

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