CN100394561C - 半导体器件及其制造方法 - Google Patents

半导体器件及其制造方法 Download PDF

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Publication number
CN100394561C
CN100394561C CNB2004100768741A CN200410076874A CN100394561C CN 100394561 C CN100394561 C CN 100394561C CN B2004100768741 A CNB2004100768741 A CN B2004100768741A CN 200410076874 A CN200410076874 A CN 200410076874A CN 100394561 C CN100394561 C CN 100394561C
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Prior art keywords
interlayer dielectric
mentioned
elastic modulus
metal
semiconductor device
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CNB2004100768741A
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CN1595621A (zh
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松浦正纯
堀部裕史
松本晋
滨谷毅
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Renesas Electronics Corp
Panasonic Holdings Corp
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Renesas Technology Corp
Matsushita Electric Industrial Co Ltd
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Abstract

本发明的半导体器件配备：在半导体衬底上形成的弹性模量不同的多种层间绝缘膜(5、6、9、10、13、14、17、18、3、7、11、15、19)和配置在上述多种层间绝缘膜上的金属焊区(22)，还配备：具有上述不同的弹性模量之中最小的弹性模量，在上述金属焊区(22)下面设置了开口部的低弹性模量的层间绝缘膜(3、7、11、15、19)；具有比上述低弹性模量的层间绝缘膜的弹性模量大的弹性模量，以与上述低弹性模量的层间绝缘膜连接的方式，遍及上述开口部及其外围区域连续扩展并叠层了的非低弹性模量的层间绝缘膜(5、6、9、10、13、14、17、18)；以及在上述金属焊区下面，填埋上述低弹性模量的层间绝缘膜的开口部，与上述非低弹性模量的层间绝缘膜连接而配置的金属布线层(4、8、12、16、20)。

Description

半导体器件及其制造方法
技术领域
本发明涉及半导体器件及其制造方法，特别是涉及在使用了低机械强度的低介电常数层间绝缘膜的基础上，具有高可靠性的金属焊区的半导体器件及其制造方法。
背景技术
在0.18微米时代以后的系统LSI中，为了实现器件的高速化，降低器件的信号延迟十分重要。器件的信号延迟是用晶体管的信号延迟和布线延迟之和表示的，随着布线间距急剧缩小，与晶体管的信号延迟相比布线延迟的影响增大。由于布线延迟与电阻(R)和层间电容(C)的乘积(R×C)成正比，减小布线电阻或者降低层间绝缘膜的电容量对降低布线延迟是有效的。因此，为了解决上述问题，正在积极研究埋层布线结构的低介电常数的层间绝缘膜与铜布线的组合。
一般来说，金属焊区及其外围部形成一种在其最上层上进行引线键合的铝焊区或者铝铜合金焊区和配置在其下层上、用铜布线形成的焊区及用支撑栓支撑的叠层结构。该特殊金属焊区及其外围部的结构已予公布(M.Inohara et al，Technical Digest of 2002 IEDMpp.77～80“High Performance Copper and Low-k InterconnectTechnology Fully Compatible to 90nm-Node SOC Application(CMOS4)”)。
如上所述，在最先进的系统LSI中，为了降低布线延迟，正在积极研究引入低介电常数的层间绝缘膜。如举出能够作为这种低介电常数材料应用的材料，则有：氢化硅倍半氧烷(HydrogenSilsesquioxane)、甲基硅倍半氧烷(Methy Silsesquioxane)、聚芳基醚(Poly Arylether)、聚亚苯基聚合物(PolyphenylenePolymer)、苯并环丁烯(Benzocyclobutene)、聚四氟乙烯(Polytetrafluoroethylene)和作为多孔二氧化硅的干凝胶(Xerogel)、气凝胶(Aerogel)等用旋转涂敷法形成的材料，和氟掺杂氧化硅膜(SiOF膜)、氟掺杂无定形碳膜(CF膜)、聚对亚苯基二甲基(Parylene)、碳掺杂氧化硅膜(SiOF膜)等用CVD(化学气相生长法：Chemical Vapor Deposition)形成的材料。
上述材料，与迄今一直使用的氧化硅膜相比机械强度非常弱。表1对氧化硅膜和代表性的低介电常数的层间绝缘膜中使用的SiOC膜的硬度及弹性模量进行了比较。
[表1]
  硬度   弹性模量
  氧化硅膜(非低弹性模量)   9(GPa)   70～100(GPa)
  碳掺杂氧化硅膜(低弹性模量)   2(GPa)   13(GPa)
根据表1可知，降低了介电常数的SiOC膜的硬度及弹性模量比现有的氧化硅膜大大降低。在以下的说明中，将这样的硬度及弹性模量的降低总称为机械强度的降低。
起因于上述层间绝缘膜的机械强度的降低，在进行用于引线键合和器件测试的探针检测(探针接触)时，配置在金属焊区下层上的层间绝缘膜中产生裂纹，在引线键合中发生焊接不良。因此，提出了许多提高金属焊区及其外围部的可靠性的方案(例如参考特开2000-340569、特开2000-183104、特开2001-308100号公报)。
但是，随着金属焊区的极小化，在进行引线键合时施加的冲击应力增高，要求缓和更大的应变、防止裂纹和膜剥落的金属焊区的下部结构。
发明内容
本发明的目的在于：提供防止在使用机械强度低的低介电常数层间绝缘膜时成为问题的金属焊区下层发生的层间绝缘膜的裂纹和焊接不良的半导体器件及其制造方法。
本发明的半导体器件配备：在半导体衬底上形成的弹性模量不同的多种层间绝缘膜和配置在多种层间绝缘膜的上面的金属焊区。而且，该半导体器件配备：具有不同的弹性模量之中最小的弹性模量，在上述金属焊区的下面设置了开口部的低弹性模量的层间绝缘膜；具有比低弹性模量的层间绝缘膜的弹性模量大的弹性模量，以与低弹性模量的层间绝缘膜连接的方式，遍及开口部及其外围区域连续扩展并叠层了的非低弹性模量的层间绝缘膜；以及在金属焊区的下面，填埋低弹性模量的层间绝缘膜的开口部，与非低弹性模量的层间绝缘膜连接而配置的金属布线层。
按照上述结构，金属焊区的下部配置非低弹性模量的层间绝缘膜和金属布线层，而不配置低弹性模量的层间绝缘膜。因此，在引线键合中，有可能发生裂纹的低弹性模量的层间绝缘膜不正面接受引线键合的冲击应力，能够防止裂纹发生。另外，缓和在金属布线层与非低弹性模量的层间绝缘膜的界面上发生的应变，也能够可靠地防止偏离了金属焊区正下方的位置处的低弹性模量的层间绝缘膜的剥落。
本发明的半导体器件的制造方法是具有进行与外部的电连接的金属焊区，在半导体衬底上形成的半导体器件的制造方法。该制造方法具有：在半导体衬底的上方形成具有比氧化硅膜小的弹性模量的低弹性模量的绝缘层的工序；以及在低弹性模量的绝缘层中，在形成金属焊区的该部位设置开口部的工序。另外，还配备：形成填埋开口部、覆盖低弹性模量的绝缘膜的金属层的工序；以及在金属层上实施化学机械研磨处理，使低弹性模量的绝缘层及开口部的金属层露出的工序。而且，还配备：在实施化学机械研磨处理后，用具有比低弹性模量的绝缘膜的弹性模量大的弹性模量的绝缘层，覆盖金属层及低弹性模量的绝缘层的工序；在由低弹性模量的绝缘层、金属层及非低弹性模量的绝缘层构成的叠层结构的上方，设置金属焊区的工序。
按照上述的方法，能够简单地形成可靠性高的金属焊区结构。
从结合附图而被理解的本发明下面的详细的说明，本发明的上述和其它的目的、特征、方面和优点会变得明白。
附图说明
图1是表示本发明的实施例1中的半导体器件的金属焊区部的结构的图。
图2A及图2B是沿图1的II-II线的剖面图，图2A表示没有孔的金属布线层，图2B表示排列了孔的金属布线层。
图3是表示本发明的实施例2中的半导体器件的金属焊区部的结构图。
图4A及图4B是沿图3的IV-IV线的剖面图，图4A表示金属布线层被埋入离散的孔中的状态的图，图4B表示金属布线层被埋入条形孔中的状态的图。
图5是表示本发明的实施例3中的半导体器件的金属焊区部的结构的图。
具体实施方式
接着，用附图说明本发明的实施方式。
实施例1
图1是表示本发明的实施例1中的半导体器件的金属焊区外围的结构的图。在本实施例中，在包含在硅衬底1上形成的晶体管等元件的基底绝缘层2上，形成具有为了抑制布线电容而选定的低介电常数的第1低介电常数层间绝缘膜3。作为低介电常数的大体的标准是比氧化硅膜低的介电常数。由于氧化硅膜的介电常数是4.3，作为标准是指具有比4.3小的介电常数。为了降低布线电容，希望是比4.3小的介电常数。例如，作为更低的低介电常数材料希望介电常数是3以下的材料。
由于上述第1低介电常数层间绝缘膜3的弹性模量等机械的强度低，也可以称为第1低弹性模量的层间绝缘膜。作为低弹性模量的大体的标准虽说是比氧化硅膜低的弹性模量，作为具体的数值是指弹性模量不足50Gpa的情况。因此，上述的非低弹性模量层间绝缘膜是指具有50GPa以上弹性模量的层间绝缘膜。所谓弹性模量非常大的情况，是指弹性模量100GPa以上的情况。在本说明中，除非另有特别说明，所谓非低弹性模量层间绝缘膜的情况多半是指弹性模量非常大的层间绝缘膜的情况。弹性模量例如能够利用毫微凹入法(微小压进实验法)求出。
接着，通过光刻和干法刻蚀，对第1低介电常数层间绝缘膜3形成所希望的布线图形沟槽(开口部)3a，在该开口部3a中形成第1铜布线。虽然没有图示，但在第1铜布线4上配置作为阻挡层金属的钽或者氮化钽，以防止铜向层间绝缘膜中扩散。因此，第1铜布线4的下表面及两侧面被阻挡层金属覆盖。对于后面将要说明的铜布线，除非另有特别说明，用阻挡层金属覆盖。
在本实施例中，在第1低介电常数层间绝缘膜3上使用用等离子体CVD法形成的碳掺杂氧化硅膜(SIOC膜)。另外，在本实施例中应用的铜布线用下述步骤制作。首先，在用溅射法形成的钽或者氮化钽的阻挡层金属上，用溅射法形成薄膜的铜。接着，用电镀法在它的上面形成厚膜的铜。即铜布线由用溅射法形成的薄膜的铜和用电镀法形成的厚膜的铜构成。
然后，用化学机械研磨法(Chemical Mechanical Polishing：CMP)除去不需要部分的铜及阻挡层金属，最终在沟槽(开口部)3a中形成第1铜布线4。铜布线可以是没有孔和空隙等的通常的薄膜，也可以是在内部排列了孔的薄膜。即，如图2A或者图2B所示，沿第1铜布线4的部分的II-II线的剖面图可以是完全的薄膜，也可以是排列了孔4a的薄膜。与铜布线4位于同一层的绝缘膜3埋入该孔4a中。即孔4a被第1低介电常数层间绝缘膜3填埋。
接着，形成介电常数及弹性模量比第1低介电常数层间绝缘膜3都高的第1非低介电常数层间绝缘膜5及第2非低介电常数层间绝缘膜6。在本说明中，称(第1低介电常数层间绝缘膜3/第1非低介电常数层间绝缘膜5/第2非低介电常数层间绝缘膜6)为第1层。
接着，在其上形成低介电常数的第2低介电常数层间绝缘膜7。接着，通过光刻和干法刻蚀，对第2低介电常数层间绝缘膜7形成所希望的布线图形的沟槽(开口部)7a。接着，通过CMP处理等，在其开口部7a中形成第2铜布线8。在第2铜布线8上形成第3非低介电常数层间绝缘膜9及第4非低介电常数层间绝缘膜10。(第2低介电常数层间绝缘膜7/第3非低介电常数层间绝缘膜9/第4非低介电常数层间绝缘膜10)成为第2层。
在本实施例中使用了的第1及第3非低介电常数层间绝缘膜5、9中，能够应用以等离子体CVD法形成的氮化硅膜和碳化硅膜，或者氮掺杂碳化硅膜、氧掺杂碳化硅膜等。在本实施例中应用了碳化硅膜。另外，在第2及第4非低介电常数层间绝缘膜6、10中，应用了用同样的等离子体CVD法形成的氧化硅膜。如表1所示，该氧化硅膜比作为本实施例的低介电常数层间绝缘膜的SiOC膜硬度及弹性模量大，难以发生因测试探测和引线键合引起的裂纹。
接着，用与第2层同样的方法形成第3层及第4层的层间绝缘膜和铜布线。最后，形成第5层的低介电常数层间绝缘膜19和铜布线20。
在如上形成的第5层的铜布线上，形成第1钝化膜21。接着，用配置连接孔21a的图形刻蚀第1钝化膜21，使第5层的铜布线20的表面露出。
在第1钝化膜21中应用了用等离子体CVD法形成的氮化硅膜、氧化硅膜、氮氧化硅膜等。进而，在其上用溅射法形成铝焊区22，进一步用第2钝化膜23覆盖其表面。在第2钝化膜23中也应用了用等离子体CVD法形成的氮化硅膜、氧化硅膜、氮氧化硅膜等。按所希望的图形刻蚀第2钝化膜23，使铝焊区22露出，以便进行引线键合。最后，在铝焊区上形成引线键合部。
在现有的金属焊区的结构中，弹性模量低的低弹性模量层间绝缘膜被配置在金属焊区下方。因此，在对铝焊区施加垂直向下的应变的情况下，在弹性模量有很大差异的铜布线与SiOC膜的界面，或者在氧化硅膜与SiOC膜的界面，产生很大的应变量。其结果是，局部地增大存储在这些界面上的内部应力。该内部应力的增大促进在界面处的剥离，作为结果，在膜内部产生裂纹或者引线键合部的焊接不良(剥落)。
在本实施例的半导体器件的结构中，在铝焊区正下方配置弹性模量高的氧化硅膜和铜布线(铜的弹性模量约为130Gpa，与氧化硅膜同样大小)，不配置弹性模量低的层间绝缘膜。其结果是，在本实施例中，通过在铝焊区正下方填埋弹性模量高的氧化硅膜和铜布线，减轻弹性模量之差。因此，在引线键合和测试探测时，减轻附加在铝焊区正下方的垂直方向的应变量，能够防止因引线键合或者测试探测而发生的裂纹和引线键合中的焊接不良。
在本实施例中，在全部5层布线层中都插入了铜布线，即使在一部分的层中插入铜布线，也能够得到同样的效果。这种情况下，希望在接近铝焊区的布线层中插入铜布线。
另外，在本实施例中，在连接孔21a的层21上配置弹性模量高的氧化硅膜。这种情况下，铝焊区以外的部分，例如在连结元件之间的配置金属布线(铜布线)的部分，也在连接孔的层上配置氧化硅膜。即使在这种情况下，由于在金属布线间上也配置低介电常数层间绝缘膜，因配置氧化硅膜而引起的布线间电容的增加是很少一点点。另外，出于竭力降低布线间电容的目的，也可以在铝焊区以外的金属布线部分在连接孔的层上配置低介电常数层间绝缘膜。在这种情况下，在铝焊区正下方及其外围部分，能够有选择地在连接孔的层上配置氧化硅膜。
实施例2
图3是表示本发明的实施例2中的半导体器件的金属焊区的结构的图。由于该实施例中的层间绝缘膜及铜布线的形成方法与实施例1完全相同，故省略其详细说明。
与本发明的实施例1不同的部分在于各层的铜布线填埋位于其下的连接孔而形成。即，在第2层中，第2铜布线8填埋连接孔5a、6a而形成，在第3层中，第3铜布线填埋连接孔9a、10而形成。进而在第4层上有填埋连接孔13a、14a而形成的第4铜布线16，在第5层中，有填埋连接孔17a、18a而形成的第5铜布线20。上述连接孔也可以仅仅称为「孔」。
沿图3中的IV-IV线的剖面图成为图4A或者图4B。铜布线可以如图4A所示那样填埋离散的孔14a，也可以如图4B所示那样填埋条形孔14a。不论那种情况都用「孔」表现。
在本实施例中，由于增加了用铜形成的连接孔的部分，与实施例1相比增大了铝焊区正下方处的机械强度。因此，能够进一步彻底地减轻因引线键合或者测试检测而引起的应变。其结果是，能够防止因引线键合或者测试检测而发生的裂纹和引线键合中的焊接不良。
实施例3
图5是表示本发明的实施例3中的半导体器件的金属焊区的结构的图。由于本实施例中的层间绝缘膜及铜布线的形成方法与实施例1完全相同，故省略其详细的说明。与实施例1的不同点在于配置在设置于各层的低弹性模量的层间绝缘膜上的开口部3a、7a、11a、15a、19a中的铜布线4、8、12、16、20的平面尺寸不一致。更具体地说，在上下方向上备层的铜布线的平面尺寸交互变化。第2层的铜布线被配置成比第1层的铜布线4的平面尺寸大。在第3层和第5层中，与第1层同样地减小，在其间的第4层中，与第2层同样地大。
在本实施例中，通过交互改变所配置的铜布线4、8、12、16、20的大小，能够减轻在铜布线的外围附近的应变的集中。使铜布线的平面尺寸一致而插入的情况下，在上下方向上铜布线的端部一致，在低介电常数层间绝缘膜所连接的铜布线外围的应变的集中增大。像本实施例那样通过交互错开铜布线的端部的位置，能够减轻应变的集中。
另外，在交互改变上述铜布线的大小的结构中，如在实施例2中说明的那样，设置填埋连接孔的铜布线，除本实施例中的效果外，还能够得到与在实施例2中得到的效果同样的效果。
最后，包含上述本发明的实施例中说明过的例子在内，对本发明的实施例罗列式地举出例子。
上述非低介电常数的层间绝缘膜也可以形成为由第1非低介电常数层间绝缘膜和连接它并位于其上、与第1非低介电常数层间绝缘膜不同材料的第2非低弹性模量的层间绝缘膜构成的结构。
通过将2块非低弹性模量的层间绝缘膜重叠，在该高强度的2块层间绝缘膜的界面处使冲击能量衰减，能够防止来自其他的应力集中部的裂纹发生。
另外，如反复说明的那样，前提是非低弹性模量的层间绝缘膜的介电常数比低弹性模量的层间绝缘膜的介电常数大。
也可以采取在上述金属焊区下面的开口部的非低弹性模量的层间绝缘膜中开孔，用金属布线层填埋该孔的结构。铜等的金属布线的弹性模量非常高，为100GPa程度以上，通过使该金属布线一边填埋孔一边遍布上下连续扩展，能够实现优异的机械强度。另外，也能够期待在层间绝缘膜的孔侧面和金属布线的界面处的冲击能量的衰减等。
也可以采取在上述金属布线层中开孔，与该金属布线层同一层的低弹性模量的层间绝缘膜填埋孔的结构。在这种情况下，在叠层界面上弹性模量不产生很大的差异，能够实现优异的机械强度。另外，也能够期待在金属布线的孔侧面和层间绝缘膜的界面处的冲击能量的衰减等。
能够采取包含上述开口部中的非低弹性模量的层间绝缘膜和开口部被金属布线层填埋了的低弹性模量的层间绝缘膜的叠层结构被重叠2层以上的结构。这样通过采取多层叠层结构，能够取得与形成用于实现半导体器件原来的功能的结构的多个部分的匹配性。另外，多层叠层结构的各界面也能够有效地吸收引线键合等中的冲击能量。
在包含上述开口部中的非低弹性模量的层间绝缘膜和开口部被金属布线层填埋了的低弹性模量的层间绝缘膜的叠层结构被重叠2层以上的情况下，能够采取使上下邻接的层内的金属布线层的平面尺寸变得不同的结构。按照该结构，金属布线的端部在上下并不一致，能够减轻在金属布线的端部一致的情况下所发生的应力集中。
虽然对本发明已进行了详细说明和揭示，但显然可知，所作的说明仅仅是例示性的而不是限定性的，本发明的宗旨和范围仅由所附权利要求书的范围来限定。

Claims (10)

1.一种半导体器件，其特征在于：
配备在半导体衬底上形成的弹性模量不同的多种层间绝缘膜和配置在上述多种层间绝缘膜的上面的用于引线键合的金属焊区，
还配备：
多种包括第1层间绝缘膜的层间绝缘膜，该第1层间绝缘膜具有上述不同的弹性模量之中最小的弹性模量，并在上述金属焊区的下面设置了开口部；
多种包括第2层间绝缘膜的层间绝缘膜，该第2层间绝缘膜具有比最小弹性模量大的弹性模量，在上述第1层间绝缘膜之下并与其接触；以及
金属布线层，具有比最小弹性模量大的弹性模量，配置在上述金属焊区的下面，填埋上述第1层间绝缘膜的开口部，并在金属布线层的下表面与上述第2层间绝缘膜接触，
其中，金属布线层和第2层间绝缘膜紧靠金属焊区之下被配置，而第1层间绝缘膜是将金属焊区配置在开口部的区域中而不在金属焊区之下被配置。
2.如权利要求1所述的半导体器件，其特征在于：
上述第2层间绝缘膜由第3非低弹性模量的层间绝缘膜和与上述第3非低弹性模量的层间绝缘膜不同材料的第4非低弹性模量的层间绝缘膜构成。
3.如权利要求2所述的半导体器件，其特征在于：
在上述金属焊区下面的上述第2层间绝缘膜中开孔，金属布线层填埋该孔。
4.如权利要求2所述的半导体器件，其特征在于：
包含非低弹性模量的一层间绝缘膜和每个的开口部被一金属布线层填埋了的低弹性模量的层间绝缘膜的叠层结构被重叠2层以上。
5.如权利要求2所述的半导体器件，其特征在于：
包含非低弹性模量的一层间绝缘膜和每个的开口部被一金属布线层填埋了的低弹性模量的层间绝缘膜的叠层结构被重叠2层以上，在上下邻接的层中的上述金属布线层其平面尺寸不同。
6.如权利要求2所述的半导体器件，其特征在于：
在上述金属布线层中开孔，与该金属布线层同一层的一个最小弹性模量的层间绝缘膜填埋上述孔。
7.如权利要求6所述的半导体器件，其特征在于：
包含非低弹性模量的一层间绝缘膜和每个的开口部被一金属布线层填埋了的低弹性模量的层间绝缘膜的叠层结构被重叠2层以上，在上下邻接的层中的上述金属布线层其平面尺寸不同。
8.如权利要求1所述的半导体器件，其特征在于：
上述第2层间绝缘膜的介电常数比上述第1层间绝缘膜的介电常数大。
9.如权利要求8所述的半导体器件，其特征在于：
包含非低弹性模量的一层间绝缘膜和开口部被一金属布线层填埋了的最小弹性模量的一层间绝缘膜的叠层结构被重叠2层以上，在上下邻接的层中的上述金属布线层其平面尺寸不同。
10.一种半导体器件的制造方法，这是具有进行与外部的电连接的金属焊区，在半导体衬底上形成的半导体器件的制造方法，其特征在于：
配备：
在上述半导体衬底的上方形成第1绝缘层的工序；
在上述第1绝缘层上形成具有比第1绝缘层和氧化硅膜还要小的弹性模量的第2绝缘层的工序；
在所述第2绝缘层，在所述金属焊区的形成位置设置开口部，使第1绝缘层在下方露出的工序；
形成填埋上述开口部、覆盖上述第2绝缘层、并在开口部的下方接触第1绝缘层的金属层的工序；
在上述金属层上实施化学机械研磨处理，使上述第2绝缘层及开口部的金属层露出的工序；
在由上述第1绝缘层、金属层及第2绝缘层构成的叠层结构的上方，设置金属焊区的工序。
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US20070145583A1 (en) 2007-06-28
KR100605428B1 (ko) 2006-07-28
US20050054188A1 (en) 2005-03-10
US7202565B2 (en) 2007-04-10
JP2005085939A (ja) 2005-03-31
KR20050025916A (ko) 2005-03-14

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