CN1311530A - 用于改善后端生产线结构稳定性的混合介质结构 - Google Patents

用于改善后端生产线结构稳定性的混合介质结构 Download PDF

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CN1311530A
CN1311530A CN01108312A CN01108312A CN1311530A CN 1311530 A CN1311530 A CN 1311530A CN 01108312 A CN01108312 A CN 01108312A CN 01108312 A CN01108312 A CN 01108312A CN 1311530 A CN1311530 A CN 1311530A
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查尔斯·R·戴维斯
丹尼尔·C·埃德尔斯坦
约翰·C·海
杰弗里·C·赫德里克
克里斯托弗·詹尼斯
文森特·迈克海
亨利·A·奈三世
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Abstract

集成电路芯片上的一种多层共面铜镶嵌互连结构,它包括集成电路衬底上的具有被介电常数较低且弹性模量也较低的介电材料分隔的多个线路导体的第一平面互连层。第一平面互连层上的第二平面互连层包含弹性模量比第一平面互连层更高的介电膜和穿过其中的导电通孔。通孔选择性地接触到线路导体。第二平面互连层上的第三平面互连层具有被介电材料分隔并选择性地接触到通孔的多个线路导体。

Description

用来改善后端生产线结构 稳定性的混合介质结构
本发明涉及到集成电路上的多层共面互连结构，更确切地说是涉及到用来改善后端生产线结构稳定性的混合介质结构。
集成电路密度的不断改进部分地是由互连技术的进步造成的。IC制造通常包括前部生产线(FEOL)工艺和后部生产线(BEOL)工艺。FEOL工艺涉及到与多晶硅栅层一起制作晶体管和电容器等。BEOL工艺包括制作金属互连和相关的介质的工艺。常规的互连结构采用铝作为导体。铝被淀积成薄膜，然后被图形化以形成互连。再加入介电绝缘材料，并对其进行平面化。
近来已经开发了使用铜互连的工艺。一种这样的工艺采用镶嵌铜电镀来进行芯片互连。此工艺一开始制作平面绝缘层。对此绝缘层进行腐蚀以形成沟槽或通孔，然后用金属填充沟槽或通孔，并抛光以便整平。在双重镶嵌工艺中，二种图形被组合成一个。
从铝互连过渡到铜互连，已经导致了互连电阻降低。为了降低RC噪声，目前将具有低介电常数(也称为“低k”)的介电材料集成到BEOL结构中。然而，低k介电材料本质上通常不是结构性的。它们无法支持金属丝键合或球键合过程中遇到的外加负载而不对器件的电学可靠性造成有害的影响。但随着工业界将具有高弹性模量的石英改变为用作电介质的低模量材料，这些改变是必需要着手考虑的。
本发明的目的是以新颖而简单的方法来克服上述的一个或多个问题。
根据本发明，采用低k介电材料的混合介电互连结构，在最容易出现噪声的线路层中使用低模量介电材料，而在通孔层中使用性质上是结构性的较高弹性模量的介电材料。
广义地说，此处公开了集成电路芯片上的一种多层共面互连结构，它包括具有被介电常数较低且弹性模量也较低的介电材料分隔的多个互连导体的平面线路层。平面通孔层包含弹性模量比线路层更高的介电膜和穿过其中的导电通孔。线路层和通孔层之一位于集成电路衬底上并确定第一层，而线路层和通孔层中的另一个位于第一层上，使通孔选择性地接触到线路层导体。
本发明的一个特点是介电膜具有较低的介电常数。
本发明的另一特点是介电材料具有小于大约3.0的介电常数。
本发明的另一特点是介电材料包含聚亚芳基醚材料。
本发明的又一特点是介电材料包含有机或无机材料。介电膜包含无机薄膜。
本发明的再一特点是介电膜包含SiCOH膜。
根据本发明的另一种情况，公开了集成电路芯片上的一种多层共面铜镶嵌互连结构，它包括集成电路衬底上的具有被介电常数较低且弹性模量也较低的介电材料分隔的多个线路导体的第一平面互连层。第一平面互连层上的第二平面互连层包含弹性模量比第一平面互连层更高的介电膜和穿过其中的导电通孔。通孔选择性地接触到线路导体。第二平面互连层上的第三平面互连层具有被介电材料分隔并选择性地接触到通孔的多个线路导体。
根据本发明的另一种情况，公开了集成电路芯片上的一种多层共面互连结构，它包括具有被介电常数较低的有机或无机介电材料分隔的多个互连导体的平面线路层。平面通孔层包含介电常数较低的无机介电膜和穿过其中的导电通孔。线路层和通孔层之一位于集成电路衬底上并确定第一层，而线路层和通孔层中的另一个位于第一层上，使通孔选择性地接触到线路层导体。
从说明书和附图可以容易地明白本发明的进一步特点和优点。
图1剖面图示出了用于集成电路芯片上的根据本发明的多层共面互连结构；而
图2-4示出了制造图1的互连结构的工艺。
由于铜互连的形状比随下一代器件而增大，故线路之间的交叉串扰最容易出现在同一个线路层上的各个线路之间，而比较不容易出现在不同线路层即跨越通孔层的电容上的各个线路之间。根据本发明，具有低k介电常数的介电材料分隔了给定线路层上的各个线路。在铜密度不重要的通孔层处，利用模量比较高的介电材料提高了通孔层处的稳定性。
一开始参照图1，示出了集成电路芯片10，它具有根据本发明的多层共面互连结构12。此互连结构包括衬底16上的第一平面层14。第二平面层18位于第一平面层14上。最后，第三平面层20位于第二平面层18上。
衬底16包含具有下方电子器件的硅集成电路。第一平面层14包含线路层。第二平面层18包含通孔层。第三平面层20包含线路层。
线路层14和20具有多个被介电材料24分隔的互连导体22。通孔层18包含具有多个穿过其中的导电通孔28的介电膜26。通孔28选择性地与某些导体22接触。显然，特定的连接根据需要由集成电路芯片10的设计来确定。
根据本发明，线路层14和20中的介电材料24包含低k和低弹性模量的电介质。通孔层18中的介电膜26具有中等程度的低k介电常数和更高的弹性模量。用于集成电路的常规介电材料是二氧化硅，其介电常数k=4.0，而弹性模量约为75GPa。在本发明的示例性实施例中，线路层14和20处的介电常数低于4.0，最好是低于3.0，而弹性模量小于20GPa。在本发明的示例性实施例中，介电材料24可以包含从Dow Chemical Company得到的SiLK半导体介电树脂。SiLK是一种旋涂在有机材料上固化形成绝缘膜的聚亚芳基醚。作为变通，介电材料24可以是无机材料。SiLK具有k=2.65的介电常数。介电膜26可以包含例如诸如介电常数为k=2.7的SiCOH之类的无机薄膜。根据本发明，包括SiO2的介电常数更高的材料能够被用于通孔层18中的膜26。但k更高的材料不被用于线路层14或20。
参照图2-4，示出了制作互连结构12的工艺。图2示出了衬底16，它包括其上含有线路层的第一层14。层14包括一个铜互连导体22和介电材料24。在本发明的示例性实施例中，如上所述，介电材料24包含旋涂并固化形成绝缘膜的SiLK。然后用常规铜镶嵌工艺制作互连线路导体22。势垒层30覆盖着第一层14。然后用等离子体增强化学汽相淀积(PECVD)SiCOH的方法，在第一层14上淀积无机介电薄膜26。再用常规的图形化和腐蚀方法制作通孔窗口32。
参照图3，SiLK介电材料24被旋涂并固化。如所示，可以在通孔窗口32中制作空腔34。在SiLK24的顶部制作硬掩模覆盖层36，然后根据待要制作的导体线路图形，对光刻胶层38进行图形化。参照图4，进行SiLK腐蚀，以清除未图形化的区域中的SiLK介电材料24。一种不同的气体被用来清除通孔窗口32下方的势垒层30。然后可以用双重镶嵌工艺，对通孔层18处的导电通孔28和第三平面层20中的线路导体22进行电镀。
显然，互连结构12能够使用额外的线路层和/或通孔层。同样，根据芯片的需要，第一层可以是通孔层，而第二层可以是线路层，等等。
于是，本发明的特别目的是使用具有铜镶嵌互连的双重低介电常数材料。各个电介质被用于淀积在平面表面上的平面膜中。平面层上互连之间的各个间隙，不管间距如何，都用相同的低k材料填充。不同电介质之间的所有界面都是纯水平的。根据本发明，k更高的材料可以用于通孔层处，但不用于互连导体之间。

Claims (18)

1．集成电路芯片上的一种多层共面互连结构，它包含：
具有被介电常数较低且弹性模量也较低的介电材料分隔的多个互连导体的平面线路层；以及
包含弹性模量比线路层更高的介电膜和穿过其中的导电通孔的平面通孔层，其中
线路层和通孔层之一位于集成电路衬底上并确定第一层，而线路层和通孔层中的另一个位于第一层上，使通孔选择性地接触到线路层导体。
2．权利要求1的多层共面互连结构，其中的介电膜具有较低的介电常数。
3．权利要求1的多层共面互连结构，其中的介电材料的介电常数小于大约3.0。
4．权利要求1的多层共面互连结构，其中的介电材料包含聚亚芳基醚材料。
5．权利要求1的多层共面互连结构，其中的介电材料包含有机材料。
6．权利要求1的多层共面互连结构，其中的介电膜包含无机薄膜。
7．权利要求1的多层共面互连结构，其中的介电膜包含SiCOH膜。
8．集成电路芯片上的一种多层共面铜镶嵌互连结构，它包含：
集成电路衬底上的具有被介电常数较低且弹性模量也较低的介电材料分隔的多个线路导体的第一平面互连层；
第一平面互连层上的包含弹性模量比第一平面互连层更高的介电膜和穿过其中的导电通孔的第二平面互连层，通孔选择性地接触到线路导体；以及
第二平面互连层上的具有被介电材料分隔并选择性地接触到通孔的多个线路导体的第三平面互连层。
9．权利要求8的多层共面镶嵌互连结构，其中的介电膜具有较低的介电常数。
10．权利要求8的多层共面镶嵌互连结构，其中的介电材料的介电常数小于大约3.0。
11．权利要求8的多层共面镶嵌互连结构，其中的介电材料包含聚亚芳基醚材料。
12．权利要求8的多层共面镶嵌互连结构，其中的介电材料包含有机材料。
13．权利要求8的多层共面镶嵌互连结构，其中的介电膜包含无机薄膜。
14．权利要求8的多层共面镶嵌互连结构，其中的介电膜包含SiCOH膜。
15．集成电路芯片上的一种多层共面互连结构，它包含：
具有被介电常数较低的介电材料分隔的多个互连导体的平面线路层；以及
包含介电常数较低的无机介电膜和穿过其中的导电通孔的平面通孔层，其中
线路层和通孔层之一位于集成电路衬底上并确定第一层，而线路层和通孔层中的另一个位于第一层上，使通孔选择性地接触到线路层导体。
16．权利要求15的多层共面互连结构，其中的介电材料具有比介电膜更低的弹性模量。
17．权利要求15的多层共面互连结构，其中的介电材料和介电膜的介电常数均小于大约3.0。
18．权利要求16的多层共面互连结构，其中的介电材料的弹性模量小于20GPa。
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