TWI251274B - Process for transferring thin semiconductor layers and process for obtaining a donor wafer for such a transfer process - Google Patents

Process for transferring thin semiconductor layers and process for obtaining a donor wafer for such a transfer process Download PDF

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TWI251274B
TWI251274B TW091136755A TW91136755A TWI251274B TW I251274 B TWI251274 B TW I251274B TW 091136755 A TW091136755 A TW 091136755A TW 91136755 A TW91136755 A TW 91136755A TW I251274 B TWI251274 B TW I251274B
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layer
wafer
donor
support
semiconductor material
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TW200305208A (en
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Fabrice Letertre
Thibaut Maurice
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Soitec Silicon On Insulator
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/20—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy
    • H01L21/2003—Deposition of semiconductor materials on a substrate, e.g. epitaxial growth solid phase epitaxy characterised by the substrate
    • H01L21/2007—Bonding of semiconductor wafers to insulating substrates or to semiconducting substrates using an intermediate insulating layer
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76251—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology using bonding techniques
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/954—Making oxide-nitride-oxide device
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S438/00—Semiconductor device manufacturing: process
    • Y10S438/964—Roughened surface

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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Recrystallisation Techniques (AREA)
  • Crystals, And After-Treatments Of Crystals (AREA)
  • Container, Conveyance, Adherence, Positioning, Of Wafer (AREA)

Description

1251274 A7 五、發明說明（i) 發明所屬技術領域 、，本發明概與半導體基板製造有關，尤其與供電子、 光電或光學工業用者有關。 更特別口 t本發明與兩晶圓之組件之生產有關， 5 其中至少一係半導體。 先前技術 一般來說’在上述領域中，此組件受分子黏著或晶圓接合 之影響，且在此組合操作後，歷經—定數量之技術步驟，以產 生電路或元件。 10 特別言之，在智慧切割（登記註冊商標）型基板製造期 中，包含於主體施體晶圓中之受控深度處佈植氣體種，以產生 弱區，並施加應力使得弱區處一端分離，在此分離後，施行多 種操作，尤其是： 15 在施體晶圓上施行力學、化學力學或其它抛光步驟，以回 收後者； 化學清洗步驟，· 具相當高溫之步驟，—般在· s ，諸如氧化物沉 經濟部智慧財產局員工消費合作社印制衣 積步驟，或為大致較高之溫度，一般在1150 其是在碳化石夕S1C晶圓之情況下）； 20 佈植一或多種氣體種之步驟； 晶圓接合步驟；及 施加應力之分離步驟（熱及/或力學及/或其它應力）。 ▲施體晶圓之回收需要薄層後端之相繼移除，藉以持續降低 该晶圓厚度。 本紙張尺度適用中國國家標準(CNS)A4規格（21〇 χ 297公釐: 1251274 A7
曰门體晶圓過㈣，或若在層移除前，不論何因，啟始 曰曰圓已相當料，其在供後續移除操作之用上，有下列困難： 、，在諸如隨所需之各種轉移操作、藉由表面氧化物之
CMP 平坦“接合㈣著之力學步驟_，具摘裂風險； 5 ^溫熱處理期間，亦具高斷裂風險，尤其因為晶圓中溫 度不均勻所致； 由操作員施行之鮮晶_持，亦具斷裂風險； 薄晶圓對導致晶圓中應變之特定技術步驟特別敏感，諸如 佈植氣體種倾祕定沉積步驟；—般在雜纽種之情況 1〇下，涛晶圓顯著下彎，造成凸起輪廓；此下彎嚴重累及需要接 觸表面具妥適平坦度之鑄造操作。 故具有&體晶圓厚度之健，不足即不堪使用，或者導致 此々不利於製造處理之斷裂，尤以自經濟觀財量為最。 具體言之，在施體晶圓係由_種相#昂#且易碎之材料 is Sic製成之情況下，晶圓薄至約2〇〇微米時（在晶圓標準直徑 ^ 2 口寸’亦即約5公分之情況下），即因處理過於頻繁期間之 斷裂或因在適當接合前採取後續佈植導致下彎而不堪使用。 經濟部智慧財產局員工消費合作社印制衣 依另一fe例，在啟始時，具有對低厚度施體晶圓之需求。 故目前在市場上，具有厚度足以不導致上述問題之㈣施體晶 %圓。現行施行實際上係在蠢晶後即移除之蠢晶長成基板（種核 層）上’以稱之為HPVE (混合氣相蠢晶）n曰曰技術產生 曰曰圓。但此技術具兩大缺失··首先，其僅得以獲得厚度至多約 200至300微米之自行支撐晶圓，因為若欲具較高厚度，則因 與種核基板之晶格匹配之不完美而產生過度應變；再者，且最
1251274 A7
重要處在於利用此技術之長成速率極低（一般每小時為10至 100微米）。對製造成本而言係一嚴重阻礙。 發明内容 本發明之主要目的在去除這些缺點，並提供自施體 晶圓移除連續薄層之方法，即使在材料厚度非常薄時， 自施體晶圓移除層之操作中，亦可採用。 故依第-態樣’本發明提供—種自施體之半導體材 料轉變連續薄層至接收晶圓之方法，特徵在於豆包括下 列步驟： / 10 (a)組合-由半導體材料組成之主體薄片及一支 樓，俾形成構成該施體晶圓之_力學穩定組件，其包括 具該半導體材料之一施體層及一支標芦· ⑴於該施體層中之一受控深度處產生—弱區· ⑷經由該施體晶圓之該施體層之自由側接：該施 15 體晶圓至該接收晶圓； (d )造成該施體層之該弱區中 T之刀離，因而將該 經濟部智慧財產局員工消費合作社印製 半導體材料之-薄層自該施體晶圓轉變至該圓； 及
u)在不破壞該施體晶圓之該支撐層 20 操作（b)至（d)。 P 其較佳但不以之為限，上述方法之特徵如後： 步驟（a)之施行係藉由在該主體每 ’片與錢撐抛光表面 間之晶圓接合為之； 步驟（a)之施行係藉由在該主體键 _5艰4片與錢撐之拋光表面 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） 1251274 A7 發明說明（4) 間之高溫焊接為之； 步驟（b)之施行係藉由佈植氣體種為之； 步驟（c)之施行係藉由晶圓接合為之； 步驟（d)之施行係藉由施加應力為之，尤其是熱及/或力 學應力； 視該施體層之厚度及該弱區之深度，施行所選之最高次數 重複步驟（a)至（d); 該半導體材料係一單晶半導體，及該支撐係選自包括與一 "口質較差之之單晶相同半導體、多晶型式之相同半導體及與一 10不同多晶型態之相同半導體之群中； 该半導體材料係選自包括矽、碳化矽及大能帶隙單晶金屬 或多晶金屬氮化物； 該施體層厚約100至300微米； 該支撐層厚約100至300微米； 该半導體材料係一大能帶隙單晶金屬或多晶金屬氮化物， 尤其是氮化鎵； 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 该支撐層係一主體層，並係由取自一包括矽、氮化鎵、碳 化矽、氮化鋁及藍寶石之群中之材料產生。 此外，習知自一晶碇產生主體施體晶圓之技術一般需要 20 (在單晶Sic之情況下）下列操作步驟： 利用一鋸切割該晶碇為後約1毫米之薄片； 對該薄片之各面粗略拋光，以移除割鋸造成之晶體損傷， 並獲得良好平坦度；及 對未來的正面（移除面）連續拋光，以消除工作硬化晶
經濟部智慧財產局員工消費合作社印製 1251274 Α7 丨丨丨1 - _B7_ 五、發明說明Y77 '~- 體，並獲得適當之表面粗糙度。 故此，於相當厚之薄片之已知方法，包含在連續拋光步驟 期間之大量材料損失。明顯影響製造成本。 本毛明之另一恶樣目的在於產生損失較低之施體晶圓，並 5因而更利於供作啟始材料之用（在此情況下為單晶％)。 、依此第—態樣，本發明因而提供_種產生施體晶圓之方 法，其係欲供將來自-紐晶圓之—給定半導體材料之連續薄 曰轉4為接收晶圓之方法，特徵在於其包括下列步驟·· (0產生該半導體材料之一主體薄片； U)組合該主體薄片與—支撐，俾形成該施體晶圓，後 者包括該半導體材料之一施體層及一支撐層。 上述方法之特徵如後較佳，但不以之為限： 猎由麟-晶磓或在—種核層上之厚膜蟲晶產生主體薄 片； 15 在後者情況下，包含移除該種核層之步驟； 該方法在步驟（ii)前尚包含下列步驟： :(〇僅於欲使該主體薄層與該支撐接觸之面上抛光·， 該方法在步驟（ii)前尚包含下列步驟： (〇將欲互相接觸之該主體薄片之面與該支擇之面抛光 20至-律定程度，及在步驟（η)中以一溫度施行一段時間，俾 於該主體薄片與該支撐間達成晶圓接合或焊接； α該半導體材_-單晶半導體，及該支撐係選自包括與一 質車乂差之單晶相同之半導體、多晶型式之相同半導體及與一 不同多晶型態之相同半導體之群中；
1251274 、發明說明（6) 5 10 15 經濟部智慧財產局員工消費合作社印製 20 或多晶金屬氮化物^自包妙、碳化石夕及大能帶隙單晶金屬尤其=1^材料係—大能帶隙單晶金屬或多晶金屬氣化物， ，支擇層係-主體層，並係由取自—包括秒、氮化錄、石炭 化石夕、氮尬及藍寶石之群中之材料產生； 實施方式 現將描述本發明之方法德略情況。 _ ^啟始施體晶目供移除連續騎之方法使用前，藉由組合 :體;#片及力學上之支龍而形成此施體晶圓。藉由晶圓 接5施行歧«作触，其胁妥胁施_狀/或力學支 樓體上，以適當之介面接合層為之。 選擇力學支撐體使其與自施體薄片移除薄層之連續步驟所 為之處理相容，並以溫度為最適宜。 在此觀點上’施體薄片材料及力學支撐體之熱膨脹係數間 關係成為-重要„。首先，”均該件，，可不盡侧，亦即施 體層與支撐層之材料似化學及力學师。其將可為例如下 列材料層： 在低品質單晶或多晶SlC (支樓）上之單晶如（施體）； 在低。口貝單晶或多晶GaN (支禮）上之單晶㈣（施 體）；及 在低°口貝單晶或多晶Si (支撐）上之單晶Si (施體）。 在此情況下，特別具由與為產生施體晶圓所需熱量有關之 限制’因為該兩材料具良好祕配，且施體層料受擴散等干 -8- 本紙張尺度適用中國國家標準(CNS)A4規格（210x297公釐） 1251274
擾。 接著’”異質組件”可不盡相同’施體層與支撐層之材料具 相異化學及/或力學性質。其將為例如下列材料層： ’八 在Si (支撐）上之單晶SiC (施體）； 5 在Si上之磷化銦InP ; 在Si上之GaN ; 類此等等。 在此情況下，該組件暴露之熱預算或溫度更為限制，因為 熱不匹配會造成形變或斷裂。以在Si (支撐）上之單曰sic 】〇 (施體）所製施體晶圓情況為例，困難係肇因於溫度:勒 另-重要因素在於所產生之施體/支揮體組件厚度須與方法 步驟相符’並使其至多可消耗所有或大部分之施體薄片。 15 只要已施行接合且若需以適當處理強化，則此組件成為準 備女當之碰晶®，其於移除騎之連續方法操作_，仿若 ^知主體《般厚辆勻。基本上依鋪層厚度及弱區深 又選擇欲移除之薄層數，使得最終移除不受伸及之支擇層影 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 =且無任何缺陷區，所伸及之施體層與支撐層間過渡處與既 存者亦為類似。 2〇 *2有所需i财組合操作完成時，可使施❹圓背面（在 =曰側上）肖化，俾調整晶圓厚度並使其與下游技術步驟及 :能之標準相符。例如當支縣係卿製成時，此薄化步驟極 易以力學拋光研磨方式為之。 範例1-SiC!情、:斤， •9- 本紙張尺度適时規格（210x297公爱) 1251274 A7
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雇 I I 1251274 A7 - B7 五、f月說明（9) ~'~"-— 使此被抛光面與多晶SiC支撐晶圓具適當平坦度之面緊密 接觸，俾以晶圓接合將之接合；支撐晶圓―般係由cvd式厚 膜沉積產生，厚度約為例如勘i遍微米；應注意低品質 (因而不貴）單晶sic，或與施體層（例如6H Sic支擇及4H 5 SiC施體層）相異之多晶型Sic，亦可供做支撐之用； 接著將組件暴露於適當熱預算中（例如在u〇〇〇c下2小 時），俾使薄片與支撐晶圓間獲得適當接合力；接觸面之拋光 程度亦應納入考量，俾於前述條件下，獲得符合需求之晶圓接 合；因而可獲得單一厚度單晶Sic (施體層）/多晶Sic (力學 1〇支撐層）組合晶圓；做為一變體，亦可簡單將晶圓互相疊置， 並以焊接方式接合之（一般在2〇〇〇。(：或更高溫度下）；但此係 屬額外要求； 接著將此組合晶圓於單晶SiC之自由面上以標準程度拋光 將之拋光，俾止於不具嵌入硬化工作區且具適當表面粗糙度之 15 早晶SiC。 經濟部智慧財產局員工消費合作社印製 與利用主體薄片之介紹中所述技術相較，此方法因而得以 產生具極少昂貴材料（單晶sic)損失之施體晶圓，此外，其 在晶圓生產線之極上游即組合施體層與支撐，故對自施體晶圓 轉變層之方法並無影響。 20 所達成之節省在產生SiC晶碇（尤其是藉由HTCVD (高 溫化學氣相沉積）所得之極高純度半絕緣Sic晶碇）方法，或 產生具諸如錯位及微管等極低本質晶體缺陷濃度之sic晶碇愈 困難及/或愈昂貴處，愈為顯著。 範例2-GaN情況 -11- 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公爱） !251274 A7
在對GaN施體晶圓採用智慧切割技術之情況下，所採行之 各種步驟包含-般而言，遠低於SlC中面臨之溫度。故支撑與 知體晶圓之各熱膨脹係數問題即可略之。使得對支撐材料之選 擇具彈性。 5 .在本範例中，厚度約100至2〇〇微米之GaN薄片係接合至 例如多晶或單晶s】c製之力學支撐體。與SlC中之情況類似， 事先決定欲使GaN晶圓置於支撐側上之面之極性，因此，在自 由側上之晶圓之面（亦即在層被移除之側上）具相反極性。 此處之支撐層/GaN施體層組件再度成為所使用之準備妥當 10之晶圓，直到施體層已完全或近乎完全在智慧切割方法之各製 程中被消耗殆盡。 於圖式之圖la至le概略圖示本發明。 圖la中所示係將形成連續轉變薄層之半導體材料薄片 10，及支撐層20。 15 在圖1b中，如所述組合薄片及支撐晶圓，以形成包括施體 層10及支撐層20之施體晶圓30。 在圖lc中’肷入之弱區12係於自施體層1〇之自由表面之 經濟部智慧財產局員工消費合作社印制衣 一定深度處形成，此區12界定與施體層1〇之殘餘體ι〇2有關 之薄層101。 20 在圖Id中，晶圓接合係於施體層1〇之自由表面（若有所 需，在此面上具先前氧化）與接收晶圓40之一面（若有所 需，在此面上具先前氧化）間施行。 在圖le中，於弱區12處施行分離，尤其是採用熱及/或力 學應力者，俾一方面獲得所需組成40、101，其—般形成供電 -12- 本紙張尺度適用中國國家標準(CNS)A4規格（21〇x297公爱） 1251274
5 10 15 子光迅或光子應用之基板；另一方面，獲得施體晶圓3〇,， 其施體層ίο基本上係與區撤對應，並已為轉變之薄層ι〇ι 厚度大幅薄化。 可對施體晶圓30,重複這些步驟，直到以近乎完全消耗施 體層10，不論如何將支撐層2〇拉削均然。 爲給定一特定範例，可於施體晶圓製造商之場地施行圖la 至le中步驟’而下列步驟可構成在供電子、光電及光學業界 用之合成基板之製造商之場地上施行之個別方法之一部分。 無庸置疑地，本發明適用於生產包括其它材料製之施體層 之晶圓，諸如氮化!S、更廣義為半導體；尤其是大能帶隙、單 晶金屬或多晶金屬氮化物、鑽石等；或為極高品質之單晶石夕施 體層及低品質卓晶或多晶秒支樓。 圖式之簡單說明 閱讀以上本發明之施行之較佳方法之詳細描述，即更易於 了解本發明之進—倾徵、目的及優點，該描述储由非限制 性_並參考隨關式—，其帽la_le概略圖示依本發明 轉變薄層之方法。 經濟部智慧財產局員工消費合作社印制衣 10薄片 20支撐晶圓 40接收晶圓 102殘餘體 圖式之代號說明 12弱區 30施體晶圓 101薄層 13- 本紙張尺度適用中國國家標i^(CNS)A4 *^7ΐΐ〇
X 297公釐）

Claims (1)

  1. A8 B8 C8 D8 經濟部智慧財產局員工消費合作社印製 1251274 六、申請專利範圍 1. 一種轉變來自一施體晶圓之一半導體材料之連續薄層 為一接收晶圓之方法，包括下列步驟： (a) 組合一由半導體材料組成之主體薄片及一支 撐，俾形成構成該施體晶圓且包括具該半導體材料之一 5 施體層之一力學穩定組件及一支撐層； (b) 於該施體層中之一受控深度處產生一弱區； (c) 經由該施體層之自由側接合該施體晶圓至該接 收晶圓， (d) 造成該施體層之該弱區中之分離，因而將該半 10 導體材料之一薄層自該施體晶圓轉變至該接收晶圓；及 (e) 在不破壞該施體晶圓之該支撐層下，重複操作 (b)至⑷。 2. 如申請專利範圍第1項之方法，特徵在於步驟⑷之施行 係藉由在該主體薄片與該支撐之拋光表面間之晶圓接 15 合為之。 3. 如申請專利範圍第1項之方法，特徵在於步驟(a)之施行 係藉由在該主體薄片與該支撐之拋光表面間之高溫焊 接為之。 4. 如申請專利範圍第1項之方法，特徵在於步驟(b)之施行 20 係藉由佈植氣體種為之。 5. 如申請專利範圍第1項之方法，特徵在於步驟(c)之施行 係精由晶圓接合為之。 6. 如申請專利範圍第1項之方法，特徵在於步驟(d)之施行 係藉由施加應力為之，尤其是熱及/或力學應力。 -14 -
    本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） 1251274 、申請專利範圍 10 15 經濟部智慧財產局員工消費合作社印製 20 7·如申請專利範圍第！項之方法 厚度及該弱區之深度，以—所選^ =該施體層之 (a)至(d)。 斤k之取鬲二人數重覆步驟 項之方法，特徵 係-早晶半導體，及該支撐 *體材科 導體之品質較差之單曰 ，匕/、一相同之半 -不同夕曰^t 相同半導體之多晶型式及與 夕日日ι恶之相同半導體之群中。 9 ㈣8項之方法’特徵在於該半導體材料 屬敗化^反化石夕及大能帶隙單晶金屬或多晶金 1〇·如申晴專利範圍第9項之方法，特徵在於該施體層厚约 100至300微米。 11.如申請專利範圍第9或10項之方法，特徵在於該支撐層 厚約100至300微米。 &如申請專利範圍第！項之方法，特徵在於該半導體材料 係-大能帶隙單晶金屬或多晶金屬氣化物，尤其是氮 化鎵。 13·如申請專利範圍第12項之方法，特徵在於該支撐層係 一主體層，並係由取自一包括矽、氮化鎵、碳化矽、 氮化鋁及藍寶石之群中之材料產生。 14· 一種產生施體晶圓之方法，其係欲供將來自一施體晶 圓之一給定半導體材料之連續薄層轉變為一接收晶圓 之方法，特徵在於其包括下列步驟： (i)產生該半導體材料之一主體薄片； 裝 計 線 -15 - 本紙張尺度適用中國國家標準(CNS)A4規格（21〇 X 297公釐） 1251274 A8 B8 C8 D8 六、申請專利範圍 (ii)組合該主體薄片與一支撐，俾形成該施體晶 圓，後者包括該半導體材料之一施體層及一支撐層。 15.如申請專利範圍第14項之方法，特徵在於該主體薄片 係藉由割鋸一晶磓產生。 5 16.如申請專利範圍第14項之方法，特徵在於該主體薄片 係藉由在一種核層上之厚膜磊晶產生。 17. 如申請專利範圍第16項之方法，特徵在於其包含一移 除該種核層之步驟。 18. 如申請專利範圍第14項之方法，特徵在於其在步驟(ii) 10 前尚包含下列步驟： (i’）僅於欲使該主體薄層與該支撐接觸之面上拋 光。 19. 如申請專利範圍第14項之方法，特徵在於其在步驟(ii) 前尚包含下列步驟： 15 (ii’)將欲互相接觸之該主體薄片之面與該支撐之面 拋光至一律定程度，及在步驟(ii)中以一溫度施行一時 間，俾於該主體薄片與該支撐間達成晶圓接合或焊接。 經濟部智慧財產局員工消費合作社印製 20. 如申請專利範圍第14項之方法，特徵在於該半導體材 料係一單晶半導體，及該支撐係選自包括與一品質較 20 差相同之半導體之單晶、相同半導體之多晶型式和一 不同多晶型態之相同半導體之群中。 21. 如申請專利範圍第20項之方法，特徵在於該半導體材 料係選自包括矽、碳化矽及大能帶隙單晶金屬或多晶 金屬氮化物。 -16 - 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐） 1251274 as B8 C8 ___D8_ 六、申請專利範圍 22. 如申請專利範圍第14項之方法，特徵在於該半導體材 料係一大能帶隙單晶金屬或多晶金屬氮化物，尤其是 氮化鎵。 23. 如申請專利範圍第14項之方法，特徵在於該支撐層係 5 一主體層，並係由取自一包括矽、氮化鎵、峻化矽、 氮化鋁和藍寶石之群中之材料產生。 經濟部智慧財產局員工消費合作社印製 7 本紙張尺度適用中國國家標準(CNS)A4規格（210 X 297公釐）
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Families Citing this family (229)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050026432A1 (en) * 2001-04-17 2005-02-03 Atwater Harry A. Wafer bonded epitaxial templates for silicon heterostructures
CA2482258A1 (en) 2001-04-17 2002-10-24 California Institute Of Technology A method of using a germanium layer transfer to si for photovoltaic applications and heterostructure made thereby
US7238622B2 (en) * 2001-04-17 2007-07-03 California Institute Of Technology Wafer bonded virtual substrate and method for forming the same
SE525574C2 (sv) 2002-08-30 2005-03-15 Okmetic Oyj Lågdopat kiselkarbidsubstrat och användning därav i högspänningskomponenter
TWI233154B (en) * 2002-12-06 2005-05-21 Soitec Silicon On Insulator Method for recycling a substrate
US20040262686A1 (en) * 2003-06-26 2004-12-30 Mohamad Shaheen Layer transfer technique
FR2858715B1 (fr) * 2003-08-04 2005-12-30 Soitec Silicon On Insulator Procede de detachement de couche de semiconducteur
FR2858875B1 (fr) * 2003-08-12 2006-02-10 Soitec Silicon On Insulator Procede de realisation de couches minces de materiau semi-conducteur a partir d'une plaquette donneuse
US20050070048A1 (en) * 2003-09-25 2005-03-31 Tolchinsky Peter G. Devices and methods employing high thermal conductivity heat dissipation substrates
FR2864970B1 (fr) * 2004-01-09 2006-03-03 Soitec Silicon On Insulator Substrat a support a coefficient de dilatation thermique determine
US7390724B2 (en) * 2004-04-12 2008-06-24 Silicon Genesis Corporation Method and system for lattice space engineering
WO2005104192A2 (en) * 2004-04-21 2005-11-03 California Institute Of Technology A METHOD FOR THE FABRICATION OF GaAs/Si AND RELATED WAFER BONDED VIRTUAL SUBSTRATES
US9011598B2 (en) * 2004-06-03 2015-04-21 Soitec Method for making a composite substrate and composite substrate according to the method
FR2871172B1 (fr) * 2004-06-03 2006-09-22 Soitec Silicon On Insulator Support d'epitaxie hybride et son procede de fabrication
WO2006015185A2 (en) * 2004-07-30 2006-02-09 Aonex Technologies, Inc. GaInP/GaAs/Si TRIPLE JUNCTION SOLAR CELL ENABLED BY WAFER BONDING AND LAYER TRANSFER
WO2006037783A1 (fr) * 2004-10-04 2006-04-13 S.O.I.Tec Silicon On Insulator Technologies Procédé de transfert d'une couche mince comprenant une perturbation controlée d'une structure cristalline
US7846759B2 (en) * 2004-10-21 2010-12-07 Aonex Technologies, Inc. Multi-junction solar cells and methods of making same using layer transfer and bonding techniques
ATE420461T1 (de) 2004-11-09 2009-01-15 Soitec Silicon On Insulator Verfahren zum herstellen von zusammengesetzten wafern
EP1681712A1 (en) 2005-01-13 2006-07-19 S.O.I. Tec Silicon on Insulator Technologies S.A. Method of producing substrates for optoelectronic applications
FR2880988B1 (fr) * 2005-01-19 2007-03-30 Soitec Silicon On Insulator TRAITEMENT D'UNE COUCHE EN SI1-yGEy PRELEVEE
JP2006210660A (ja) * 2005-01-28 2006-08-10 Hitachi Cable Ltd 半導体基板の製造方法
US10374120B2 (en) * 2005-02-18 2019-08-06 Koninklijke Philips N.V. High efficiency solar cells utilizing wafer bonding and layer transfer to integrate non-lattice matched materials
JP2008532317A (ja) * 2005-02-28 2008-08-14 シリコン・ジェネシス・コーポレーション レイヤ転送プロセス用の基板強化方法および結果のデバイス
US8101498B2 (en) * 2005-04-21 2012-01-24 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
DE102005052358A1 (de) * 2005-09-01 2007-03-15 Osram Opto Semiconductors Gmbh Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement
DE102005052357A1 (de) 2005-09-01 2007-03-15 Osram Opto Semiconductors Gmbh Verfahren zum lateralen Zertrennen eines Halbleiterwafers und optoelektronisches Bauelement
KR100653848B1 (ko) * 2005-09-13 2006-12-05 (주)한비젼 3차원 적층형 이미지 센서 및 그의 제조방법
WO2007032632A1 (en) * 2005-09-13 2007-03-22 Hanvision Co., Ltd. Method of fabricating silicon/dielectric multi-layer semiconductor structures using layer transfer technology and also a three-dimensional multi-layer semiconductor device and stacked layer type image sensor using the same method, and a method of manufacturing a three-dimensional multi- layer semiconductor device and the st
US20070194342A1 (en) * 2006-01-12 2007-08-23 Kinzer Daniel M GaN SEMICONDUCTOR DEVICE AND PROCESS EMPLOYING GaN ON THIN SAPHIRE LAYER ON POLYCRYSTALLINE SILICON CARBIDE
JP5042506B2 (ja) * 2006-02-16 2012-10-03 信越化学工業株式会社 半導体基板の製造方法
FR2899572B1 (fr) * 2006-04-05 2008-09-05 Commissariat Energie Atomique Protection de cavites debouchant sur une face d'un element microstructure
FR2899594A1 (fr) * 2006-04-10 2007-10-12 Commissariat Energie Atomique Procede d'assemblage de substrats avec traitements thermiques a basses temperatures
US20070243703A1 (en) * 2006-04-14 2007-10-18 Aonex Technololgies, Inc. Processes and structures for epitaxial growth on laminate substrates
DE102006061167A1 (de) * 2006-04-25 2007-12-20 Osram Opto Semiconductors Gmbh Optoelektronisches Halbleiterbauelement
JP5003033B2 (ja) * 2006-06-30 2012-08-15 住友電気工業株式会社 ＧａＮ薄膜貼り合わせ基板およびその製造方法、ならびにＧａＮ系半導体デバイスおよびその製造方法
FR2903808B1 (fr) * 2006-07-11 2008-11-28 Soitec Silicon On Insulator Procede de collage direct de deux substrats utilises en electronique, optique ou opto-electronique
FR2914110B1 (fr) * 2007-03-20 2009-06-05 Soitec Silicon On Insulator Procede de fabrication d'un substrat hybride
US7575988B2 (en) 2006-07-11 2009-08-18 S.O.I.Tec Silicon On Insulator Technologies Method of fabricating a hybrid substrate
US7732301B1 (en) 2007-04-20 2010-06-08 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
US20090278233A1 (en) * 2007-07-26 2009-11-12 Pinnington Thomas Henry Bonded intermediate substrate and method of making same
FR2919960B1 (fr) * 2007-08-08 2010-05-21 Soitec Silicon On Insulator Procede et installation pour la fracture d'un substrat composite selon un plan de fragilisation
WO2009063288A1 (en) * 2007-11-15 2009-05-22 S.O.I.Tec Silicon On Insulator Technologies Semiconductor structure having a protective layer
WO2009141724A1 (en) * 2008-05-23 2009-11-26 S.O.I.Tec Silicon On Insulator Technologies Formation of substantially pit free indium gallium nitride
US8236428B2 (en) * 2008-07-10 2012-08-07 Jx Nippon Mining & Metals Corporation Hybrid silicon wafer and method for manufacturing same
US8431419B2 (en) * 2008-08-28 2013-04-30 Soitec UV absorption based monitor and control of chloride gas stream
SG159484A1 (en) * 2008-09-05 2010-03-30 Semiconductor Energy Lab Method of manufacturing soi substrate
JP5667743B2 (ja) * 2008-09-29 2015-02-12 株式会社半導体エネルギー研究所 Ｓｏｉ基板の作製方法
US7927975B2 (en) 2009-02-04 2011-04-19 Micron Technology, Inc. Semiconductor material manufacture
JP5179401B2 (ja) * 2009-02-19 2013-04-10 信越化学工業株式会社 貼り合わせウェーハ及びその製造方法
US8669778B1 (en) * 2009-04-14 2014-03-11 Monolithic 3D Inc. Method for design and manufacturing of a 3D semiconductor device
JP5597933B2 (ja) * 2009-05-01 2014-10-01 住友電気工業株式会社 Ｉｉｉ族窒化物半導体層貼り合わせ基板およびその製造方法
KR20120014017A (ko) * 2009-05-11 2012-02-15 스미토모덴키고교가부시키가이샤 탄화규소 기판, 반도체 장치 및 탄화규소 기판의 제조 방법
US8318588B2 (en) * 2009-08-25 2012-11-27 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
KR101731809B1 (ko) 2009-10-09 2017-05-02 가부시키가이샤 한도오따이 에네루기 켄큐쇼 반도체 기판의 재생 방법, 재생된 반도체 기판의 제조 방법, 및 ｓｏｉ 기판의 제조 방법
US11374118B2 (en) 2009-10-12 2022-06-28 Monolithic 3D Inc. Method to form a 3D integrated circuit
US10366970B2 (en) 2009-10-12 2019-07-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10157909B2 (en) 2009-10-12 2018-12-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10043781B2 (en) 2009-10-12 2018-08-07 Monolithic 3D Inc. 3D semiconductor device and structure
US10910364B2 (en) 2009-10-12 2021-02-02 Monolitaic 3D Inc. 3D semiconductor device
US11018133B2 (en) 2009-10-12 2021-05-25 Monolithic 3D Inc. 3D integrated circuit
US10354995B2 (en) 2009-10-12 2019-07-16 Monolithic 3D Inc. Semiconductor memory device and structure
US10388863B2 (en) 2009-10-12 2019-08-20 Monolithic 3D Inc. 3D memory device and structure
US11984445B2 (en) 2009-10-12 2024-05-14 Monolithic 3D Inc. 3D semiconductor devices and structures with metal layers
EP2562789A4 (en) * 2010-04-20 2015-03-04 Sumitomo Electric Industries PROCESS FOR PRODUCING COMPOSITE SUBSTRATE
US9190560B2 (en) 2010-05-18 2015-11-17 Agency For Science Technology And Research Method of forming a light emitting diode structure and a light diode structure
US10217667B2 (en) 2011-06-28 2019-02-26 Monolithic 3D Inc. 3D semiconductor device, fabrication method and system
US10497713B2 (en) 2010-11-18 2019-12-03 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11482440B2 (en) 2010-12-16 2022-10-25 Monolithic 3D Inc. 3D semiconductor device and structure with a built-in test circuit for repairing faulty circuits
US10896931B1 (en) 2010-10-11 2021-01-19 Monolithic 3D Inc. 3D semiconductor device and structure
US11257867B1 (en) 2010-10-11 2022-02-22 Monolithic 3D Inc. 3D semiconductor device and structure with oxide bonds
US11227897B2 (en) 2010-10-11 2022-01-18 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11600667B1 (en) 2010-10-11 2023-03-07 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US11469271B2 (en) 2010-10-11 2022-10-11 Monolithic 3D Inc. Method to produce 3D semiconductor devices and structures with memory
US10290682B2 (en) 2010-10-11 2019-05-14 Monolithic 3D Inc. 3D IC semiconductor device and structure with stacked memory
US11024673B1 (en) 2010-10-11 2021-06-01 Monolithic 3D Inc. 3D semiconductor device and structure
US11158674B2 (en) 2010-10-11 2021-10-26 Monolithic 3D Inc. Method to produce a 3D semiconductor device and structure
US11315980B1 (en) 2010-10-11 2022-04-26 Monolithic 3D Inc. 3D semiconductor device and structure with transistors
US11018191B1 (en) 2010-10-11 2021-05-25 Monolithic 3D Inc. 3D semiconductor device and structure
US11327227B2 (en) 2010-10-13 2022-05-10 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11164898B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11605663B2 (en) 2010-10-13 2023-03-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11855114B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10679977B2 (en) 2010-10-13 2020-06-09 Monolithic 3D Inc. 3D microdisplay device and structure
US11133344B2 (en) 2010-10-13 2021-09-28 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10998374B1 (en) 2010-10-13 2021-05-04 Monolithic 3D Inc. Multilevel semiconductor device and structure
US10943934B2 (en) 2010-10-13 2021-03-09 Monolithic 3D Inc. Multilevel semiconductor device and structure
US11855100B2 (en) 2010-10-13 2023-12-26 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11043523B1 (en) 2010-10-13 2021-06-22 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US10833108B2 (en) 2010-10-13 2020-11-10 Monolithic 3D Inc. 3D microdisplay device and structure
US11869915B2 (en) 2010-10-13 2024-01-09 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US10978501B1 (en) 2010-10-13 2021-04-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11437368B2 (en) 2010-10-13 2022-09-06 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11929372B2 (en) 2010-10-13 2024-03-12 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors and wafer bonding
US11063071B1 (en) 2010-10-13 2021-07-13 Monolithic 3D Inc. Multilevel semiconductor device and structure with waveguides
US11163112B2 (en) 2010-10-13 2021-11-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with electromagnetic modulators
US11984438B2 (en) 2010-10-13 2024-05-14 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11694922B2 (en) 2010-10-13 2023-07-04 Monolithic 3D Inc. Multilevel semiconductor device and structure with oxide bonding
US11404466B2 (en) 2010-10-13 2022-08-02 Monolithic 3D Inc. Multilevel semiconductor device and structure with image sensors
US11164770B1 (en) 2010-11-18 2021-11-02 Monolithic 3D Inc. Method for producing a 3D semiconductor memory device and structure
US11854857B1 (en) 2010-11-18 2023-12-26 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11615977B2 (en) 2010-11-18 2023-03-28 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11569117B2 (en) 2010-11-18 2023-01-31 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11495484B2 (en) 2010-11-18 2022-11-08 Monolithic 3D Inc. 3D semiconductor devices and structures with at least two single-crystal layers
US11018042B1 (en) 2010-11-18 2021-05-25 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11804396B2 (en) 2010-11-18 2023-10-31 Monolithic 3D Inc. Methods for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11355381B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11521888B2 (en) 2010-11-18 2022-12-06 Monolithic 3D Inc. 3D semiconductor device and structure with high-k metal gate transistors
US11482438B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11121021B2 (en) 2010-11-18 2021-09-14 Monolithic 3D Inc. 3D semiconductor device and structure
US11901210B2 (en) 2010-11-18 2024-02-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11862503B2 (en) 2010-11-18 2024-01-02 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with memory cells and multiple metal layers
US11923230B1 (en) 2010-11-18 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11784082B2 (en) 2010-11-18 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11610802B2 (en) 2010-11-18 2023-03-21 Monolithic 3D Inc. Method for producing a 3D semiconductor device and structure with single crystal transistors and metal gate electrodes
US11508605B2 (en) 2010-11-18 2022-11-22 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11443971B2 (en) 2010-11-18 2022-09-13 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11482439B2 (en) 2010-11-18 2022-10-25 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device comprising charge trap junction-less transistors
US11735462B2 (en) 2010-11-18 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with single-crystal layers
US11094576B1 (en) 2010-11-18 2021-08-17 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11211279B2 (en) 2010-11-18 2021-12-28 Monolithic 3D Inc. Method for processing a 3D integrated circuit and structure
US11355380B2 (en) 2010-11-18 2022-06-07 Monolithic 3D Inc. Methods for producing 3D semiconductor memory device and structure utilizing alignment marks
US11004719B1 (en) 2010-11-18 2021-05-11 Monolithic 3D Inc. Methods for producing a 3D semiconductor memory device and structure
US11031275B2 (en) 2010-11-18 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure with memory
US11107721B2 (en) 2010-11-18 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure with NAND logic
US8436363B2 (en) 2011-02-03 2013-05-07 Soitec Metallic carrier for layer transfer and methods for forming the same
US9142412B2 (en) 2011-02-03 2015-09-22 Soitec Semiconductor devices including substrate layers and overlying semiconductor layers having closely matching coefficients of thermal expansion, and related methods
US9082948B2 (en) 2011-02-03 2015-07-14 Soitec Methods of fabricating semiconductor structures using thermal spray processes, and semiconductor structures fabricated using such methods
JP2011193010A (ja) * 2011-04-28 2011-09-29 Hitachi Cable Ltd 半導体ウェハ及び高周波電子デバイス用半導体ウェハ
US9123529B2 (en) 2011-06-21 2015-09-01 Semiconductor Energy Laboratory Co., Ltd. Method for reprocessing semiconductor substrate, method for manufacturing reprocessed semiconductor substrate, and method for manufacturing SOI substrate
FR2977069B1 (fr) 2011-06-23 2014-02-07 Soitec Silicon On Insulator Procede de fabrication d'une structure semi-conductrice mettant en oeuvre un collage temporaire
US10388568B2 (en) 2011-06-28 2019-08-20 Monolithic 3D Inc. 3D semiconductor device and system
KR20130049484A (ko) * 2011-11-04 2013-05-14 삼성코닝정밀소재 주식회사 박막 접합 기판 제조방법
US11616004B1 (en) 2012-04-09 2023-03-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11410912B2 (en) 2012-04-09 2022-08-09 Monolithic 3D Inc. 3D semiconductor device with vias and isolation layers
US11881443B2 (en) 2012-04-09 2024-01-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11088050B2 (en) 2012-04-09 2021-08-10 Monolithic 3D Inc. 3D semiconductor device with isolation layers
US11735501B1 (en) 2012-04-09 2023-08-22 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11694944B1 (en) 2012-04-09 2023-07-04 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US11164811B2 (en) 2012-04-09 2021-11-02 Monolithic 3D Inc. 3D semiconductor device with isolation layers and oxide-to-oxide bonding
US11594473B2 (en) 2012-04-09 2023-02-28 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and a connective path
US10600888B2 (en) 2012-04-09 2020-03-24 Monolithic 3D Inc. 3D semiconductor device
US11476181B1 (en) 2012-04-09 2022-10-18 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
JP2014007325A (ja) * 2012-06-26 2014-01-16 Sumitomo Electric Ind Ltd 炭化珪素半導体装置の製造方法
FR2995136B1 (fr) 2012-09-04 2015-06-26 Soitec Silicon On Insulator Pseudo-substrat avec efficacite amelioree d'utilisation d'un materiau monocristallin
US11217565B2 (en) 2012-12-22 2022-01-04 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11967583B2 (en) 2012-12-22 2024-04-23 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11784169B2 (en) 2012-12-22 2023-10-10 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11309292B2 (en) 2012-12-22 2022-04-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11916045B2 (en) 2012-12-22 2024-02-27 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11063024B1 (en) 2012-12-22 2021-07-13 Monlithic 3D Inc. Method to form a 3D semiconductor device and structure
US11018116B2 (en) 2012-12-22 2021-05-25 Monolithic 3D Inc. Method to form a 3D semiconductor device and structure
US11961827B1 (en) 2012-12-22 2024-04-16 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US10600657B2 (en) 2012-12-29 2020-03-24 Monolithic 3D Inc 3D semiconductor device and structure
US11430667B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US11087995B1 (en) 2012-12-29 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10115663B2 (en) 2012-12-29 2018-10-30 Monolithic 3D Inc. 3D semiconductor device and structure
US10903089B1 (en) 2012-12-29 2021-01-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11430668B2 (en) 2012-12-29 2022-08-30 Monolithic 3D Inc. 3D semiconductor device and structure with bonding
US10651054B2 (en) 2012-12-29 2020-05-12 Monolithic 3D Inc. 3D semiconductor device and structure
US11177140B2 (en) 2012-12-29 2021-11-16 Monolithic 3D Inc. 3D semiconductor device and structure
US11004694B1 (en) 2012-12-29 2021-05-11 Monolithic 3D Inc. 3D semiconductor device and structure
US10892169B2 (en) 2012-12-29 2021-01-12 Monolithic 3D Inc. 3D semiconductor device and structure
US9875935B2 (en) 2013-03-08 2018-01-23 Infineon Technologies Austria Ag Semiconductor device and method for producing the same
US10325651B2 (en) 2013-03-11 2019-06-18 Monolithic 3D Inc. 3D semiconductor device with stacked memory
US8902663B1 (en) 2013-03-11 2014-12-02 Monolithic 3D Inc. Method of maintaining a memory state
US11935949B1 (en) 2013-03-11 2024-03-19 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11869965B2 (en) 2013-03-11 2024-01-09 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers and memory cells
US11088130B2 (en) 2014-01-28 2021-08-10 Monolithic 3D Inc. 3D semiconductor device and structure
US10840239B2 (en) 2014-08-26 2020-11-17 Monolithic 3D Inc. 3D semiconductor device and structure
US11398569B2 (en) 2013-03-12 2022-07-26 Monolithic 3D Inc. 3D semiconductor device and structure
US11923374B2 (en) 2013-03-12 2024-03-05 Monolithic 3D Inc. 3D semiconductor device and structure with metal layers
US11721547B2 (en) * 2013-03-14 2023-08-08 Infineon Technologies Ag Method for manufacturing a silicon carbide substrate for an electrical silicon carbide device, a silicon carbide substrate and an electrical silicon carbide device
US10224279B2 (en) 2013-03-15 2019-03-05 Monolithic 3D Inc. Semiconductor device and structure
WO2014157430A1 (ja) 2013-03-27 2014-10-02 日本碍子株式会社 半導体用複合基板のハンドル基板
TWI538018B (zh) 2013-03-27 2016-06-11 Ngk Insulators Ltd Semiconductor substrate for composite substrate
US11270055B1 (en) 2013-04-15 2022-03-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US9021414B1 (en) 2013-04-15 2015-04-28 Monolithic 3D Inc. Automation for monolithic 3D devices
US11341309B1 (en) 2013-04-15 2022-05-24 Monolithic 3D Inc. Automation for monolithic 3D devices
US11720736B2 (en) 2013-04-15 2023-08-08 Monolithic 3D Inc. Automation methods for 3D integrated circuits and devices
US11030371B2 (en) 2013-04-15 2021-06-08 Monolithic 3D Inc. Automation for monolithic 3D devices
US11574109B1 (en) 2013-04-15 2023-02-07 Monolithic 3D Inc Automation methods for 3D integrated circuits and devices
US11487928B2 (en) 2013-04-15 2022-11-01 Monolithic 3D Inc. Automation for monolithic 3D devices
TWI629753B (zh) 2013-04-26 2018-07-11 日本碍子股份有限公司 半導體用複合基板之操作基板
JP6347553B2 (ja) * 2013-05-31 2018-06-27 日本碍子株式会社 複合基板用支持基板および複合基板
JP6326487B2 (ja) 2013-06-20 2018-05-16 ストレイティオ， インコーポレイテッドＳｔｒａｔｉｏ， Ｉｎｃ． Ｃｍｏｓ画像センサ用のゲート制御型電荷変調デバイス
JP5697813B1 (ja) 2013-07-18 2015-04-08 日本碍子株式会社 半導体用複合基板のハンドル基板
US9548247B2 (en) * 2013-07-22 2017-01-17 Infineon Technologies Austria Ag Methods for producing semiconductor devices
WO2015084858A1 (en) * 2013-12-02 2015-06-11 Stratio Layer transfer technology for silicon carbide
JP5781254B1 (ja) 2013-12-25 2015-09-16 日本碍子株式会社 ハンドル基板、半導体用複合基板、半導体回路基板およびその製造方法
US10297586B2 (en) 2015-03-09 2019-05-21 Monolithic 3D Inc. Methods for processing a 3D semiconductor device
US11107808B1 (en) 2014-01-28 2021-08-31 Monolithic 3D Inc. 3D semiconductor device and structure
US11031394B1 (en) 2014-01-28 2021-06-08 Monolithic 3D Inc. 3D semiconductor device and structure
JP5849176B1 (ja) 2014-02-12 2016-01-27 日本碍子株式会社 半導体用複合基板のハンドル基板および半導体用複合基板
JP6076486B2 (ja) 2014-02-26 2017-02-08 日本碍子株式会社 半導体用複合基板のハンドル基板
CN105931997B (zh) * 2015-02-27 2019-02-05 胡迪群 暂时性复合式载板
US11011507B1 (en) 2015-04-19 2021-05-18 Monolithic 3D Inc. 3D semiconductor device and structure
US10825779B2 (en) 2015-04-19 2020-11-03 Monolithic 3D Inc. 3D semiconductor device and structure
US11056468B1 (en) 2015-04-19 2021-07-06 Monolithic 3D Inc. 3D semiconductor device and structure
US10381328B2 (en) 2015-04-19 2019-08-13 Monolithic 3D Inc. Semiconductor device and structure
US11956952B2 (en) 2015-08-23 2024-04-09 Monolithic 3D Inc. Semiconductor memory device and structure
US10515981B2 (en) 2015-09-21 2019-12-24 Monolithic 3D Inc. Multilevel semiconductor device and structure with memory
US11978731B2 (en) 2015-09-21 2024-05-07 Monolithic 3D Inc. Method to produce a multi-level semiconductor memory device and structure
US10522225B1 (en) 2015-10-02 2019-12-31 Monolithic 3D Inc. Semiconductor device with non-volatile memory
US11114464B2 (en) 2015-10-24 2021-09-07 Monolithic 3D Inc. 3D semiconductor device and structure
US11296115B1 (en) 2015-10-24 2022-04-05 Monolithic 3D Inc. 3D semiconductor device and structure
US10418369B2 (en) 2015-10-24 2019-09-17 Monolithic 3D Inc. Multi-level semiconductor memory device and structure
US10847540B2 (en) 2015-10-24 2020-11-24 Monolithic 3D Inc. 3D semiconductor memory device and structure
US11991884B1 (en) 2015-10-24 2024-05-21 Monolithic 3D Inc. 3D semiconductor device and structure with logic and memory
US11114427B2 (en) 2015-11-07 2021-09-07 Monolithic 3D Inc. 3D semiconductor processor and memory device and structure
US11937422B2 (en) 2015-11-07 2024-03-19 Monolithic 3D Inc. Semiconductor memory device and structure
CN109478493A (zh) * 2016-07-12 2019-03-15 Qmat股份有限公司 供体衬底进行回收的方法
US20180033609A1 (en) * 2016-07-28 2018-02-01 QMAT, Inc. Removal of non-cleaved/non-transferred material from donor substrate
US20180019169A1 (en) * 2016-07-12 2018-01-18 QMAT, Inc. Backing substrate stabilizing donor substrate for implant or reclamation
US11869591B2 (en) 2016-10-10 2024-01-09 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11812620B2 (en) 2016-10-10 2023-11-07 Monolithic 3D Inc. 3D DRAM memory devices and structures with control circuits
US11251149B2 (en) 2016-10-10 2022-02-15 Monolithic 3D Inc. 3D memory device and structure
US11711928B2 (en) 2016-10-10 2023-07-25 Monolithic 3D Inc. 3D memory devices and structures with control circuits
US11329059B1 (en) 2016-10-10 2022-05-10 Monolithic 3D Inc. 3D memory devices and structures with thinned single crystal substrates
US11930648B1 (en) 2016-10-10 2024-03-12 Monolithic 3D Inc. 3D memory devices and structures with metal layers
FR3068508B1 (fr) * 2017-06-30 2019-07-26 Soitec Procede de transfert d'une couche mince sur un substrat support presentant des coefficients de dilatation thermique differents
FR3076292B1 (fr) * 2017-12-28 2020-01-03 Commissariat A L'energie Atomique Et Aux Energies Alternatives Procede de transfert d'une couche utile sur un substrat support
DE102018111450A1 (de) 2018-05-14 2019-11-14 Infineon Technologies Ag Verfahren zum Verarbeiten eines Breiter-Bandabstand-Halbleiterwafers, Verfahren zum Bilden einer Mehrzahl von dünnen Breiter-Bandabstand-Halbleiterwafern und Breiter-Bandabstand-Halbleiterwafer
CN112956030A (zh) 2018-10-09 2021-06-11 美光科技公司 包含具有增加阈值电压的晶体管的半导体装置及其相关方法与系统
CN109729639B (zh) * 2018-12-24 2020-11-20 奥特斯科技(重庆)有限公司 在无芯基板上包括柱体的部件承载件
US11018156B2 (en) 2019-04-08 2021-05-25 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11763864B2 (en) 2019-04-08 2023-09-19 Monolithic 3D Inc. 3D memory semiconductor devices and structures with bit-line pillars
US11158652B1 (en) 2019-04-08 2021-10-26 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US10892016B1 (en) 2019-04-08 2021-01-12 Monolithic 3D Inc. 3D memory semiconductor devices and structures
US11296106B2 (en) 2019-04-08 2022-04-05 Monolithic 3D Inc. 3D memory semiconductor devices and structures

Family Cites Families (12)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS62179110A (ja) * 1986-02-03 1987-08-06 Toshiba Corp 直接接着型半導体基板の製造方法
ATE97613T1 (de) * 1986-12-09 1993-12-15 Polaroid Corp Thermisches aufzeichnungsmittel.
US4839310A (en) * 1988-01-27 1989-06-13 Massachusetts Institute Of Technology High mobility transistor with opposed-gates
JPH02194519A (ja) * 1989-01-23 1990-08-01 Nippon Telegr & Teleph Corp <Ntt> 複合半導体基板およびその製造方法
US5395788A (en) * 1991-03-15 1995-03-07 Shin Etsu Handotai Co., Ltd. Method of producing semiconductor substrate
JP2726583B2 (ja) * 1991-11-18 1998-03-11 三菱マテリアルシリコン株式会社 半導体基板
JP2856030B2 (ja) * 1993-06-29 1999-02-10 信越半導体株式会社 結合ウエーハの製造方法
US5489539A (en) * 1994-01-10 1996-02-06 Hughes Aircraft Company Method of making quantum well structure with self-aligned gate
US6159824A (en) * 1997-05-12 2000-12-12 Silicon Genesis Corporation Silicon-on-silicon wafer bonding process using a thin film blister-separation method
CN1088541C (zh) * 1998-12-04 2002-07-31 中国科学院上海冶金研究所 以氮化铝为绝缘埋层的绝缘体上的硅材料制备方法
US6326279B1 (en) * 1999-03-26 2001-12-04 Canon Kabushiki Kaisha Process for producing semiconductor article
DE19943101C2 (de) * 1999-09-09 2002-06-20 Wacker Siltronic Halbleitermat Verfahren zur Herstellung einer gebondeten Halbleiterscheibe

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US20040241959A1 (en) 2004-12-02
US20030153163A1 (en) 2003-08-14
US6815309B2 (en) 2004-11-09
FR2834123B1 (fr) 2005-02-04
JP4388741B2 (ja) 2009-12-24
EP1324385A3 (fr) 2003-09-17
US6908828B2 (en) 2005-06-21
CN100426468C (zh) 2008-10-15
TW200305208A (en) 2003-10-16
SG120907A1 (en) 2006-04-26
FR2834123A1 (fr) 2003-06-27

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