TWI231596B - Method for fabricating capacitor in semiconductor device - Google Patents

Method for fabricating capacitor in semiconductor device Download PDF

Info

Publication number
TWI231596B
TWI231596B TW091136874A TW91136874A TWI231596B TW I231596 B TWI231596 B TW I231596B TW 091136874 A TW091136874 A TW 091136874A TW 91136874 A TW91136874 A TW 91136874A TW I231596 B TWI231596 B TW I231596B
Authority
TW
Taiwan
Prior art keywords
layer
dielectric thin
thin film
nitride
forming
Prior art date
Application number
TW091136874A
Other languages
English (en)
Other versions
TW200400616A (en
Inventor
Jong-Bum Park
Hoon-Jung Oh
Kyong-Min Kim
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200400616A publication Critical patent/TW200400616A/zh
Application granted granted Critical
Publication of TWI231596B publication Critical patent/TWI231596B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/02112—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer
    • H01L21/02172—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides
    • H01L21/02175—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal
    • H01L21/02178—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates characterised by the material of the layer the material containing at least one metal element, e.g. metal oxides, metal nitrides, metal oxynitrides or metal carbides characterised by the metal the material containing aluminium, e.g. Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02109—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates
    • H01L21/022—Forming insulating materials on a substrate characterised by the type of layer, e.g. type of material, porous/non-porous, pre-cursors, mixtures or laminates the layer being a laminate, i.e. composed of sublayers, e.g. stacks of alternating high-k metal oxides
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H01L21/02271—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition
    • H01L21/0228—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase deposition by decomposition or reaction of gaseous or vapour phase compounds, i.e. chemical vapour deposition deposition by cyclic CVD, e.g. ALD, ALE, pulsed CVD
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3141—Deposition using atomic layer deposition techniques [ALD]
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/55—Capacitors with a dielectric comprising a perovskite structure material
    • H01L28/56—Capacitors with a dielectric comprising a perovskite structure material the dielectric comprising two or more layers, e.g. comprising buffer layers, seed layers, gradient layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/02227—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process
    • H01L21/02247—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a process other than a deposition process formation by nitridation, e.g. nitridation of the substrate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/02104—Forming layers
    • H01L21/02107—Forming insulating materials on a substrate
    • H01L21/02225—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer
    • H01L21/0226—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process
    • H01L21/02263—Forming insulating materials on a substrate characterised by the process for the formation of the insulating layer formation by a deposition process deposition from the gas or vapour phase
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/3143—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers
    • H01L21/3144—Inorganic layers composed of alternated layers or of mixtures of nitrides and oxides or of oxinitrides, e.g. formation of oxinitride by oxidation of nitride layers on silicon
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31604—Deposition from a gas or vapour
    • H01L21/31616—Deposition of Al2O3
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/3165—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation
    • H01L21/31683—Inorganic layers composed of oxides or glassy oxides or oxide based glass formed by oxidation of metallic layers, e.g. Al deposited on the body, e.g. formation of multi-layer insulating structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/314—Inorganic layers
    • H01L21/316—Inorganic layers composed of oxides or glassy oxides or oxide based glass
    • H01L21/31691—Inorganic layers composed of oxides or glassy oxides or oxide based glass with perovskite structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Materials Engineering (AREA)
  • Semiconductor Memories (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Formation Of Insulating Films (AREA)

Description

1231596 , 玖、發明說明 (發明說明應敘明：發明所屬之技術領域、先前技術、內容、實施方式及圖式簡單說明） '(一）發明所屬之技術領域 * 本發明係關於在半導體裝置中製造積體電路之方法，尤 其是關於在半導體裝置中製造電容器之方法。 (二）先前技術 記憶體元件之整合度，尤其是動態隨機存取記憶體（DRAM ) ，持續地在增加，而貯存資訊基本單元的記憶體單胞（cell) 面積値得注意地在減少。 記憶體單胞面積減少引起單胞電容面積的額外降低，因 此降低感測邊緣和感測速度。並且導致由 α -粒子所產生 軟誤差（soft error)之耐久性降低的其他問題。因此，發展 出一種在限定的面積內獲致足夠的電容量之方法是必須的 〇 電容器之電容量是由下列的數學方程式所定義： C = E · As/d (方程式 1) 其中，E，As和 d分別表示介電常數，電極的有效表面 積和電極間的距離。 因此，已有數種已知的方法藉增加電極表面積，減少介 電薄膜層的厚度及增加介電常數，來增加電容器的電容量 〇 在這些方法中，增加電極的表面積是首要的考量。不同 形式的三維結構電容器，如凹面狀、圓柱狀、多層鰭狀等 ，其目的在有限的空內增加電極的有效面積。然而，當 -6- 1231596 , 半導體裝置的整合度變得非常高，此方法會面臨電極的有 效面積無法充分地增加的額外限制。 同時，藉減少介電材料的厚度來使兩電極間的距離（d) 最小化的其他方法，亦同時因介電薄膜層厚度減少導致洩 漏電流增加的因素而受到侷限。. 因此，最新的趨勢主要是增加介電薄膜層的介電常數， 因而使電容器獲致充分的電容量。傳統上製造電容器時使 矽氧化物層或矽氮化物層當作介電薄膜層的來源。然而， 現今更多的電容器使用具金屬層-絕緣層-多矽層（以下簡 爲MIS)結構，且其中使用加氧化鉅（Ta2 0 5 )之高K値介電 材料當作介電薄膜層。 第1圖爲顯示在半導體裝置中具圓柱狀結構電容器的典 型製造方法剖面圖。 參照第1圖，一埋入絕緣層1 2形成於預先建構活性化 區域1 1的基板1 0上，接著形成穿過埋入絕緣層1 2且接 觸到基板1 〇之活性化區域1 1的接觸孔洞。其次，將接觸 孔洞塡滿傳導材料，形成接觸栓1 3。在接觸栓1 3的頂部 ，形成具有可能做爲電容器尺寸的電容器絕緣層。 其次，電容器絕緣層被選擇性地蝕刻，以自電容孔洞露 出接觸栓1 3。一多矽下層電極1 4在電容器孔洞內部形成 ，且電容絕緣層接著被移除。 在形成多矽下層電極14後，藉由使用氮化矽（Si3N4)電 漿氣體或快速加溫製程以氮化多矽下層電極1 4表面，以 形成氮化物層1 5。 1231596 於氮化物層15上形成一氮化鉅（Ta2〇5)層作爲介電薄膜 · 層丨6，且一上層電極17接著覆蓋上去。 在此，多矽下層電極14的表面，在形成氧化鉅（Ta2〇5) 層之前由氮化矽（Si3N4)電漿氣體所氮化以形成介電薄膜層 1 6。事先氮化旨在一大氣壓的氧下執行加溫製程時防止氧 氣貫穿進入且氧化多矽下層電極14，以改善介電常數。 當高整合度更進一步的實施於半導體裝置，尤其是當電容 器具凹面狀或圓柱狀的三維結構，以固定厚度氮化多矽下 層電極表面是極困難的。亦即，典型的電漿製程或快速加 @ 溫製程無法使氮化物層在多矽下層電極14中穩定地形成 〇 假如氮化物層無法適當的形成，氧氣將貫穿進入電容器 底層結構，如多矽下層電極，且氧化底層結構。此問題最 終會降低電容器製造的信心度。 (三）發明內容 因此，本發明之目的在提供製造電容器之方法，其中在 φ 下層電極上穩定的形成氮化物質且可獲致充分的電容量及 改善的洩漏電流特性。 依照本發明之觀點，提供在半導體裝置中製造電容器之 方法，包括下列步驟：形成下層電極於基板上；形成氮化 物基第一介電薄膜層於下層電極上；藉由沈積一氧化鋁 (ai2o3)層，形成第二介電薄膜層於氮化物基第一介電薄 膜層上；形成第三介電薄膜層於第二介電薄膜層上；及形 成上層電極於第三介電薄膜層上。 - -8 - 1231596 (四）實施方式 第2圖爲顯示依照本發明較佳實施例在半導體裝置中製 造電容器之方法的剖面圖。 參照第2圖，一埋入絕緣層2 3形成於預先建構一活性 化區域2 1的基板2 0上；其後，形成一穿過埋入絕緣層2 3 且接觸到基板2 0之活性化區域2 1的接觸孔洞。接觸孔洞 接著塡充傳導材料以形成接觸栓2 2。電容器絕緣層以形 成電容器的高度，形成在接觸栓 22之頂部。在此，電容 器絕緣層可使用氧化物層，如非摻雜質的矽酸鹽玻璃，磷 -矽酸鹽玻璃，硼-磷矽酸鹽玻璃等。再者，電容器絕緣 層被選擇性蝕刻，以露出接觸栓2 2和形成電容器孔洞。 於電器器孔洞內部，爲了形成下層電極24的多矽層被 沈積直到具有約100A至約 5 0 0A的厚度範圍，且在多矽 層上形成的天然氧化物層，藉使用氫氟酸（HF)或緩衝氧化 蝕刻劑（在後文中稱爲BOE)， 淸洗多矽層表面而移除之。此時，使用具有氨酸化合物 (NH4OH):過氧化氫（H202):過氧化氫（H2〇2)比例爲 1:4 :20 的氨酸化合物（NH4OH)，過氧化氫（H2 0 2 ) ’及 H202(SC-1)爲可能。 另一個可能形成下層電極 24的選用方法是’在沈積一 摻雜質的矽層於約5〇A至約300A的厚度範圍和一非摻雜 雜質的多矽層於約50A至約300A的厚度範圍之後，在一 大氣壓的氮氣（N2)下，以約5 0 0 °C至約7〇〇°C的溫度範圍來 摻雜磷酸（pH3)。接著，電容器絕緣層被移除。 t 1231596 T種增強式熔爐氮化（在後文中稱作E F N )製程被實施， _ 藉^化矽（Si3N4)形式，以形成第一氮化物層25於多矽下 層電極24上。隨即於EFN製程後，加溫製程在一大氣壓 的氨（NH3)氣體時在預設的環境下被實施，其中溫度和壓 力分別被維持在約5 00 °C至約8 0 0 °C和約1托爾（Torr)至約 30托爾（Torr)。然後氨（NH3)氣體在上述的溫度下再次被 使用，以沈積一第二氮化物層2 6。第一和第二氮化物層（2 5 和26)變成具有約5A至約50A之沈積厚度範圍的第一介 0 電薄膜層。在此，E F N製程是經由熔爐加溫製程以氮化矽 (Si3N4)形式來氮化下層電極表面的製程，接著應用氨（NH3) 氣體於氣體於前面加溫製程的溫度和預設環境下，最後形 成雙氮化物層。 在先前技術中，於0 . 1微米閘極線寬度中，快速加溫製 程（後文中稱作 RTP)或電漿製程通常被應用以形成防止氧 氣貫穿進入下層電極和半導體裝置中其他底層結構的氮化 物層。此時，爲獲得預設的電容量，氧化層（後文中稱爲 φ Tox)厚度必須大於約40.8A。另一方面，若應用EFN製程 形成氮化物層，只要Tox大於約34A，獲致特別需求的電 容尺寸爲可能。 同時’若在EFN製程後，氧化氮（N20)電漿製程再被執 行’雖然Τ ο X僅大於約3 〇 A，獲致特別需求的電容亦爲可 能。然而’相較於前面而言，應用氧化氮電漿製程在洩漏 電流特性上是較差的。將氮化物層形成於上層電極上，接 著將氮化鉅（Ta2〇5)層沈積於其上，作爲介電薄膜層。氧 - -10- 1231596 化氮（N2o)電漿製程在沈積後接著處理，且在 0. 1微米閘 · 極線寬度技術中，此氧化氮電漿製程在相較於其他製程時 ，即使介電薄膜層會降低至例如約3 0 A的厚度時，仍可 提供特別需求尺寸的電容。 雖有前述的優點，但氧化氮製程的應用會使電容器的洩 漏電流特性惡化。因此本發明藉沈積氧化鋁層以代替氧化 氮電漿製程以沈積三層介電薄膜層。 其次，具有較佳洩漏電流特性的氧化鋁（A1 2 0 3 )層，藉 _ 由原子層沈積（後文中稱作ALD)製程，沈積一第二介電薄 膜層於第一介電薄膜層上，直到包括第一和第二氮化物（2 5 和26)時具有約20 A至約100 A的厚度範圍。 在針對氧化鋁層沈積以形成第二介電薄膜層 2 7的細節 中，晶圓溫度設定在約 2 0 0 °C至約 5 0 0 °C的範圍，且反應 室的壓力維持在約 0.1托爾（Torr)至約 1托爾（Torr)。同 時，（CH3)3A1氣體和氨（NH3)氣體分別用來當作來源氣體 和運送氣體。該（CH3)3A1氣體連同1^3氣體供應持續約0.1 φ 秒至數秒（如：1 〇秒），以便在基板2 0上被吸收。然後， 以氮氣流經其上數秒（如由約 〇 · 1秒至約1 〇秒），以淸洗 未反應的（CH3)3A1氣體。 再者，供應氧氣主要來源的H20氣體，流經基板20約 〇 · 1秒至約數秒（如：1 〇秒），接著氮氣連續流過數秒（如約 • 1秒至約10秒），以淸洗未反應的Η20氣體。 如上所述的 ALD製程重覆運用，直到獲致需要的厚度 且形成第二介電薄膜層27。 -11- 1231596 以連續的ALD製程形成第二介電薄膜層27後，第三介 電薄膜層2 8藉沈積一厚度範圍自約3 Ο A至約1 Ο Ο A的鉅 (Ta)205層於第二介電薄膜層上而形成。同時，溫度和壓 力分開保持在約2 0 0 °C至約5 0 0 °C和約0 . 1托爾（T 〇 r r )至約 1〇托爾（丁〇1^)的範圍內。鉬化物（1^((：2：«50)5)和氧氣特別 用以形成氧化鉅（Ta205)介電層。其中，氧氣作爲反應氣 體。同時，第三介電薄膜層28可使用高K値介電材料， 如鋇緦鈦氧化物（（Ba，Sr)Ti03)或鐵電材料，如鉛鍩氧化物 ((P b，Z r) T i 0 3)，鉛鑭-鉻鈦氧化物（（p b，L a ) (Z r，T i) 0 3)，緦 鉍鉅氧化物（S r B i 2 T a 2 Ο 9)，鉍鑭鈦氧化物（B i 4 - x L a x T i 3 0 i 2) 等。 在形成第三介電薄膜層 28之後，加溫製程在一大氣壓 的化氮（N20)或氧氣時，以熔爐溫度維持在約 5 00 °C至約 8 0 0 °C的範圍來實行。 後續的化學氣相沈積（CVD)製程被運用，以連續地沈積 氮化鈦（Tin)層和多矽層和第三介電薄膜層28上，而形成 上層電極 29。接著，在一大氣壓的氮氣下，以熔爐維持在 約5 00 °C至約70 0 °C的溫度範圍，施加活性化鍛練製程處理 〇 於是沈積氮化物層，氧化鋁層和氧化鉅層的三層介電薄 膜層於多矽下層電極上，以改善電器容的介電常數，和藉 由略去對洩漏電流特性不利的氧化氮製程改善洩漏電流特 性。 再者，使用氧化鋁層當作介電薄膜層明顯地可增加介電 -12- 1231596 常數，因而可減少電容器的厚度（Tox)。綜觀如上，依本 發明之較佳實施例，製造出具有高介電常數和增強式洩漏 電特性的高整合度電容器，最後成爲可能。 雖然本發明是以特定的較佳實施例敘述，但熟習於此項 技術者可以在不偏離本發明中下列申請專利範圍的範疇內 ，作各種的變化或修正是極爲明顯的。 (五）圖式說明 本發明之目的和特徵，可經由下列連同附圖的較佳實施 例之敘述而變得很明顯，其中： 第1圖爲顯示依習知技術在半導體裝置中製造電容器之 典型方法的剖面圖；及 第2圖爲顯示依照本發明較佳實施例在半導體裝置中製 造電容器之方法的剖面圖。 符號之說明 10 基 板 11 活 性 化 區 域 12 埋 入 絕 緣 層 13 接 觸 栓 14 下 層 電 極 15 氮 化 物 層 16 介 電 薄 膜 層 17 上 層 電 極 20 基 板 2 1 活 性 化 區 域 -13- 1231596 22 接 觸 栓 23 埋 入 絕 緣 層 24 下 層 電 極 25 第 一 氮 化 物 層 26 第 二 氮 化 物 層 27 第 二 介 電 薄 膜 層 2 8 第 二 介 電 薄 膜 層 29 第 三 介 電 薄 膜 層
-14-

Claims (1)

1231596 … 拾、申請專利範圍 · 1. 一種在半導體裝置製造電容器之方法，包括下列步驟： - 形成下層電極於基板上； 形成氮化物基第一介電薄膜層於下層電極上； 藉由沈積一氧化鋁（A 1 2 0 3 )層，形成第二介電薄膜層於氮 化物基第一介電薄膜層上； 形成第三介電薄膜層於第二介電薄膜層上；及 形成上層電極於第三介電薄膜層上。 鲁 2.如申請專利範圍第1項之方法，其中氧化鋁（A 1 2 0 3 )層是 藉由原子層沈積（ALD)製程所沈積。 3 .如申請專利範圍第2項之方法，其中原子層沈積製程， 包括下列步驟： 流過（CH3)3A1氣體當作來源氣體及NH3氣體在基板上約 0 . 1秒至1 0秒； 流過氮氣（N2)約 0.1秒至 10秒以淸洗未發生反應的 (CH3)3A1 氣體;. ® 流過提供氧氣源的H20氣體於基板上約0.1秒至10秒； 及 流過氮氣（N2)約0. 1秒至10秒以淸洗未發生反應的h2〇 氣體。 4.如申請專利範圍第3項之方法，其中ALD製程之實施是 藉由將晶圓之溫度保持在約2 0 0 °C至5 0 (TC的範圍及反應 室的壓力維持在約〇」托爾（Torr)至1托爾。 -15- 1231596 5.如申請專利範圍第3項之方法，其中氧化鋁（A 1 2 0 3 )層具 有自約2 0 A至約1 0 0 A的沈積厚度。 6 .如申請專利範圍第1項之方法，其中形成氮化物基第一 介電薄膜層的步驟包括： 經由熔爐加溫製程加氮於下層電極表面；及 使用^^153氣體於加氮的下層電極上沈積一氮化物層。 7 .如申請專利範圍第6項之方法，其中加氮於下層電極的 表面及沈積氮化物驟之實施是在溫度和壓力保持在分別 是約5 0 0 °C至約8 0 0 °C和約1托爾（T 〇 r 〇至約3 0托爾（T 〇 r r ) 的範圍內。
TW091136874A 2002-06-21 2002-12-20 Method for fabricating capacitor in semiconductor device TWI231596B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR10-2002-0035096A KR100500940B1 (ko) 2002-06-21 2002-06-21 반도체 장치의 캐패시터 제조방법

Publications (2)

Publication Number Publication Date
TW200400616A TW200400616A (en) 2004-01-01
TWI231596B true TWI231596B (en) 2005-04-21

Family

ID=36122002

Family Applications (1)

Application Number Title Priority Date Filing Date
TW091136874A TWI231596B (en) 2002-06-21 2002-12-20 Method for fabricating capacitor in semiconductor device

Country Status (4)

Country Link
US (1) US6706607B2 (zh)
KR (1) KR100500940B1 (zh)
CN (1) CN1329975C (zh)
TW (1) TWI231596B (zh)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100721579B1 (ko) * 2002-12-30 2007-05-23 주식회사 하이닉스반도체 캐패시터의 제조 방법
KR100469158B1 (ko) * 2002-12-30 2005-02-02 주식회사 하이닉스반도체 반도체소자의 캐패시터 형성방법
US20050092348A1 (en) * 2003-11-05 2005-05-05 Ju-Chien Chiang Method for cleaning an integrated circuit device using an aqueous cleaning composition
KR100587082B1 (ko) * 2004-06-30 2006-06-08 주식회사 하이닉스반도체 반도체 소자의 캐패시터 형성방법
KR100771546B1 (ko) * 2006-06-29 2007-10-31 주식회사 하이닉스반도체 메모리 소자의 커패시터 및 형성 방법
CN106328376A (zh) * 2015-07-03 2017-01-11 华硕电脑股份有限公司 电容器的制造方法
US11588009B2 (en) * 2018-12-12 2023-02-21 Amkor Technology Singapore Holding Pte. Ltd. Semiconductor device having a lid configured as an enclosure and a capacitive structure and method of manufacturing a semiconductor device
US11621269B2 (en) * 2019-03-11 2023-04-04 Globalfoundries U.S. Inc. Multi-level ferroelectric memory cell
DE102020113099A1 (de) 2020-02-27 2021-09-02 Taiwan Semiconductor Manufacturing Co., Ltd. Ferroelektrische direktzugriffsspeichervorrichtung mit einem dreidimensionalen ferroelektrischen kondensator
US11450676B2 (en) * 2020-02-27 2022-09-20 Taiwan Semiconductor Manufacturing Company, Ltd. Ferroelectric random access memory device with a three-dimensional ferroelectric capacitor
US20230387188A1 (en) * 2022-05-24 2023-11-30 Nanya Technology Corporation Storage capacitor with multiple dielectrics

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5745968A (en) * 1980-08-29 1982-03-16 Ibm Capacitor with double dielectric unit
US4423087A (en) * 1981-12-28 1983-12-27 International Business Machines Corporation Thin film capacitor with a dual bottom electrode structure
US4471405A (en) * 1981-12-28 1984-09-11 International Business Machines Corporation Thin film capacitor with a dual bottom electrode structure
US4437139A (en) * 1982-12-17 1984-03-13 International Business Machines Corporation Laser annealed dielectric for dual dielectric capacitor
KR970004885B1 (ko) * 1993-05-12 1997-04-08 삼성전자 주식회사 평판표시장치 및 그 제조방법
US6346741B1 (en) * 1997-11-20 2002-02-12 Advanced Technology Materials, Inc. Compositions and structures for chemical mechanical polishing of FeRAM capacitors and method of fabricating FeRAM capacitors using same
KR100280206B1 (ko) * 1997-12-06 2001-03-02 윤종용 고유전체 캐패시터 및 그의 제조 방법
US6509601B1 (en) * 1998-07-31 2003-01-21 Samsung Electronics Co., Ltd. Semiconductor memory device having capacitor protection layer and method for manufacturing the same
KR20010017820A (ko) * 1999-08-14 2001-03-05 윤종용 반도체 소자 및 그 제조방법
KR100390951B1 (ko) 1999-12-29 2003-07-10 주식회사 하이닉스반도체 반도체 소자의 구리 배선 형성 방법
KR100612561B1 (ko) * 2000-06-19 2006-08-11 주식회사 하이닉스반도체 반도체 소자의 캐패시터 제조 방법
KR20010114054A (ko) * 2000-06-20 2001-12-29 박종섭 커패시터 제조 방법
KR100639200B1 (ko) * 2000-06-30 2006-10-31 주식회사 하이닉스반도체 반도체 메모리 소자의 캐패시터 제조방법
CN1336685A (zh) * 2000-08-02 2002-02-20 联华电子股份有限公司 制造半导体电容器的方法
US6486530B1 (en) * 2000-10-16 2002-11-26 Intarsia Corporation Integration of anodized metal capacitors and high temperature deposition capacitors
JP2002164506A (ja) * 2000-11-27 2002-06-07 Toshiba Corp 半導体装置及びその製造方法
KR100417855B1 (ko) * 2001-04-30 2004-02-11 주식회사 하이닉스반도체 반도체소자의 캐패시터 및 그 제조방법
KR100406549B1 (ko) * 2001-06-30 2003-11-22 주식회사 하이닉스반도체 지르코늄산화막을 구비하는 캐패시터의 제조 방법
KR100487519B1 (ko) * 2002-02-05 2005-05-03 삼성전자주식회사 반도체 장치의 커패시터 및 그 제조 방법

Also Published As

Publication number Publication date
CN1329975C (zh) 2007-08-01
KR100500940B1 (ko) 2005-07-14
US20030235947A1 (en) 2003-12-25
TW200400616A (en) 2004-01-01
US6706607B2 (en) 2004-03-16
CN1467823A (zh) 2004-01-14
KR20040000601A (ko) 2004-01-07

Similar Documents

Publication Publication Date Title
TWI322487B (en) Method for fabricating capacitor in semiconductor device
KR100604845B1 (ko) 질소를 포함하는 씨앗층을 구비하는 금속-절연체-금속캐패시터 및 그 제조방법
TWI231596B (en) Method for fabricating capacitor in semiconductor device
TWI263345B (en) Capacitor with oxidation barrier layer and method for manufacturing the same
KR100729354B1 (ko) 유전막의 전기적 특성 향상을 위한 반도체 소자의 제조방법
KR100417855B1 (ko) 반도체소자의 캐패시터 및 그 제조방법
KR100587082B1 (ko) 반도체 소자의 캐패시터 형성방법
JP2001053255A (ja) 半導体メモリ素子のキャパシタの製造方法
KR100513804B1 (ko) 반도체 소자의 캐패시터 제조방법
KR100575887B1 (ko) 반도체 소자의 캐패시터 형성방법
KR100476374B1 (ko) 반도체소자 제조 방법
JP4784065B2 (ja) キャパシタおよびキャパシタの製造方法および半導体装置
KR19990057942A (ko) 반도체 장치의 강유전체 캐패시터 제조방법
KR100937988B1 (ko) 반도체 소자의 캐패시터 제조방법
KR100321692B1 (ko) 강유전체 메모리 소자의 캐패시터 및 그 제조방법
KR100265333B1 (ko) 반도체 장치의 고유전체 캐패시터 제조방법
KR20040102277A (ko) 유전막 형성방법
KR101062812B1 (ko) 반도체 소자의 하프늄 산화막 캐패시터 형성방법
KR100437619B1 (ko) 반도체 소자의 캐패시터 형성방법
KR100347142B1 (ko) 유전막 제조 방법
KR100406547B1 (ko) 반도체 소자의 커패시터 제조 방법
TW200411819A (en) Method for fabricating capacitor in semiconductor device
TWI223447B (en) Insulation structure of vertical trench transistor and its manufacturing method
JP4106513B2 (ja) 半導体素子のキャパシタ製造方法
KR100362197B1 (ko) 반도체소자 제조 방법

Legal Events

Date Code Title Description
MM4A Annulment or lapse of patent due to non-payment of fees