CN1329975C - 半导体器件的电容器的制造方法 - Google Patents

半导体器件的电容器的制造方法 Download PDF

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CN1329975C
CN1329975C CNB03122556XA CN03122556A CN1329975C CN 1329975 C CN1329975 C CN 1329975C CN B03122556X A CNB03122556X A CN B03122556XA CN 03122556 A CN03122556 A CN 03122556A CN 1329975 C CN1329975 C CN 1329975C
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dielectric thin
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gas
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CN1467823A (zh
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朴钟范
吴勋静
金京民
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SK Hynix Inc
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Abstract

本发明涉及半导体器件中电容器的制造方法，尤其涉及可稳定地在下层电极上形成氮化物层，并获得稳定的电容量和漏电流特性的改善的电容器的制造方法。本发明用于制造电容器的方法包括步骤：在衬底上形成下层电极；在下层电极上形成第一介电薄层；在第一介电薄层上，藉沉积Al2O3层，形成第二介电薄层；在第二介电薄层上利用高k值介电材料形成第三介电薄层；以及在第三介电薄层上形成上层电极。

Description

半导体器件的电容器的制造方法
技术领域
本发明涉及一种半导体器件中集成电路的制造方法，尤其涉及一种半导体器件中电容器的制造方法。
背景技术
存储器件的集成度，尤其是动态随机存取存储器(DRAM)，持续地在增加，而贮存信息基本单元的存储器单元(cell)面积明显减少。
存储器单元面积减少引起单元电容面积的额外降低，因此降低感测极限和感测速度。并且导致由α-粒子所产生软误差(soft error)的耐久性降低的其它问题。因此，发展出一种在限定的面积内获致足够的电容量的方法是必须的。
电容器的电容量由下列的数学方程式所定义：
C＝ε·As/d            (方程式1)
其中，ε，As和d分别表示介电常数、电极的有效表面积和电极间的距离。
因此，已有数种已知的方法藉增加电极表面积、减少介电薄层的厚度及增加介电常数，来增加电容器的电容量。
在这些方法中，增加电极的表面积是首要的考虑。不同形式的三维结构电容器，如凹面状、圆柱状、多层鳍状等，其目的在于在有限的面积内增加电极的有效面积。然而，当半导体器件的集成度变得非常高，此方法会面临电极的有效面积无法充分地增加的额外限制。
同时，由于漏电流随介电薄层厚度减少而增加，所以其它藉减少介电材料的厚度来使两电极间的距离(d)最小化的方法也受到限制。
因此，最新的趋势主要是增加介电薄层的介电常数，因而使电容器获致充分的电容量。传统制造的电容器将氧化硅层或氮化硅层用作介电薄层。然而，现今更多的电容器使用金属层-绝缘层-多晶硅层(以下简为MIS)结构，其中使用如氧化钽(Ta2O5)的高K值介电材料当作介电薄层。
图1为显示半导体器件中具圆柱状结构电容器的典型制造方法的剖面图。
参照图1，层间绝缘层12形成于预先构造有有源区11的衬底10上，接着形成穿过层间绝缘层12且接触到衬底10的有源区11的接触孔。其次，将接触孔填满导电材料，形成接触插塞13。在接触插塞13的顶部，形成具有用于形成电容器的尺寸的电容器绝缘层。
其次，电容器绝缘层被选择性地蚀刻，以露出接触插塞13并形成电容器孔。
多晶硅下层电极14在电容器孔洞内部形成，且电容绝缘层接着被移除。在形成多晶硅下层电极14后，藉由使用氮化硅(Si3N4)等离子体气体或快速热处理来氮化多晶硅下层电极14的表面，以形成氮化物层15。
于氮化物层15上形成Ta2O5层作为介电薄层16，且一上层电极17接着覆盖上去。
在此，在形成用于形成介电薄层16的Ta2O5层之前，多晶硅下层电极14的表面用Si3N4等离子体气体所氮化。事先氮化旨在氧气氛下执行热处理时防止氧气贯穿进入且氧化多晶硅下层电极14，以改善介电常数。
当高集成度更进一步地实施于半导体器件，尤其是当电容器具凹面状或圆柱状的三维结构时，以固定厚度氮化多晶硅下层电极14的表面是困难的。亦即，典型的等离子体工艺或快速热处理无法使氮化物层在多晶硅下层电极14上稳定地形成。
假如氮化物层无法适当地形成，则氧气将贯穿进入电容器底层结构，如多晶硅下层电极，且氧化底层结构。此问题最终会降低电容器制造的可靠性。
发明内容
因此，本发明的目的在于提供一种制造电容器的方法，其中在下层电极上稳定地形成氮化物层，且获致充分的电容量及改善的漏电流特性。
依照本发明的一个方面，提供一种半导体器件中电容器的制造方法，包括下列步骤：形成下层电极于衬底上；形成氮化物第一介电薄层于下层电极上；藉由沉积Al2O3层，形成第二介电薄层于氮化物第一介电薄层上；利用高k值介电材料形成第三介电薄层于第二介电薄层上；以及形成上层电极于第三介电薄层上。
附图说明
本发明的以上和其它目的和特征，可经由下列连同附图的优选实施例的叙述而变得很明显，其中：
图1为显示依现有技术制造半导体器件中的电容器的典型方法的剖面图；以及
图2为显示依照本发明优选实施例制造半导体器件中的电容器的方法的剖面图。
附图中的附图标记说明如下：
10衬底             11有源区
12层间绝缘层       13接触插塞
14下层电极         15氮化物层
16介电薄层         17上层电极
20衬底             21有源区
22接触插塞         23层间绝缘层
24下层电极         25第一氮化物层
26第二氮化物层     27第二介电薄层
28第三介电薄层     29第三介电薄层
具体实施方式
图2为显示依照本发明优选实施例制造半导体器件中的电容器的方法的剖面图。
参照图2，层间绝缘层23形成于预先建构有一有源区21的衬底20上；其后，形成一穿过层间绝缘层23且接触到衬底20的有源区21的接触孔。接触孔接着填充导电材料以形成接触插塞22。电容器绝缘层在接触插塞22的顶部上形成得足够高以形成电容器。在此，电容器绝缘层可使用氧化物层，如未掺杂的硅酸盐玻璃、磷硅酸盐玻璃、硼磷硅酸盐玻璃等。
然后，电容器绝缘层被选择性蚀刻，以露出接触插塞22并形成电容器孔。
于电容器孔内部，用于形成下层电极24的多晶硅层被沉积直到具有约100至约500范围内的厚度，且多晶硅层上形成的天然氧化物层藉由使用HF或缓冲氧化蚀刻剂(在后文中称为BOE)清洗多晶硅层表面而去除。此时，可以使用NH4OH∶H2O2∶H2O2之比为1∶4∶20的NH4OH、H2O2及H2O2(SC-1)。
也可以通过以下方法来形成下层电极24，该方法即：在沉积一掺杂多晶硅层到约50至约300厚、且沉积一非掺杂多晶硅层到约50至约300厚之后，通过在N2气氛中，在约500℃至约700℃范围内的一温度下掺杂PH3而形成下层电极。接着，电容器绝缘层被去除。
一种增强式熔炉氮化(enhanced furnace nitride)(以下称作EFN)工艺被实施，以按Si3N4的形式形成第一氮化物层25于多晶硅下层电极24上。随即于EFN工艺后，热处理在原位条件下在NH3气体气氛中进行，其中温度和压力分别被维持在约500℃至约800℃和约1乇(Torr)至约30乇(Torr)的范围内。然后，NH3气在上述温度下再次被使用，以沉积一第二氮化物层26。第一和第二氮化物层25和26成为具有约5至约50的沉积厚度范围的第一介电薄层。在此，EFN工艺是如下的一种工艺，该工艺经由炉内热处理以Si3N4形式来氮化下层电极表面，接着在用于先前热处理的相同温度下在原位环境下，施加NH3气以最后形成双氮化物层。
在现有技术中，在0.1微米栅极线宽度中，快速热处理(以下称作RTP)或等离子体工艺通常被应用以形成防止氧气贯穿进入下层电极和半导体器件中其它底层结构的氮化物层。此时，用于获得预设电容量的氧化层的厚度(后文中称为Tox)应当大于约40.8。另一方面，若应用EFN工艺形成氮化物层，只要Tox大于约34，也可以获得特别需求的电容大小。
此外，若在EFN工艺后，再次进行N2O等离子体工艺，则虽然Tox大于约30，但是也可获致特别需求的电容大小。然而，在应用N2O等离子体工艺后，漏电流特性通常比先前有更差的表现。即，将氮化物层形成于下层电极上，接着将Ta2O5层沉积于其上作为介电薄层。在沉积后接着进行N2O等离子体工艺，且即使介电薄层的厚度相比于其它工艺的应用(例如0.1微米栅极线宽度技术中的约30)有所减小，此N2O等离子体工艺的应用仍可提供特别需求的电容大小。
虽有前述的优点，但N2O等离子体工艺的应用会使电容器的漏电流特性恶化。因此，取代使用N2O等离子体工艺，本发明采用一种通过沉积Al2O3层来沉积三层介电薄层的方法。
接着，具有较佳漏电流特性的Al2O3层藉由原子层沉积(以下称作ALD)工艺，沉积在包括第一和第二氮化物层25和26的第一介电薄层上作为一第二介电薄层27，直到具有约20至约100的厚度。
更具体地，对于用于形成第二介电薄层27的Al2O3层沉积，晶片温度设定在约200℃至约500℃的范围，且反应室的压力维持在约0.1乇(Torr)至约1乇(Torr)。同时，(CH3)3Al气体和NH3气体分别用来当作源气体和运送气体。该(CH3)3Al气体连同NH3气体供应持续约0.1秒至约数秒(如10秒)，以便在衬底20上被吸收。然后，以氮气流经其上数秒(如由约0.1秒至约10秒)，以清洗未反应的(CH3)3Al气体。
再者，作为供应氧气主要来源的H2O气体流经衬底20约0.1秒至约数秒(如10秒)，接着氮气流过数秒(如约0.1秒至约10秒)，以清洗未反应的H2O气体。
如上所述的ALD工艺重复运用，直到获致需要的厚度且形成第二介电薄层27。
接续用于形成第二介电薄层27的ALD工艺之后，第三介电薄层28通过沉积一厚度范围在约30至约100之间的Ta2O5层于第二介电薄层27上而形成。同时，温度和压力分别保持在约200℃至约500℃和约0.1乇(Torr)至约1.0乇(Torr)的范围内。Ta(C2H5O)5和O2特别用以形成Ta2O5介电层。其中，氧气作为反应气体。同时，第三介电薄层28可使用如(Ba，Sr)TiO3的高K值介电材料，或如(Pb，Zr)TiO3，(Pb，La)(Zr，Ti)O3，SrBi2Ta2O9，Bi4-xLaxTi3O12等的铁电材料。
在形成第三介电薄层28之后，热处理在N2O或O2的气氛下，在炉内温度维持在约500℃至约800℃的范围内实行。
后续的化学气相沉积(CVD)工艺被运用，以连续地沉积TiN层和多晶硅层在第三介电薄层28上，用于形成上层电极29。接着，在N2气氛下，在炉内维持在约500℃至约700℃的温度范围内进行活化退火处理(activation annealing process)。
于是，沉积氮化物层、Al2O3层和Ta2O5层的三层介电薄层于多晶硅下层电极上，这改善了电器容的介电常数，并藉由略去对漏电流特性不利的N2O等离子体工艺而改善了漏电流特性。
再者，使用Al2O3层当作介电薄层明显地增加了介电常数，因而明显减少了电容器的Tox。综观如上，依本发明的优选实施例，最终可以制造出具有高介电常数和更好的漏电流特性的高集成度电容器。
虽然本发明已经以特定的优选实施例进行了说明，但对本领域技术人员而言显然的是，可以在不偏离本发明所附权利要求所确定的范围的情况下，作各种变化和修正。

Claims (11)

1.一种制造半导体器件中的电容器的方法，包括下列步骤：
形成下层电极于衬底上；
形成氮化物第一介电薄层于下层电极上；
藉由沉积Al2O3层于氮化物第一介电薄层上来形成第二介电薄层；
利用高k值介电材料形成第三介电薄层于第二介电薄层上；以及
形成上层电极于第三介电薄层上。
2.如权利要求1所述的方法，其中，Al2O3层通过原子层沉积工艺沉积。
3.如权利要求2所述的方法，其中，原子层沉积工艺包括下列步骤：
在衬底上流过作为源气体的(CH3)3Al气体、以及NH3气体0.1秒至10秒；
流过N2气体0.1秒至10秒以清除未反应的(CH3)3Al气体；
流过作为向衬底提供氧的源的H2O气体0.1秒至10秒；以及
流过N2气0.1秒至10秒以清除未反应的H2O气体。
4.如权利要求3所述的方法，其中，通过将晶片的温度保持在200℃至500℃的范围，且将反应室的压力维持在0.1乇至1乇的范围，来进行原子层沉积工艺。
5.如权利要求3所述的方法，其中，Al2O3层沉积来具有20至100的厚度。
6.如权利要求1所述的方法，其中，形成氮化物第一介电薄层的步骤包括：
通过热处理在炉内氮化下层电极的表面形成第一氮化物层；以及
使用NH3气体于所述第一氮化物层上沉积第二氮化物层。
7.如权利要求6所述的方法，其中，形成第一氮化物层和沉积第二氮化物层的步骤在温度和压力分别保持在500℃至800℃和1乇至30乇的范围内的情形下进行。
8.如权利要求6所述的方法，其中，第一和第二氮化物层的厚度在5至50的范围内。
9.如权利要求1所述的方法，其中，形成第三介电薄层的步骤包括在第二介电薄层上沉积Ta2O5层的步骤。
10.如权利要求9所述的方法，其中，在第二介电薄层上沉积Ta2O5层的步骤在温度和压力分别保持在200℃至500℃和0.1乇至1.0乇的范围内的情形下进行。
11.如权利要求9所述的方法，其中，Ta2O5层沉积的厚度在30至100的范围内。
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