TWI231019B - Lead frame and manufacturing method thereof and a semiconductor device - Google Patents

Lead frame and manufacturing method thereof and a semiconductor device Download PDF

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Publication number
TWI231019B
TWI231019B TW092100434A TW92100434A TWI231019B TW I231019 B TWI231019 B TW I231019B TW 092100434 A TW092100434 A TW 092100434A TW 92100434 A TW92100434 A TW 92100434A TW I231019 B TWI231019 B TW I231019B
Authority
TW
Taiwan
Prior art keywords
lead frame
copper oxide
oxide layer
base material
copper
Prior art date
Application number
TW092100434A
Other languages
English (en)
Other versions
TW200308069A (en
Inventor
Takahiro Yurino
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Publication of TW200308069A publication Critical patent/TW200308069A/zh
Application granted granted Critical
Publication of TWI231019B publication Critical patent/TWI231019B/zh

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    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3142—Sealing arrangements between parts, e.g. adhesion promotors
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    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/60—Attaching or detaching leads or other conductive members, to be used for carrying current to or from the device in operation
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/495—Lead-frames or other flat leads
    • H01L23/49579—Lead-frames or other flat leads characterised by the materials of the lead frames or layers thereon
    • H01L23/49586—Insulating layers on lead frames
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  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Lead Frames For Integrated Circuits (AREA)

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l23l〇l9 玖、發明說明 【發^明内穷】 發明概要 本發明之一般目的在於提供改良且有用之半導體元件 並可消除上述之問題。 本發明之特殊目的在提供以銅合金製成之引線框，其 可防止引線框表面及使用這種引線框之半導體元件附近發 生剝落。 為了達到上述目的，本發明一方面提供了一種引線框 ，其包括有··一個由銅合金製成之基底材料；以及一層藉 1〇將引線框與強氧化劑溶液接觸而形成之氧化銅層，氧化銅 層乃作為最外層，並由氧化銅而非針狀結晶形式之氧化銅 所組成。 根據上述之發明，由於引線框之基底材料上面預先形 成了氧化鋼|，故於半導體元件製程中引線框之基底材料 15不會因文熱而氧化，且基底材料中不會形成脆性層。因此 ，即使在樹脂封裝之後將半導體元件加熱，仍可防止半導 體元件之封裝件膨脹或破裂。此外，可僅將引線框浸入強 氧化劑溶液中而形成氧化銅層，其降低了半導體元件之製 造成本。 2〇 此外，本發明之引線框中氧化銅層的厚度最好為1〇至 1000埃。由於氧化銅層非常薄，氧化銅層無法變成針狀結 晶層，因此氧化銅層可於基底材料表面上形成穩定之單層 〇 此外，本發明另一方面提供了一種引線框製造方法， 7 1231019 玖、發明說明 其包括有：將銅合金製成之基底材料配置成預定圖案；將 一部分的基底材料進行電鍍；以及藉將基底材料浸入強氧 化劑溶液中，於基底材料表面上形成最外層之氧化銅層， 氧化銅層係由氧化銅而非針狀結晶形式之氧化銅所組成。 5 於本發明之製造方法中，可調整基底材料浸入強氧化 劑溶液中的時間，以在氧化銅變成針狀結晶狀態之前將基 底材料自強氧化劑溶液中取出。 此外’本發明另一方面提供了一種半導體元件，其包 括有·一個在以銅合金製成之基底材料上面形成氧化銅層 10的引線框，作為最外層之氧化銅層乃藉將引線框與強氧化 劑溶液接觸而形成，氧化銅層係由氧化銅而非針狀結晶形 式之氧化鋼所組成；一個黏貼於引線框之預定部分上面的 半導體元件；以及封裝半導體元件之密封樹脂。 於本發明之半導體元件中，氧化銅層之厚度可為1〇至 15 1000埃。 藉由下文之詳細說明，並參看諸幅附圖，則本發明之 其它目的、特色及優點將變的更明顯。 圖式簡單說明 第1圖乃使用傳統引線框之半導體元件的一個橫截面 20圖； 第2圖乃第1圖中繪示之半導體元件的橫截面圖，其繪 示了晶片座與密封樹脂之間發生剝落的情形； 第3圖乃用於本發明實施例之半導體元件的一個引線 框平面圖； 1231019 玖、發明說明 第4圖為第3圖中繪示之引線框的一個晶片座放大橫截 面圖； 第5圖繪示了將半導體晶片2黏貼於晶片座上面之後進 行打線時的引線框平面圖； 5 第6圖繪示了黏貼於晶片座上面之半導體晶片的放大 側視圖；以及 第7A及7B圖舉例說明了相較於傳統之塗黑處理程序 根據本發明形成氧化銅層的一個程序。 【實方式I 10 較佳實施例之詳細說明 現在將參看諸幅附圖說明本發明之實施例。 第3圖乃用於本發明實施例之半導體元件的一個引線 框10平面圖，第4圖則為第3圖中繪示之引線框10的一個晶 片座11放大橫截面圖。本發明之半導體元件中所使用的引 15線框10與傳統引線框類似，係以銅合金金屬板作為基板進 行加工及圖案製作程序而形成。一般而言，用於引線框之 鋼合金含有極少量的鋅（Zn)、鉛（Pb)、鉻（Cr)等添加元素 。銅合金金屬板係利用已知的技術進行圖案製作程序，例 如常用之沖壓法和蝕刻法。於銅合金金屬板圖案製作程序 20完成之後，為了形成引線框1〇架構，在每條内引線12末端 鍍上銀（Ag)，至此仍進行與傳統引線框相同之程序。 雖然傳統引線框在鑛銀（Ag)之後可塗以有機的防樋色 劑，本發明之引線框10卻省略了表面的防褪色劑，而於引 線框10表面上形成一層氧化銅薄膜。亦即在銅合金金屬板 1231019 玖、發明說明 表面塗以防褪色劑之後即完成傳統引線框，而在本發明之 引線框10中，作為基底材料之銅合金乃利用後述之特殊方 法氧化，以在引線框10表面上形成最外層之氧化銅層14( 參看第4圖）。 5 如上所述，當氧化銅層14在引線框1〇表面上、尤其是 在晶片座11表面上成形之後，引線框1〇即完成，接著利用 引線框10製造半導體元件。 除了在引線框10中形成之氧化銅層14之外，本發明實 施例之半導體元件的基本組成係與第1圖中繪示之半導體 10元件相同。第5圖繪示了將半導體晶片2黏貼於晶片座^上 面之後進行打線時的引線框平面圖，第6圖則繪示了黏貼 於晶片座11上面之半導體晶片的一個放大側視圖。 於半導體元件製程中，首先以提供之黏晶材料5將半 導體晶片2黏貼於引線框10之晶片座u上面，接著利用接 15合線6連接半導體晶片2之電極與内引線12的鍍銀部分，之 後以密封樹脂8封裝晶片座11、半導體晶片2、接合線6以 及内引線12。 本實施例之半導體元件所使用的引線框丨〇，係於基底 材料表面上形成氧化銅層14，有鑑於此，即使在打線過程 20中將引線框1〇加熱，引線框10之基底材料中的銅亦不會因 文熱而氧化。因此，在熱氧化過程中不會發生由於添加元 素之/農縮而在作為基底材料的銅合金與氧化銅層之間形成 脆性層，藉以避免由脆性層所造成之封裝件售出或破裂。 參看第7A及7B圖，現在將說明本實施例之氧化銅層 10 1231019 玖、發明說明 一般而$，塗黑處理乃藉使引線框表面形成類似針狀，以 改善密封樹脂與引線框之間的黏著性。 用於塗黑處理之強氧化劑溶液係一種混合液 ，例如氯 化鈉、氫氧化鈉、以及過硫化鉀之混合液。於大約1〇〇。〇 5之溫度下’將鋼合金浸入這種混合液3至10分鐘可形成二 價鋼（CuO)之針狀結晶層。 雖然本實施例中基底材料21上面形成之氧化銅層14亦 可利用上述塗黑處理過程中使用的強氧化劑混合液形成， 但氧化銅層14並非針狀結晶層。即言之，在傳統塗黑處理 1〇中化學反應乃持續至表面之氧化銅層變成二價銅（CuO)之 針狀結晶層為止。另一方面，本實施例之氧化銅層14主要 由一價銅（ChO)所組成，其係於二價銅(Cu〇)轉變為針狀 、、’σ B曰層之刖將引線框自強氧化劑混合液中取出而形成。 因此，本實施例之氧化處理時間必須明顯小於傳統塗 15黑處理所需之時間。此外，雖然經過塗黑處理程序之引線 框最外層為二價鋼（Cu〇)之針狀結晶層，但本實施例之引 線框10最外層的氧化銅層14仍非針狀結晶層。再者，本實 施例之氧化銅層14的厚度明顯小於利用塗黑處理所形成之 針狀結晶層厚度，且足以達到大約1〇至1〇〇〇埃的等級。 Λ 如上所述，由於本實施例之氧化銅層14可僅將引線框 浸入強氧化劑溶液極短時間而形成，故可輕易地形成氧化 銅層14而不會增加引線框的製造成本。此外，氧化銅層14 可做成相當薄，並可形成穩定之一價銅（Cu2〇)層。 其次，當利用引線框形成半導體元件時，引線框係於 12 1231019 玖、發明說明 打線過程中加熱。此時如第7A-(c)圖中所示，由於在第7圖 中所不未形成氧化銅層14之情況中，露出之基底材料21的 銅叉熱氧化而形成如第7A_(C)圖中所示之氧化銅層22。另 一方面’於上述之氧化處理程序中形成氧化銅層14的情況 中由於基底材料21表面上已被氧化銅層14所覆蓋，故不 會重新形成另一氧化銅層。 此時於露出之基底材料21的銅受熱氧化並形成氧化銅 層22之第7A圖情況中，基底材料21中的添加元素會分離， 並凝結於氧化銅層22與基底材料21之間，藉以形成一層濃 10縮層23。此濃縮層23乃相當於上述之脆性層。另一方面， 於第7B圖中繪示之形成氧化銅層14的情況中，並不會因熱 氧化而形成氧化銅層，因此不會形成濃縮層23。 於打線程序完成之後，以密封樹脂8封裝半導體晶片2 。將半導體晶片2黏貼並固定於引線框1〇之晶片座u上面 15 ，而晶片座Π亦利用密封樹脂8—起封裝。因此於第7八圖 之程序中，以密封樹脂8覆蓋氧化銅層22，如第7A-(d)圖 中所示。另一方面，於第7B圖之程序中，以密封樹脂8覆 蓋利用氧化程序而被迫形成之氧化銅層14，如第7B-(d)圖 中所示。 20 於完成樹脂封裝之後，半導體元件即成形，此時半導 體元件於第7 A圖之情況與第7B圖之情況下均能正常運作 。因此’可貯存半導體元件直到欲使用為止。於貯存期間 ，半導體元件之密封樹脂可能會從周圍空氣中吸收濕氣。 接著，當利用半導體元件製成產品時，半導體元件係 13 1231019 玖、發明說明 黏貼在-塊安裝基板上面。在許多情況中乃使用焊錫黏貼 半導體元件，特別是將外引線焊在安裝基板之電極焊塾上 以安裝引線端子型半導體元件。在這種安裝程序中，半導 體元件受到焊錫回流之加熱。由於無錯焊錫具有較高的溶 5 點’加熱溫度可達到約230-240°C。 當半導體元件於此溫度下加熱時，半導體元件（密封 樹脂）内所產生之熱應力會增加，其可能在脆性濃縮層23 中形成小裂縫。若密封樹脂吸收之濕氣進入此裂縫並轉變 成水瘵况，則如第7A-(e)中所示，濃縮層23中可能發生剝 10 落’並引起密封樹脂膨脹或破裂之問題。 另一方面，於第7B圖之情況中，半導體元件提供了氧 化銅層14，以防止形成濃縮層23，由於並無脆性層，因此 引線框10與密封樹脂8之間的邊界附近不會發生裂縫或破 損’因此不會有這類封裝件膨脹或破裂之問題。 15 發明者根據本實施例（第7B圖之範例）生產具有氧化銅 層14之基底材料21，且亦利用熱氧化方式（第7A圖之範例） 生產具有氧化銅層22之基底材料21，並於氧化銅層14及22 上進行帶狀剝離試驗。引線框乃置於加熱器上面，於250 °C下加熱3分鐘，接著將氧化銅層14及22接於帶上，並從 20引線框分開。於是在全部五個試件中，形成熱氧化薄膜之 氧化銅薄膜22自基底材料21剝離。另一方面，在全部五個 試件中，本實施例之氧化銅層14並不會發生剝離，因此可 證明本實施例之氧化銅層14較利用熱氧化所形成之氧化銅 層22能更堅固地接於引線框之基底材料21上。 14 1231019 玖、發明說明 如上所述，使用其中形成了本實施例之氧化銅層14的 引線框10,可避免因安裝過程中半導體元件受熱而造成之 封裝件膨脹或破裂。尤其是，即使在使用無鉛焊錫之安裝 過程中，當焊錫於230-240X：下回流時，仍可防止半導體 5 元件膨服或破裂。 本發明並不限於具體揭示之實施例，且於未偏離本發 明之範圍内可做變更與修正。 本申請案係以2002年6月7曰歸檔之曰本優先申請案第 2002-166898號為基礎，茲將其全文在此列作參考。 10 【圖式簡單說明】 第1圖乃使用傳統引線框之半導體元件的一個橫截面 |Ξ| · 圃， 第2圖乃第1圖中繪示之半導體元件的橫截面圖，其繪 示了晶片座與密封樹脂之間發生剝落的情形； 15 第3圖乃用於本發明實施例之半導體元件的一個引線 框平面圖； 第4圖為第3圖中繪示之引線框的一個晶片座放大橫截 面圖； 第5圖繪示了將半導體晶片2黏貼於晶片座上面之後進 20 行打線時的引線框平面圖； 第6圖繪示了黏貼於晶片座上面之半導體晶片的放大 侧視圖；以及 第7Α及7Β圖舉例說明了相較於傳統之塗黑處理程序 ，根據本發明形成氧化銅層的一個程序。 15 1231019 玖、發明說明 【圖式之主要元件代表符號表】 1...半導體元件 7、12...内引線 2...半導體晶片 8…密封樹脂 3、10...引線框 9...外引線 4、11...晶片座 14、22…氧化銅層 5...黏晶材料 21...基底材料 6...接合線 23...濃縮層 16

Claims (1)

1231019 拾、申5靑專利範阐 3.10. 第921_34號專财職申請專利範圍修正本 修正曰期·· 93年1 〇曰 1· 一種引線框，其包括有： 月 一個由銅合金製成之基底材料；以及 一層藉將引線框與強氧化_㈣觸而 化銅層，該氧化銅層乃作為最外層且係由so乳 主要組份及Cu作為-次要組份所構成。 ， 2· _請專㈣圍第1項之引線框，其中氧化鋼層之厚戶 為10至1000埃。 又 10 3· 一種引線框製造方法，其包括有： 將銅合金製成之基底材料配置成預定圖案； 將一部分的基底材料進行電鍍；以及 藉將基底材料浸入強氧化劑溶液中，於基底材料 5 表面上形成最外層之氧化銅層，該氧化銅層係由Cu2〇 5 作為一主要組份及Cu作為一次要組份所構成。 (如申請專利範圍第3項之製造方法，其中將基底材料浸 入強氧化劑溶液之時間乃經過調整，以在氧化銅變成 針狀結晶狀態之前將基底材料自強氧化劑溶液中取出。 5· 一種半導體元件，其包括有： 一個在以銅合金製成之基底材料上面形成氧化銅 層的引線框’作為最外層之氧化銅層乃藉將引線框與 強氧化劑溶液接觸而形成，該氧化銅層係由作為 一主要組份及Cii作為一次要組份所構成； 一個黏貼於引線框之預定部分上面的半導體元件 17 1231019 拾、申請專利範圍 :以及 封裝半導體元件之密封樹脂。 6·如申請專利範圍第5項之半導體元件，其中氧化銅層之 厚度為10至1000埃。 18
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US20100310781A1 (en) 2010-12-09
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US8940583B2 (en) 2015-01-27
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KR20030095195A (ko) 2003-12-18
US20030227073A1 (en) 2003-12-11

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