TW521386B - Hexagonal boron nitride film with low dielectric constant, layer dielectric film and method of production thereof, and plasma CVD apparatus - Google Patents

Hexagonal boron nitride film with low dielectric constant, layer dielectric film and method of production thereof, and plasma CVD apparatus Download PDF

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Publication number
TW521386B
TW521386B TW090113728A TW90113728A TW521386B TW 521386 B TW521386 B TW 521386B TW 090113728 A TW090113728 A TW 090113728A TW 90113728 A TW90113728 A TW 90113728A TW 521386 B TW521386 B TW 521386B
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Taiwan
Prior art keywords
film
boron nitride
insulating film
wiring
hexagonal boron
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TW090113728A
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English (en)
Inventor
Hitoshi Sakamoto
Toshihiko Nishimori
Hiroshi Sonobe
Yoshimichi Yonekura
Nobuki Yamashita
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Mitsubishi Heavy Ind Ltd
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Priority claimed from JP2000193734A external-priority patent/JP2002016064A/ja
Priority claimed from JP2001120272A external-priority patent/JP2002334876A/ja
Application filed by Mitsubishi Heavy Ind Ltd filed Critical Mitsubishi Heavy Ind Ltd
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Publication of TW521386B publication Critical patent/TW521386B/zh

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    • C04B35/58—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides
    • C04B35/583—Shaped ceramic products characterised by their composition; Ceramics compositions; Processing powders of inorganic compounds preparatory to the manufacturing of ceramic products based on non-oxide ceramics based on borides, nitrides, i.e. nitrides, oxynitrides, carbonitrides or oxycarbonitrides or silicides based on boron nitride
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    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/0021—Reactive sputtering or evaporation
    • C23C14/0036—Reactive sputtering
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    • C23C—COATING METALLIC MATERIAL; COATING MATERIAL WITH METALLIC MATERIAL; SURFACE TREATMENT OF METALLIC MATERIAL BY DIFFUSION INTO THE SURFACE, BY CHEMICAL CONVERSION OR SUBSTITUTION; COATING BY VACUUM EVAPORATION, BY SPUTTERING, BY ION IMPLANTATION OR BY CHEMICAL VAPOUR DEPOSITION, IN GENERAL
    • C23C14/00—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material
    • C23C14/06—Coating by vacuum evaporation, by sputtering or by ion implantation of the coating forming material characterised by the coating material
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    • C23C16/00—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes
    • C23C16/22—Chemical coating by decomposition of gaseous compounds, without leaving reaction products of surface material in the coating, i.e. chemical vapour deposition [CVD] processes characterised by the deposition of inorganic material, other than metallic material
    • C23C16/30—Deposition of compounds, mixtures or solid solutions, e.g. borides, carbides, nitrides
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    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L21/31—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
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  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

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521386 A7 B7 五、發明説明（1 ) 技術領域 本發明係關於一種可利用來作為低介電率層間絕緣膜材 料之氮化硼膜及其製造方法，以及，關於一種非晶矽太陽 電池、薄膜電晶體、光敏器等之各種半導體元件的膜形成 所使用之電漿 CVD(Chemical Vapor Deposition)裝置。 背景技術 在至今之積體電路中，係廣泛使用矽氧化膜（比介電率 ε = 4〜4.5)作為層間絕緣膜。但，為以次世代之高積體化 為目標，元件訊號延遲之支配原因乃成為配線延遲，為解 決此，必須層間絕緣膜低介電率。矽氧化膜因其比介電率 高，在次世代之積體電路乃無法使用，而尋求更低介電率 之層間絕緣膜材料。在如此之狀況下，有機系材料中，ε <2.5之極低介電率的材料亦存在，但此等尚有耐熱性差之 問題。因此，擁有一種耐熱性優、且石夕氧化膜程度之比1 介電率的氮化硼（ΒΝ)乃倍受注目，而謀求其低介電率化。 在ΒΝ薄膜之製作以往使用一般之電漿CVD法，但氣體源 因使用例如Β2Η6及ΝΗ3，ΒΝ膜中產生ΒΗ、ΝΗ等之氫結 合，無法比介電率3.0以下之低介電率化，在立方晶ΒΝ(以 下，稱「c-BN」）、六方晶ΒΝ(以下，稱「h-BN」）之薄膜 製作，必須使基板溫度400°C為比較高之基板溫度，因熱 引起之金屬配線劣化，無法適用於金屬配線製作程序。 又，自以往，在半導體裝置中之低比介電率（比介電率 = 2.0〜2.7)層間絕緣膜，係已開發出以旋轉塗布法之有機 膜（Hare、SiLK :聚婦丙基醚系高分子、BCB :苯並環丁烯 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 B7 五、發明説明（2 ) 系高分子）及有機、無機混成膜（HSG-R7 :甲基矽氧烷系 SOG、HOSP :氫化甲基準矽氧烷）或、以CVD法產生之有 機膜（a - CF :氟化烴系高分子、AF4 :氟化甘油戊酸酯系 高分子）及有機、無機混成膜（Black Diamond :甲基碎燒 系、4MS :四甲基矽烷系）等之外，尚研究膜構造之多孔質 化。 如前述般，以往之低比介電率層間絕緣膜係為進行低比 介電率化，及減少密度，故有如下問題：氧電漿耐性之降 低、力學強度劣化、熱擴散效率變差、吸濕性、透濕性會 增加、耐熱性下降、對雜質擴散之阻隔效果降低等。故， 在以往，依形成低比介電率層間絕緣膜後之熱處理或CMP (Chemical Mechanical Polishing)等之製程，裝置特性有可能 明顯降低。 因此，本發明之第1目的在於提供一種具有比介電率3.0 以下之六方晶氮化硼膜，並提供一種在不會因熱造成金屬 配線劣化之低溫下的層間絕緣膜製造方法。 又，本發明之第2目的在於提供一種電漿CVD裝置，其 可提昇氧電漿耐性、力學強度、熱擴散效率、吸濕性、透 濕性、耐熱性、對雜質擴散之阻隔效果。 發明之揭示 本發明之低介電率六方晶氮化硼膜、層間絕緣膜及其製 造方法，係提供一種具有比介電率3.0以下之六方晶氮化硼 膜。又，本發明係提供一種六方晶氮化硼膜，其乃使氮原 子與氫原子之結合及硼原子與氫原子之結合的合計含量為 -5- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 B7 五、發明説明（3 ) 4莫耳％以下，其特徵在於：使c軸方向之面間隔相對於3.3 A延伸5〜30%，但使a軸方向之面間隔的延伸相對於2.2 A 抑制至5 %以内，c軸方向相對於基板呈水平方向。進一 步，提供一種使用此等六方晶氮化硼之層間絕緣膜。又， 提供一種六方晶氮化硼膜之製造方法，係於真空中使用一 含有氮離子或氮與稀有氣體之混合離子的照射及硼供給源 蒸鍍之離子蒸鍍法，其特徵在於：使用一不含有與氫原子 結合之原料氣體。 進一步，本發明之電漿CVD裝置其特徵在於具備：成膜 於半導體晶圓之低比介電率的配線間絕緣膜表面，形成一 作為保護膜之低比介電性膜的成膜裝置、及、將半導體晶 圓加熱至特定溫度之加熱裝置。若依此發明，藉成膜裝置 於配線間絕緣膜之表面形成低比介電性膜後，加熱半導體 晶圓，於配線間絕緣膜表面形成保護膜，故與習知相比， 可提高氧電漿耐性、力學性強度、熱擴散效率、吸濕性、 透濕性、耐熱性、對雜質擴散之阻隔效果。又，若依此發 明，因連續地進行低比介電性膜之成膜與加熱處理，故可 謀求製程之縮短化。 又，本發明之電漿CVD裝置其特徵在於具備：於前述半 導體晶圓形成低比介電率之配線間絕緣膜的成膜裝置；於 前述配線間絕緣膜表面形成一作為保護膜之低比介電性膜 的成膜裝置；將半導體晶圓加熱至特定溫度之加熱裝置。 若依此發明，因連續地進行配線間絕緣膜的成膜與保護膜 的成膜，故可進一步謀求縮短製程。 -6- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 521386
又，在上述電漿CVD裝置巾，其特徵在於具備一使配線 間絕緣膜多孔質化之多孔質化裝置。若依本發明，藉多孔 質化裝置使配線間絕緣膜多孔質化，於配線間絕緣膜之表 面形成保護膜，故可謀求製程之縮短化，進一步可提昇多 孔質化膜之弱點即界面特性，以及，可抑制成膜、蝕刻、 灰化引起之膜質劣化、或高吸濕性。 圖面之簡單說明 第1圖係表TF —含有層間絕緣膜之積體電路元件一例的 圖。 罘2圖係表示習知11-；61^膜（第2圖a)、本發明之膜 (第2圖B )。 弟3圖係表示本發明中所使用之離子蒸鍍法的成膜裝置 圖。 第4圖係表示實施形態！所得到之h_BN膜經紅外線吸收 分光（FTIR)測足的結果，區域a係依nh結合之譜峯，區域 B係依BH結合之譜峯所顯現的區域圖。 第5圖係表示本發明之電漿CVD裝置構成圖。 第6圖係表示本發明所製造之半導體元件構成圖。 第7圖係表示本發明之製造製程的流程圖。 第8圖係表示本發明之製造製程的流程圖。 第9圖係表示本發明之製造製程的流程圖。 用以實施發明之最佳形態 (實施形態1 ) 本發月之h-BN膜係可利用來作為低介電率絕緣膜材料。 -7- ^紙張尺度適财_冢標A4規格(210 X 297公釐)-------— 521386
層間絕緣膜係包含於積體電路元件，且使設於基板上之 電極、插件、配線進行絕緣分離之絕緣膜及保護膜，例 如，有元件絕緣膜等，將積體電路元件之一例表示於第丄 圖中。在第1圖中，配線部係由二層所構成。 石夕基板等之基板丨具有源極2、閘極氧化膜3、汲極4、 私極5絶緣膜6等，於其上設有元件絕緣膜7 (例如由矽氧 化膜所構成）。於元件絕緣膜7係設有第丨層層間絕緣膜9， 其乃具有一連接於兀件絕緣膜7之接觸插塞8的配線部忉。 在第1圖中，於層間絕緣膜9之上進一步表示第2層層間絕 緣膜12。第2層層間絕緣膜9中之配線部而介由啤酒插塞 11而連接於第2層層間絕緣膜12中的配線部13。第2層層間 絕緣膜12係被最終保護膜14所保護。最終保護膜14一般由 氮化碎等所構成。 本發明之h-BN層間絕緣膜宜4〇1〜1〇μιη之膜厚，更宜 為0.35 μιη (3’5GG Α) <膜厚。本發明之層間絕緣膜係使習知 之層間絕緣膜的介電率下降，但可與習知層間絕緣膜同樣 地使用’可使用於與習知相同之基板、元件絕緣膜、最終 保護膜等。即使對於配線金屬，肖習知同樣地，可使用銅 或鋁合金。 若依所謂之0.18μιη.計法則，於配線材料使用鋁合金之 層間絕緣材料使用Si〇2(比介電率45)的配線延遲為Μ㈣例 如，半導體周邊材料之最新動向（1999)pl9,東轉研究中 心），_但使用本發明之h_BN作為層間絕緣膜時，進一步可 預想高速化，於配線材料使用銅，並近似於層間絕緣材料
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線 -8 - 521386 A7 B7 五、發明説明（6 ) 使用低介電率絕緣材料之配線延遲即10 ps左右。 本發明之h - BN膜其特徵在於可降低氮原子與氫原子之 結合(NH)及硼原子與氫原子之結合（BH)的量。氫結合之量 可以富利葉變換紅外吸收分光法（FTIR)求得，h BN膜中宜 為4莫耳％以下，進一步宜為0.1莫耳％以下。藉BH、NH等 之氫結合量的降低，可成為比介電率3.0以下之低介電率化。 又，本發明之h - BN膜其特徵在於：於c軸方向之延伸具 有面間隔。面間隔係可依X線繞射法（XRD)或穿透型電子 顯微鏡（TEM)來測定（例如，JCPDS卡No· 34〜421)。h-BN 之面間隔一般於c軸方向為3.3 A，於a軸方向為2.2 A，於b 軸方向為2.2 A。然而，本發明之h-BN對於c軸方向宜為5 〜30%，更宜為10-20%，尤宜為15%延伸者，對於a軸方向 宜為5 %以下，更宜為3 %以下之延伸者。若朝c軸方向延 伸面間隔，h - BN膜因密度變低，可降低介電率。 本發明之h - BN膜其特徵在於c軸方向相對於基板為水平 方向。第2圖表示習知之h-BN膜（第2圖A)、本發明之h- BN膜（第2圖B )。習知之h _ BN膜雖為六方晶，但配向方向 為隨機，近似非晶形。另外，本發明之h - BN膜係六方晶之 c軸方向相對於基板為整齊於水平方向。又，c軸方向若為 水平方向，亦可產生面内旋轉。h - BN膜之結晶構造可藉穿 透型電子顯微鏡（TEM)來測定（例如，T. A. Friedmann、thin solid films, 237(1994) 48-56)。c軸方向相對於基板為水平方 向之h-BN宜為30莫耳％。以上，更宜為70莫耳％以上。於 h - BN膜中，若使c軸方向相對於基板呈水平方向，膜全體 -9- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 __ _B7__ 五、發明説明（7 ) 之分極率會降低，介電率會減少。 氮原子與氫原子之結合（NH)及硼原子與氫原子之結合 (BH)的量減少、使面方向朝c轴方向延伸，使c轴方向相對 於基相呈水平方向，係分別貢獻於h - BN膜之低介電率化。 藉由組合此等，可進一步成為低介電率化。 本發明之h - BN膜係從離子注入氫而產生分子連結性之 混亂，進一步可降低比介電率。分子連結性之混亂可以穿 透型電子顯微鏡（TEM)來測定（例如T. A. Friedmann、thin solid films，237(1994)48-56)。為降低比介電率，較佳係形成 最大50分子左右之連結性混亂，更佳係形成最大15分子左 右之連結性的混亂，會很有效果。藉由產生分子連結性混 亂，膜全體之分極率比無混亂時還更降低，介電率會降低。 又，本發明之h-BN膜係離子注入氫，混入非晶形ΒΝ( α -BN)，可使低介電率化。非晶形BN之存在量可以穿透型電 子顯微鏡（TEM)來測定（例如 T· A· Friedmann、thin solid films， 237(199句48-56)，宜以40莫耳％以下混合。 又，本發明之h-BN膜係離子注入氫，混入c-BN，可使 之低介電率化。c-ΒΝ之存在量可藉穿透型電子顯微鏡 (TEM)等來測足（例如 τ a· Friedmann、thin solid films， 237(1994)48-56)，宜以40莫耳％以下混入。 α - BN與c - BN係可併存在一起，但於h - BN膜中較佳係以 合計為40莫耳％存在。 使a-BN4c_BN混在一起，俾膜全體之分極率降低，介 電率會降低。 -10- 本紙張尺度適用中國國家標準(CNS) A4規格(210X 297公釐） 521386 A7 B7 五、發明説明（8 ) 繼而，說明有關本發明之h - BN膜的製造裝置及製造方 法。 在本發明中所使用之離子蒸鍍法乃謂在真空中含有氮離 子或氮與稀有氣體之混合離子的照射及硼供給源之蒸鍍。 此處，所謂真空係可使蒸鍍成為可能之真空，一般乃使用 10-3〜HT8Torr之範圍。 第3圖表示本發明所使用之以離子蒸鍍法所得到的BN膜 成膜裝置之一例。真空室15係可保持真空之腔室，從排氣 口 15A連通於未圖示之真空源。真空室15係配置基材支ix 體16，基材支ix體16係藉冷卻給排水管16A所導入之冷卻水 進行冷卻，可使安裝於支ix體16之基材17保持於特定的溫 度。對於此基材17，照射一來自離子源19之稀有氣體與氮 之混合氣體經離子化的混合離子，同時從蒸發源18蒸鍍硼 (B)。藉此，可於基板上製造B/N組成比為0.9〜1.1之h-BN 膜。 · 稀有氣體可使用氬或氪，氮供給源可使用一不具氮原子 與氫原子之結合的氮等以取代具有氮原子與氫原子之結合 的氨（NH3)。稀有氣體與氮之混合比係於混合氣體中氮為20 體積％以上，宜為含有50〜90體積％者。使用稀有氣體與 氮之混合比係為提高氮之解離效率。 對基材17供給硼蒸氣之硼供給源，係宜為不具有硼原子 與氫原子之結合的硼供給源，以取代具有硼原子與氫原子 之結合的（B2H6 )，可適當地舉出金屬硼。 離子源19可舉例如考夫曼型離子源、微波放電型離子 -11 - 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 __B7 1、發明説明（9 ) " ’ ' 源。蒸發源18可舉例如電子束蒸發源。 基材17《溫度係藉冷卻給排水管16A所導入之冷卻水來 進行冷卻，宜維持於室溫〜20(rc。在本發明中，因使用不 含有BH結合或NH結合之氮供給源及硼供給源，故於所生 成之BN膜中不產生氮結合（BH、nh)，可降低基材之溫 度’因不產生熱引起之金屬配線劣化，可適用於金屬配線 製作製程。 以下，依實施例具體地說明本發明，但本發明不限於此 等。 實施例1 使用以第3圖所示之離子蒸鍍法的BN膜製造裝置。於真 空室15内之基材支汝體16安裝p型矽基材作為基材17。對此 矽基板（基材溫度200 C )以0.5 kV之加速電壓照射一來自考 夫X型離子-惑氬：氮（N) = 64 : 36混合而成的離子（流量 =5 seem)作為離子源19,同時並從作為蒸發源18之電子束 蒸發源以0.5 A/s之速度供給硼（B)，形成b/n組成比為1之h · BN膜。成膜中之真空室1内真空度為1〇>< 1〇·4 T〇rr。 所得到之h-BN膜經紅外線吸收分光（FTIR)測定的結果表 示於第4圖中°從圖4明顯可知，於第4圖之區域a不存在 NH結合（3340 cm 4 ’而於同區域B不存在bh結合（2520 cm-1)。 所得到之h-BN膜進行容量一電壓（CV)測定（例如，M. z. Karim、surface and coatings technology，60(1993)502-505)，俾算 出比介電率ε後，ε =2.4。 所得到之h - ΒΝ膜斷面經穿透型電子顯微鏡（ΤΕΜ)觀察 -12- 本紙張尺度適用中國國家榡準(CNS) Α4規格(210 X 297公釐） 521386 A7 B7 五、發明説明（1〇 ) 後，c軸方向而間隔從一般之間隔3 . 32.5 A擴展至3.73 A。 此時，h - BN之c軸方向相對於矽基板為水平方向。 實施例2 與實施例1同樣地做法，製造h - BN膜，於所得到之h - BN 膜以能量15 keV、注入量1 X 1016 cnT2之條件注入氫離子。 其後，進行CV測定，算出比介電率後，ε = 2.2。又，TEM 觀察該h-BN膜斷面後，c軸方向而間隔從一般之間隔3. 32.5 A擴展至3.73 A，結晶之周期性為60 A以下，a - BN及 c-BN混在一起，此時，h-BN之c軸方向相對於矽基板為水 平方向。 實施例1與實施例2中係為不含氫而使用無氫結合之氣體 源，又，使氣體源離子化、加速而賦予能量，可在基板溫 度200°C之低溫製造h - BN膜。又，h - BN膜之c軸方向面間 隔係從3.3 A延伸至3.7 A，其c軸方向相對於基板為水平方 向。藉由此等，可使h - BN膜之比介電率低介電率化至2.4。 又，將氫離子注入於所得到之h - BN膜，混亂結晶之周 期性，使α · BN及c - BN混在一起，並使h - BN膜之比介電率 進一步降低至2.2。 如以上般，本發明之h _ BN膜乃使用來作為一比矽氧化 膜（ε = 4〜4.5)還低介電率的層間絕緣膜，可裝作更高積體 化之元件。 其次，以實施形態2〜4詳細說明有關本發明之電漿CVD裝置。 (實施形態2 ) 第5圖係表示本發明之實施形態2〜4構成的圖。在此圖 -13- 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐)
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線 521386 A7 B7 五、發明説明（11 ) 中，表示一利用電漿氣相激發而於半導體元件形成多層膜 的電漿CVD裝置。此電漿CVD裝置係將構成薄膜之元素所 構成的原料氣體供給於半導體晶圓上，藉由在氣相或半導 體晶圓表面之化學反應形成特定薄膜的裝置。為激發氣體 分子可使用電漿放電。 在第5圖中，於反應容器20之内侧面設有一用以放出上 述原料氣體之噴嘴21、喷嘴22。從喷嘴22係以H2、N2、
He、Ar等稀釋至5 %以下之B2H6以總流量100〜1000 seem放 出作為從鋼瓶（未圖示）所供給之原料氣體。又，從喷嘴21 係 100% N2、100% NH3 或 N2+NH3 以總流量 100〜1000 seem放 出作為鋼瓶（未圖示）所供給之原料氣體。 RF電極23係設於反應容器20之上部，連接於高周波電源 24。偏壓電極25係以與RF電極23對向之方式設於反應容器 20内，連接於高周波電源26。此等之RF電極23及偏壓電極 25係為產生電場。RF電極23之RF電源為1 kW以上，偏壓電 極25之偏壓電源為0.5 kW以上。 磁場線圈27係捲繞於反應容器20的周圍，產生旋轉水平 磁場（10〜300高斯）者。12英吋徑之半導體晶圓28係以與上 述電場正交的方式載置於偏壓電極25上。在此半導體晶圓 28之表面可藉後述之製程形成低比介電率BN膜29。此處， 所謂低介電率BN膜乃由硼源（B) : B2H6、BC13、氮源（N)N2、 NH3所構成的低介電率保護膜。又，磁場線圈27非必然者。 第6圖表示以實施形態2〜4所製造之半導體元件100的構 成。在同圖所示之半導體元件100中，基本電晶體101、 -14- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
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線 521386 A7 B7 五、發明説明（12 ) 101、…乃以元件間分離膜102絕緣。基本電晶體101、 101、…之表面乃形成 BPSG (Boro_Phospho-Silicate-Glass)等之 配線下絕緣膜103。 金屬配線104係形成於配線下絕緣膜103的表面，介由一 貫通配線下絕緣膜103之接觸孔所形成的配線間金屬105， 而連接於基本電晶體101。進一步，於配線下絕緣膜103(金 屬配線104)之表面形成配線間絕緣膜106。配線間絕緣膜 106為降低寄生容量，乃由低比介電率材料所構成。於配 線間絕緣膜106之表面可形成一作為保護膜之低比介電率 BN膜 107。 金屬配線108係形成於低比介電率BN膜107的表面，介由 一貫通配線間絕緣膜106及低比介電率BN膜107之接觸孔所 形成的配線間金屬109，而連接於金屬配線104。進一步於 低比介電率BN膜107(金屬配線108)表面形成配線間絕緣膜 110。配線間絕緣膜110之表面係形成一作為保護膜之低比 介電率BN膜111。此配線間絕緣膜110為降低寄生容量，乃 由低比介電率材料所構成。 金屬配線112係形成於低比介電率BN膜111之表面，介電 一貫通配線間絕緣膜110及低比介電率BN膜111之接觸孔所 形成的配線間金屬113，而連接於金屬配線108。如此，半 導體元件100係成為多層膜構造。 繼而，參照第7圖所示之流程圖，同時並說明有關實施 、形態2之製造製程。以下，主要說明第6圖所示之低比介電 率BN膜107的成膜製程。此時，在第5圖所示之半導體晶圓 -15- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 B7 五、發明説明（13 ) 28上係形成至第6圖所示之配線間絕緣膜106者。但，未形 成配線間金屬109。 在第7圖所示之步騾SA1中，於半導體晶圓28的表面（配 線間絕緣膜106)係形成低比介電率膜’。具體上，從喷嘴22 係以H2、N2、He、Ar等稀釋至5 %以下之B2H6#總流量100 〜1000 seem放出。又，從喷嘴21亦100% N2、100% NH3或 N2+NH3以總流量100〜1000 seem放出作為由鋼瓶（未圖示）所 供給之原料氣體。藉此，在反應容器20内混合上述原料氣 體，於配線間絕緣膜106之表面形成低比介電率膜。 在步騾SA2中，係進行熱處理，其乃反應容器20内之半 導體晶圓28藉加熱裝置（未圖示）加熱至300〜400°C。藉 此，在步騾SA3中，係於配線間絕緣膜106的表面形成低比 介電率BN膜107。此低比介電率BN膜107之比介電率為2.2。 低比介電率BN膜107基本上擁有六方晶之結晶構造，其組 成為[B]/[N] = 1。進一步，低比介電率BN膜107之膜厚係形 成有效的20〜100 nm作為保護膜。 步騾SA4中，係對低比介電率BN膜107及配線間絕緣膜 106進行一用以形成接觸孔之蝕刻。在步騾SA5中，於所形 成之接觸孔埋入配線間金屬109。在步驟SA6中，藉CMP研 磨表面。在步騾SA7中，係於低比介電率BN膜107表面形 成金屬配線108。以下，反覆實施步騾SA1以後之製程，俾 可製造第6圖所示之多層膜構造的半導體元件100。 又，於實施形態2中，係由前述之硼源（B)及氮源（N)構 成第6圖所示之絕緣膜103、106、110，亦可採用使此等形 -16- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386 A7 B7 五、發明説明（14 ) 成低介電率BN膜之構成。 如此，若依實施形態2，於配線間絕緣膜106之表面形成 低比介電率性膜後，加熱半導體晶圓28，於配線間絕緣膜 106之表面形成低比介電率BN膜107，故，與習知比較，可 提昇氧電漿耐性、力學強度、熱擴散效率、吸濕性、透濕 性、耐熱性、對雜質擴散之阻隔效果。 又，若依實施形態2，因在反應容器20内可連續地實施 低比介電性膜的成膜與加熱處理，可謀求製程之縮短化。 (實施形態3 ) 在前述實施形態2中，係說明有關於反應容器20内進行 低比介電率BN膜107或低比介電率BN膜111的成膜例，但亦 可於反應容器20内進行配線間絕緣膜106或配線間絕緣膜 110的成膜。以下，說明此情形作為實施形態3。 繼而，參照第8圖所示之流程圖，並說明有關實施形態3 之製造製程。以下，主要說明第6圖所示之配線間絕緣膜 106及低比介電率BN膜107的成膜製程。此時，在第5圖所 示之半導體晶圓28，係形成至第6圖所示之配線下絕緣膜 103及金屬配線104。 第8圖所示之步驟SB1中係藉周知之CVD法形成反應容器 20内之半導體晶圓28表面（配線下絕緣膜103、金屬配線 104)、配線間絕緣膜106。在步騾SB2中，係經過前述步騾 SA1〜步騾SA3(參照圖7 )，而於配線間絕緣膜106的表面形 成低比介電率BN膜107。 此處，至步騾SB3〜步騾SB6之處理，因係與步騾SA4〜 -17- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐） 521386 A7 B7 五、發明説明（15 ) 步驟SA7(參照圖7 )相同，故省略其說明。以下，藉由反覆 實施步騾SB1以後的製程，俾可製造第6圖所示之多層膜構 造的半導體元件100。 如此，若依實施形態3，在反應容器20内連續地實施配 線間絕緣膜106的成膜與低比介電率BN膜107的成膜，故可 進一步謀求製程之縮短化。 (實施形態4 ) 在前述實施形態2中，係說明有關於反應容器20内進行 低比介電率BN膜107或低比介電率BN膜111的成膜例，但， 亦可進行配線間絕緣膜106或配線間絕緣膜110的多孔質 化。以下，以此情形作為實施形態4中來進行說明。 其次，參照第9圖所示之流程圖，並說明有關實施形態4 之製造製程。以下，主要說明第6圖所示之配線間絕緣膜 106的多孔質化及低比介電率BN膜107的成膜製程。此時， 在第5圖所示之半導體晶圓28中，係形成至第6圖所示之配 線間絕緣膜106。但，未形成配線間絕緣膜109。 在第9圖所示之步騾SCI中，於半導體晶圓28的表面（配 線間絕緣膜106)係與步騾SA1(參照圖7 )同樣，而形成低比 介電率膜。在步驟SC2中，藉由已知之多孔質化法，使配 線間絕緣膜106多孔質化。藉此，配線間絕緣膜106之密度 會變小，被低比介電率化。 在步騾SC3中，係與步驟SA2及步騾SA3(參照第7圖）同樣 地，於配線間絕緣膜106的表面形成低比介電率BN膜107。 此處，步驟SC4〜步騾SC7之處理因係與步驟SA4〜步驟 -18- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐) 521386
SA7(參照第7圖）同樣，故省略其說明。以下，反覆實施步 驟S C1以後之絮赶 施也】Λ _ 私俾製造弟6圖所示之多層膜構造之半導 體元件100。 浚此若依實施形態4，因使配線間絕緣膜106多孔質 於配、泉間絶緣膜106的表面形成低比介電率ΒΝ膜107， 故可m %之短縮化’進—步’可提昇多孔質化膜之弱 17界面特〖生，同時並可抑制成膜、姓刻、灰化引起之膜 質劣化或高吸濕性。 、上叙若依本發明，藉成膜裝置於配線間絕緣膜的 夕成低比A %性膜後，加熱半導體晶圓，於配線間絕 彖膜々表面形成保護膜，故，與習知相比，可提昇氧電 水耐性、力學強度、熱擴散效率、吸濕性、透濕性、耐熱 性、對雜質擴散之阻隔效果。 又，若依本發日月，因連續地進行低比介電性膜的成膜與 加熱處理’故可謀求製程之縮短化。 進而，若依本發明，因連續地進行配線間絕緣膜之成膜 與保護膜之成膜，故可進一步謀求製程之縮短化。 又，若依本發明，藉多孔質化裝置使配線間絕緣膜多孔 質^於配線間絕緣膜之表面形成保護膜，故可謀求製程 之、、猫釔化，進一步可提昇多孔質化膜之弱點即界面特性， 同時並可抑制成膜、侧、灰化引起之膜質劣化或高濕性。 -19- 本紙張尺度適种@國家標準(CNS)城格(摩挪公爱） 裝 訂
線

Claims (1)

  1. ^-· .........52isr *飞 L|^28號專利申請案 鼻 利範圍修正本（91年11月) A BCD 六、申請專利範圍 1 · 一種六方晶氮化硼膜，其特徵在於：使氮原子與氫原 子之結合及硼原子與氫原子之結合的合計含量為4莫耳 %以下。 2 . —種六方晶氮化硼膜，其特徵在於：對於六方晶氮化 硼’使c軸方向之面間隔相對於3 3 a延伸5〜30%，但使 a軸方向之面間隔的延伸相對於2.2 a抑制於5 %以内。 3· —種六方晶氮化硼膜，其特徵在於^軸方向相對於基板 呈水平方向。 4· 一種層間絶緣膜，其特徵在於：係使用申請專利範圍 第1〜3項中之任一者的六方晶氮化硼膜。 5 .根據申請專利範圍第4項之層間絕緣膜，其中前述六方 晶氮化棚膜乃含有：40莫耳％以下之非晶形氮化硼、 或、40莫耳％以下之立方晶氮化硼膜、或合計為4〇莫耳 /〇以下之非晶形氮化棚與立方晶氮化棚。 6 · —種六方晶氮化硼膜之製造方法，其係使用離子蒸鍍 法，其乃含有在真2中氮離子或氮與稀有氣體之混合 離子的照射，及硼供給源的蒸鍍，其特徵在於：使用 一不含與氫原子結合之氮及硼供給源。 7.根據申請專利範圍第6項之六方晶氮化硼膜的製造方 法’其中前述成膜基板溫度為2〇〇°c以下。 8·根據申請專利範圍第6或7項之六方晶氮化硼膜的製造 方法’其中進一步含有使氫進行離子注入之步驟。 本紙張尺度適Wis家料(CNS) A4規格㈣X 297公釐) ----^ 521386 A B c D 六、申請專利範圍 9. 一種電漿CVD裝置，其特徵在於具備： 於半導體晶圓上成膜之低比介電率的配線間絕緣膜 表面，形成一作為保護膜之低比介電性膜的成膜裝 置； 將前述半導體晶圓加熱至特定溫度之加熱裝置。 10. —種電漿CVD裝置，其特徵在於具備： 於前述半導體晶圓形成低比介電率之配線間絕緣膜 的成膜裝置； 於前述配線間絕緣膜之表面形成一作為保護膜的低 比介電性膜之成膜裝置； 將前述半導體晶圓加熱至特定溫度之加熱裝置。 11. 根據申請專利範圍第10項之電漿CVD裝置，其中具備一 使前述配線間絕緣膜多孔質化之多孔質化裝置。 -2- 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐）
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KR20020001584A (ko) 2002-01-09
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EP1167291A1 (en) 2002-01-02
US20040058199A1 (en) 2004-03-25

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