TW517374B - Packaged integrated circuit - Google Patents
Packaged integrated circuit Download PDFInfo
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- TW517374B TW517374B TW090105029A TW90105029A TW517374B TW 517374 B TW517374 B TW 517374B TW 090105029 A TW090105029 A TW 090105029A TW 90105029 A TW90105029 A TW 90105029A TW 517374 B TW517374 B TW 517374B
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- H—ELECTRICITY
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- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/58—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries
- H01L23/585—Structural electrical arrangements for semiconductor devices not otherwise provided for, e.g. in combination with batteries comprising conductive layers or plates or strips or rods or rings
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
- H01L23/49855—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers for flat-cards, e.g. credit cards
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- H01L2223/66—High-frequency adaptations
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- H01L2224/02—Bonding areas; Manufacturing methods related thereto
- H01L2224/04—Structure, shape, material or disposition of the bonding areas prior to the connecting process
- H01L2224/05—Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
- H01L2224/0554—External layer
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
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- H01L2224/42—Wire connectors; Manufacturing methods related thereto
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- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
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- H01L2224/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
- H01L2224/85—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a wire connector
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
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- H01L2924/00014—Technical content checked by a classifier the subject-matter covered by the group, the symbol of which is combined with the symbol of this group, being disclosed without further technical details
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- H01L2924/10—Details of semiconductor or other solid state devices to be connected
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- H01L2924/14—Integrated circuits
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- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
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- H01L2924/19—Details of hybrid assemblies other than the semiconductor or other solid state devices to be connected
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Description
517374 Α7 __ Β7 _ 五、發明說明(1 ) 本發明係關於一種如申請專利範圍第1項之導言中所 說明之封裝積體電路β 在該項技藝,例如在1999年1 1月8日’自 ATMEL宣告,、ATMEL宣告藍牙解決辦法〃,連 同ΑΤΜΕ L藍牙解決辦法背景資料 > 不再有電纜藍.牙無 線標準及ATMEL Corporation之即刻推出藍牙解決辦法〃, 巳知此種封裝積體電路,該二文件均發表於ΑΤΜΕ L網 址。在該二文件中,說明一種藍牙收發機係由一多晶片模 組所構成,其包括在一球狀格栅陣列封裝之無線電,基帶 及快閃記憶體。此模組予以組裝在一印刷電路板,連同性 質不同之外部個別組件,諸如一濾波器及一天線。因爲此 種收發機使用在不同種類之小型手提式裝置,此種收發機 裝置應該必要爲很小。另外計及預期大量之此等收發機應 用在藍牙支援裝置,此種收發機之生產成本及安裝成本應 該低。 本發明之一項目的,爲提供一種以上巳知類型之封裝 積體電路,但其相對於巳知者爲較小,並有減低之成本。 根據本發明,此目的係藉在申.請專利範圍第1項說明 之封裝積體電路所達成。 L· (請先Μ讀背面之注意事項再填寫本頁) 實在,此目的係藉在一在封裝積體電路實施之積體電 路晶粒提供至少一射頻組件,同時射頻天線也予以整合在 相同封裝所達成。在一包括一天線之部份之整個封裝,可 予以整合在一種無線電應用,諸如一種藍牙應用,代替將 一射頻模組及一單獨之天線合倂在一印刷電路板,供在此 本紙张尺度適用中國國家標準(CNS)A4規格(2]0 X 297公釐) 517374 A7 五、發明說明(2 (請先閱讀背面之注意事項再填寫本頁) 種無線電應用’諸如藍牙之應用。以此方式,便節省在印 刷電路板及在無線電應用外殼之空間,並同時減低實施無 線電應用之成本,因爲僅需要一動作,代替一動作供安裝 無線電模組,及一動作供安裝天線在印刷電路板,以及隨 後處理二元件之互相連接。 在申請專利範圍第2項中,說明本發明之另一特徵說 明實施例。 射頻天線係以至少一金屬物體在一容納封裝積體電路 之元件之積體電路封裝內所構成。使用一在積體電路封裝 內之現有或另外金屬物體,在積體電路之封裝內便構成天 線。 隨後分別在申請專利範圍第3及4項中說明本發明之 特徵說明實施例。 線· 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 在該二替代性實施例,使用一在封裝內之金屬物體, 供實施射頻天線。首先,在申請專利範圍第3項,藉金屬 線接合將例如積體電路晶粒之輸出耦合至一輸出終端,而 構成整合射頻天線。如果一金屬線接合之長度爲目標爲將 行予以接收或傳輸之無線電信號波長之1 / 2 λ或1 / 4 λ ’此便爲可行。第二,在申請專利範圍第4項,作爲 一種替代,使用一在積體電路封裝內之金屬引線框架,作 爲射頻天線。 在申請專利範圍第5項中說明本發明之一另外特徵說 明實施例。 作爲另一替代性射頻天線’可使用至少一平面金屬圖 本紙張尺度適用中國國家標準(CNS〉A4規格(2]〇χ 297公釐) -5- 517374 A7 B7 經濟部智慧財產局員工消費合作社印奴 五、發明說明(3 ) 案作爲天線。將金屬圖案模製在封裝材料,或將圖案完成 在封裝之表面,藉以可將此種至少一金屬圖案包括在積體 電路封裝。 另外,天線係由一接地金屬平面所構成。圖案及接地 平面在積體電路封裝內被一絕緣層所分開。 在申請專利範圍第6項中,說明本發明之又一特徵說 明實施例。 射頻天線係由一平面縫隙圖案置於一接地基板上所構 成。此基板予以完成在一積體電路封裝之表面。使用一種 具有高電介質常數之陶瓷材料,藉以可甚至更使在陶瓷基 板上之射頻天線尺寸最小。 在申請專利範圍第7項中,也說明本發明之另一特徵 說明實施例。 在接地基板上之射頻天線之縫隙圖案,係由一第一 S -形縫隙所構成,此第一 S -形縫隙之長度確定將行予以 接收或傳輸之射頻信號之諧振頻率。切開部之S -形導致 一非線性變化極化輻射圖案。應用此整形天線之技術,僅 只對天線之形狀或尺寸略作修改,便方便使射頻天線適合 另一諧振頻率。以此方式,天線便爲頻率可調諧。 在申請專利範圍第8項中,說明本發明之一隨後特徵 說明實施例。 除第一 S -形縫隙外,另有一相對於第一 s —形縫隙 旋轉9 0度之第二S -形縫隙。此第二s -形縫隙在射頻 信號之操作頻率之諧波頻率抑制較高階諧振,並從而減少 (請先W讀背面之注意事項再填寫本頁) ,# 訂· · •線 本紙张尺度適用中國國家標準(CNS)A4規格(2]0><297公釐) -6- 517374 A7 五、發明說明(4 (請先閱讀背面之注意事項再填寫本頁) 射頻彳s號之帶寬。切開部之s -形導致一非線性極化幅射 圖案,並且二S -形縫隙之組合不僅界定諧振頻率及帶寬 ,而且除了所需要之射頻信號外,並抑制所有其他諧波頻 率’藉以也構成某些濾波器特徵。應用此整形天線之技術 ’僅只對天線之形狀或尺寸略作修改,便方便使射頻天線 適合另一諧振頻率,並且也抑制其他諧波頻率。以此方式 ’天線便也爲帶寬可調諧。應用第二S -形天線本身,提 供一種濾波器特徵,藉以減低應用一另外濾波元件之需要 〇 在後附申請專利範圍第9 ,1 0及1 1項中,述及本 發明之另外特徵說明實施例。 將此種射頻模組整合在一標準積體電路封裝,諸如一 球狀格柵陣列封裝,方形扁平包裝封裝或一小輪廓封裝, 或任何其他標準封裝,封裝藉以可藉標準設備,諸如一焊 料流動機或測試設備予以處理,產生成本上之減低。使用 此等標準封裝,藉以也減少總體無線電設備之大小及成本 另外,本發明也係關於一種射頻模組,包括至少一如 以上所說明之封裝積體電路。 參照一實施例之下列說明,配合附圖,將會更明白本 發明之以上及其他諸多目的及特色,並將會最佳瞭解本發 明本身,在附圖中: 圖1表示一在其中實施一射頻模組’連同一射頻天線 之球狀格柵陣列封裝;圖2表示在圖1之射頻模組中所使 本紙张尺度適用中國國家標準(CNS)A4規格(2]〇χ 297公釐) 517374 A7 B7 五、發明說明(5 ) 用縫隙天線之圖案 主要元件對照表 A 點A B 點B G N D PL 平面金屬 層 G N D P L 1 接地平面 I C D 積體電路 晶 粒 I C P 平面金屬 層 I c P A 球狀格栅 陣 列 封裝 M E T 第一金屬 化 層 P C B 印刷電路 板 R F A 天線 S 1 第一S - 形 縫 隙 s 2 第二S - 形 縫 隙 V 1 通道孔 V 2 通道 k V 3 通道孔 ΐ V 4 通道 1 丨才 V 5 通道 ί h V 6 通道孔 ----------ίιιΛ^ —— (請先閱讀背面之注意事項再填寫本頁) •線 在下列諸段,請參照附圖,將說明一根據本發日月& $ 法之實施。在此說明之第一部份,說明如在圖1中所提出 本紙张尺度適用中國國家標準(CNS)A4規格(2]0 X 297公釐) 517374 % A7 ________ B7 五、發明說明(6 ) ,在其中實施本發明之封裝積體電路之球狀格柵陣列封裝 I C P A之主要元件。此部份後繼爲在每一前所述元件間 (請先閱讀背面之注意事項再填寫本頁) 之所有互相連接之說明。隨後說明本發明實施之實際執行 〇 本發明之球狀格栅陣列(Ball Grid Array,簡稱 BGA)封裝I CPA爲一種可安裝在印刷電路板( 經濟部智慧財產局員工消費合作社印製
Printed CircuitBoard,簡稱P C B )之腔向下封裝。此 BGA封裝基本上由平面金屬層GNDPL,I CP,藉 絕緣層分開所構成。絕緣層係以一種陶瓷材料所完成。在 球狀格柵陣列封裝I C P A之頂部,完成一第一金屬化層 MET。天線RFA使用熟知縫隙技術,在金屬化層 Μ E T予以蝕刻。在射頻天線下面有一陶瓷絕緣層及平面 金屬層GND P L,用作接地平面。另外在接地平面 GNDPL下面有另一絕緣層及金屬層I CP,用作一互 相連接平面。在此層I CP,在一積體電路晶粒I CD之 所有接腳與所有輸出連接器或內部元件間之互相連接予以 蝕刻。B G A封裝之輸出終端,爲可焊接在印刷電路板 P C B之焊球。 積體電路晶粒I C D內含電子射頻組件,諸如電晶體 ,電容器,電感器,及電阻器。 在所有元件之間使用通道孔,進行垂直互相連接,其 爲在絕緣層塡滿金屬之孔。利用焊球完成至印刷電路板 P C B之連接。 射頻天線R F A之終端藉通道孔諸如V 1 ,及藉在層 本紙张尺度適用中國國家標準(CNS)A4規格(2]〇χ 297公发) -9- 517374 A7 B7 五、發明說明(7 ) (請先閱讀背面之注意事項再填寫本頁) I CP之金屬互相連接,耦合至積體電路晶粒I CD。使 用在印刷電路板P C B耦合至一接地平面GND P L 1之 通道孔V3及V6 ,接地平面GNDPL連接至電接地。 積體電路晶粒I C D也藉通道V 2親合至接地平面 GND P L。通道V 4及V 5用以將積體電路晶粒信號輸 出耦合至安裝在印刷電路板P C B之其他隨後元件。積體 電路晶粒I C D之接腳經由金屬線接合W B耦合至互相連 接平面I C P。 .線 在圖2中,示如在B GA封裝之頂部,在第一金屬化 層所構成之射頻天線R F A之更多細節。天線R F A使用 熟知縫隙技術予以蝕刻,此處”縫隙”意爲一在金屬圖案 之開口。天線R F A係由一第一 S —形縫隙S 1及一相對 於第一 S -形縫隙旋轉9 0度之第二S -形縫隙S 2所構 成。天線被一在天線邊緣之通道孔V Η之正方形陣列所包 圍。 在下段,解釋先前所述元件之關聯性及定位。 經濟部智慧財產局員工消費合作社印製 首先,使用腔向下封裝,將晶粒置於在二接地平面 GNDPL及GNDPL I之間,藉以方便將積體電路晶 粒I C D自輻射屏蔽。在另一方面,應用接地平面 G N D P L,藉以也將射頻天線R F Α自積體電路晶粒 I CD屏蔽。此結構使能將一積體電路晶粒I CD及一天 線R F A合倂在一封裝內,而無相互影響及/或性能干擾 〇 天線R F A係由一縫隙圖案置於一陶瓷絕緣層所構成 -1〇- 本紙張尺度適用中國國家標準(CNS)A4規格(2】〇χ 297公釐) 517374 A7 B7 五、發明說明(8 ) (請先M讀背面之注意事項再填寫本頁) 。因爲陶瓷材料之高電介質常數ε r ,及準確控制層之尺 寸,諸如厚度及圖案布局之能力,而可使天線尺寸最小, 並可準確複製天線尺寸。縫隙圖案本身係由二S 一形縫隙 SI ’ S2旋轉9 0度所構成。第一 S —形縫隙S1之長 度確定天線諧振頻率。第二S -形縫隙S 2在操作頻率之 諧波頻率抑制較高階諧振並減少帶寬。切開部之S 一形導 致一非線性極化輻射圖案,並且二S -形縫隙之組合不僅 界定諧振頻率及帶寬,而且除了所需要之射頻信號外,也 抑制所有其他諧波頻率,藉以界定有些濾波器特徵。 切開部之S -形~導致一非線性極化輻射圖案。應用此 整形天線之技術。僅只對天線之形狀或尺寸略作修改,便 方便使射頻天線適合另一諧振頻率,並且也抑.制其他諧波 頻率。以此方式,天線爲頻率可調諧。 痤齊^pitp曰慧讨轰导員!.肖費合咋fi-屮泣 而且,應用此整形天線之技術。僅只對天線之形狀或 尺寸略作修改,便方便使射頻天線適合另一諧振頻率,並 且也抑制其他諧波頻率。以此方式,天線也爲帶寬可調諧 。應用第二S -形天線本身具有濾波器特徵,便免除需要 應用一另外濾波元件。 天線被一正方形陣列之通道孔所包圍,其使在天線邊 緣之金屬化接地,俾避免邊緣效應。 天線在圖2之點A及B予以差分激勵,利用在此二點 之通道孔作成連接至晶粒。而且,自點A及點B所見之阻 抗,由於天線之對稱而爲確切相同。 供使天線之大小最小,天‘線-濾波器以及在矽及天線 本紙張尺度適用中國國家標準(CNS)A4規格(2]〇χ_297公发) -11 - 517374 A7 ___B7 _ 五、發明說明(9 ) 之間屏蔽所使用之技術,使得可將所有無線電功能整合至 一供藍牙應用之很小晶片封裝解決辦法。 要述及的是,在積體電路封裝使用金屬物體,諸如金 屬線接合及金屬引線框架之實施例,也適合在封裝積體電 路內實施一射頻天線。 另外要述及的是,代替使用一種B GA封裝,也可使 用一種小輪廓封裝,一種方形扁平包裝封裝,或任何其他 標準封裝,以提供與B G A封裝所提供之相同優點。本發 明也可應用於內含在陶瓷材料以外之其他材料所完成絕緣 層之封裝。 雖然以上業經配合特定裝置說明本發明之原理,但請 •予淸楚瞭解,此說明僅意在作爲實例,而不作爲對於如在 後附申請專利範圍所界定本發明之範圍之限制。 (請先閱讀背面之注意事項再填寫本頁) 經濟部智慧財產局員工消費合作社印ίκ 本紙張尺度適用中國國家標準(CNS)A4規格(2]ϋ X 297公发) -12-
Claims (1)
- 517374 A8 B8 C8 ___D8 六、申請專利範圍 附件一:第901 05029號專利申請案 中文申請專利範圍修正本 (請先閱讀背面之注意事項再填寫本頁) 民國91年11月15日修正 1 . 一種封裝積體電路(P I C),包含至少一射頻 組件,包括在一與一射頻·天線(R F A )關連之積體電路 晶粒(I C D )中,該積體電路晶粒(I c D )以包括在 δ亥封裝積體電路(P I C )中,該射頻天線也包括在該封 裝積體電路封裝(P I C )中,並排除在該積體電路晶粒 (I c D )外,其特徵在於一屏蔽安插介於該積體電路晶 粒和該射頻天線間,其中該積體電路藉由路由過該屏蔽之 金屬線而直接連接至該射頻天線。 2 ·如申請專利範圍第1項之封裝積體電路(Ρ I c ),其特徵爲,該封裝積體電路(P I C )包括一積體電 路封裝(I C P A ),其容納該至少一射頻組件及該射頻 天線(R F A ),其由至少一爲該積體電路封裝之一部份 之金屬物體所構成。 經濟部智慧財產局員工消費合作社印製 3 ·如申請專利範圍第2項之封裝積體電路(Ρ I C ),其中,該射頻天線(R F A )予以施加在該積體電路 封裝(I C Ρ A )之一金屬引線,框架。 4 .如申請專利範圍第1項之封裝積體電路(ρ I C ),其中,該射頻天線(R F A )係由至少一平面金屬圖 案’藉一絕緣層與該屏蔽分開所構成。 · 5 .如申請專利範圍第4項之封裝積體電路(Ρ I C 本紙張尺度適用中國國家標準(CNS ) A4規格(210X297公釐) < 517374 經濟部智慧財產局員工消費合作社印製 A8 B8 C8 D8 六、申請專利範圍 ),其中,該平面金屬圖案爲一金屬縫隙圖案,及該絕緣 層爲陶瓷層。 6 ·如申請專利範圍第5項之封裝積體電路(P I c ),其中,該縫隙圖案係由一第一 S -形縫隙所構成。 7 ·如申請專利範圍第6項之封裝積體電路(P I C ),其中,該射頻天線(P F A )包含一相對於該第一 S 一形縫隙旋轉9 0度之第二S -形縫隙。 8 ·如申請專利範圍第1項之封裝積體電路(p I C ),其中,該積體電路封裝(I C P A )爲一球狀格柵陣 列封裝。 9 ·如申請專利範圍第1項之封裝積體電路(p I C ),其中,該積體電路封裝(1〇?六)爲~種方形扁平 包裝封裝。 1〇.如申請專利範圍第1項之封裝積體電路( p I c ),其中,該積體電路封裝爲一種小輪廓封裝。 1 1 · 一種射頻模組,其特徵在於包括至少—如串請 專利範圍第1至1 0項之任何一項之封裝積體電路( P I C )。 本紙張尺度適用中國國家標準(CNS ) A4規格(210 X 297公釐) ^ 訂------ (請先閱讀背面之注意事項再填寫本頁) -2-
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JPS63181505A (ja) * | 1987-01-23 | 1988-07-26 | Nippon Telegr & Teleph Corp <Ntt> | 小形スロツトアンテナ |
JPH0685530A (ja) * | 1992-08-31 | 1994-03-25 | Sony Corp | マイクロストリップアンテナ及び携帯無線機 |
JPH06196924A (ja) * | 1992-10-29 | 1994-07-15 | Sanyo Electric Co Ltd | マイクロ波アンテナ |
US5528222A (en) * | 1994-09-09 | 1996-06-18 | International Business Machines Corporation | Radio frequency circuit and memory in thin flexible package |
JPH08250913A (ja) * | 1995-03-15 | 1996-09-27 | Honda Motor Co Ltd | Mmicパッケージ組立 |
JP3266491B2 (ja) * | 1996-02-29 | 2002-03-18 | 京セラ株式会社 | 高周波用パッケージ |
-
2000
- 2000-02-18 EP EP00400459A patent/EP1126522A1/en not_active Ceased
-
2001
- 2001-01-31 JP JP2001022627A patent/JP2001292026A/ja not_active Withdrawn
- 2001-02-03 KR KR1020010005267A patent/KR20010082044A/ko not_active Application Discontinuation
- 2001-02-15 CN CN01104524A patent/CN1369914A/zh active Pending
- 2001-02-16 US US09/784,015 patent/US20010052645A1/en not_active Abandoned
- 2001-02-16 SG SG200100864A patent/SG94765A1/en unknown
- 2001-03-05 TW TW090105029A patent/TW517374B/zh not_active IP Right Cessation
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7602050B2 (en) | 2005-07-18 | 2009-10-13 | Qualcomm Incorporated | Integrated circuit packaging |
TWI406447B (zh) * | 2006-01-26 | 2013-08-21 | Ibm | 與由封裝的引線形成之天線一起封裝之積體電路晶片之裝置及方法 |
Also Published As
Publication number | Publication date |
---|---|
CN1369914A (zh) | 2002-09-18 |
JP2001292026A (ja) | 2001-10-19 |
EP1126522A1 (en) | 2001-08-22 |
US20010052645A1 (en) | 2001-12-20 |
SG94765A1 (en) | 2003-03-18 |
KR20010082044A (ko) | 2001-08-29 |
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