TWI487085B - 具屏蔽之積體電路封裝件系統 - Google Patents

具屏蔽之積體電路封裝件系統 Download PDF

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TWI487085B
TWI487085B TW097140394A TW97140394A TWI487085B TW I487085 B TWI487085 B TW I487085B TW 097140394 A TW097140394 A TW 097140394A TW 97140394 A TW97140394 A TW 97140394A TW I487085 B TWI487085 B TW I487085B
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lead
integrated circuit
shield
package
die
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TW097140394A
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TW200929507A (en
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Seng Guan Chow
Byung Tai Do
Heap Hoe Kuan
Rui Huang
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Stats Chippac Ltd
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Description

具屏蔽之積體電路封裝件系統 相關申請案的交互參照
本申請案包含與同時申請的美國專利申請案相關的標的，該美國申請案由Rui Huang,Byung Tai Do,Seng Guan Chow,以及Heap Hoe Kuan所申請,名稱為“INTEGRATED CIRCUIT PACKAGE SYSTEM FOR ELECTROMAGNETIC ISOLATION”。相關的申請案已經讓渡給STATS ChipPAC Ltd.以及被編為檔案編號27-455。
本發明一般係關於積體電路封裝件系統,以及尤關於具屏蔽之積體電路封裝件系統。
增進組件微型化、較大積體電路(ICs)封裝密度、更高的效能以及較低的成本為電腦工業持續的目標。半導體封裝件結構繼續朝微型化精進，以在從此製成之產品的尺寸減少時增加封裝於其中之組件的密度。這樣是反應資訊和通訊產品對於持續減少尺寸、厚度和成本以及持續增加效能之持續增加的需求。
這些對於微型化增加的需求是尤其要注意的，例如，在可攜式的資訊和通訊裝置像是手機(cellular phone)、免持的手機耳機(hand free cellular headsets)、個人資料輔助器(“PDA’ s”)、攝錄影機(camcorders)、手提電腦(notebook computer)以及諸如此類等。持續更小和更薄型地製造所有的這些裝置以增進他們的可攜性。因此，被併入這些裝置裡的大型積體電路(“LSI”)封裝件需要做的更小以及更薄。罩著和保護LSI的封裝件組態也一樣需要做的更小和更薄。
許多傳統的半導體(或晶片)封裝件皆是以樹脂(諸如：環氧模製化合物)模製半導體晶粒至封裝件的形式。封裝件具有導腳自封裝件主體向外突出的導腳框，以提供用於在晶粒和外部裝置之間訊號傳輸的路徑。其他的傳統封裝件組態係具有直接形成在封裝件的表面上之接觸端子或接觸墊。像這樣的傳統半導體封裝件係按照下列製程所製作出來：晶粒接合製程(將半導體晶粒設置在導腳框的踏板上)、打線製程(使用導腳框導線電性連接踏板上之半導體晶粒至內導腳)、模製製程(以環氧樹脂將包含有晶粒、內導腳以及導腳框導線的組合件之預定部分囊封起來，形成封裝件主體)以及修整(trimming)製程(完成每一個組合件作為個別、獨立的封裝件)。
因此所製造的半導體封裝件藉由配對和焊接其外部導腳框或接觸墊至電路板上之配對圖案，因而使電源和訊號的輸入/輸出(I/O)運作介於封裝件的半導體裝置和電路板之間。
對於微型化的需求的反應，為了要設置高頻LSI鄰近其他高頻LSI，減少半導體晶粒之間的距離以達到其較高的密度。這樣的作法卻導致LSI被干擾(更具體來說是指電磁的干擾(electromagnetic interference,EMI))的影響增加的問題。
傳統上，用於解決EMI的問題之技術是以金屬封裝件結構覆蓋半導體裝置的封裝件。然而，這樣的金屬封裝件結構一般必須要被設置在印刷電路板上作為和半導體裝置分隔的獨立組件，因此具有金屬封裝件結構的封裝件尺寸增加，因而妨礙或限制了封裝件的微型化。此外，金屬封裝件結構係形成為和半導體裝置分隔的組件，因而增加了製造成本。
有多種封裝件方法試圖於半導體封裝件內提供屏蔽。然而，這必須將訂製結構納入計算，如積體電路尺寸、高度以及任何堆疊組態和其他在封裝件中的元件，諸如：接合線或其他裝置。同時，需要定製以附接屏蔽至適當的接地源。所有的考慮，以及其他的考量因素，增加了製造製程的複雜度，減少良率並增加成本。
因此，仍然有提供低製造成本、增加良率、減少積體電路封裝件尺寸以及解決干擾所造成的問題之積體電路封裝件系統的需求。有鑑於持續增加之節省成本和增進效能的需求，找到上述問題的答案亦越來越重要。
已經找尋對於這些問題的解決方法很久，但先前技術發展並沒有教示或揭露任何解決方法並且，因此，這些問題的解決方式也困擾本發明所屬技術領域中具有通常知識者很久。
本發明提供積體電路封裝方法包含：形成第一導腳和第二導腳；連接積體電路晶粒與第一導腳；於積體電路晶片、第一導腳以及第二導腳上形成封裝體，且暴露第二導腳的頂側的一部分；以及於封裝體、第一導腳以及第二導腳上形成屏蔽，且屏蔽並未和第一導腳接觸。
本發明的某些具體實施例具有除了上述之外之其他態樣或是置換上述的態樣。對於本發明所屬技術領域中具有通常知識者而言，當參照附加的圖式閱讀以下詳細敘述時，這些態樣為顯而易知的。
以下的具體實施例係充分詳細描述以使本發明所屬技術領域中具有通常知識者能製作和使用發明。應瞭解的是，根據本發明的揭露，其他具體實施例將為顯而易知，且可在未悖離本發明的範疇內做出系統、製程或機構的改變。
於下列敘述中，係給定多個具體細節以提供對本發明之完整瞭解。然而，顯然可在沒有這些具體細節下實施本發明。為避免混淆本發明，一些已知的電路、系統組態及製程步驟未詳細地揭露。同樣地，系統的具體實施例所顯示的圖式係為半概略的且未按比例，且特別地，一些尺寸是為了清楚呈現，並且誇大地顯示於圖式中。一般來說，本發明可於任何方位下操作。
另外，在揭露及描述具有某些共同特徵之多個具體實施例，為了清楚及容易說明、描述及理解，彼此相似及相同特徵一般將以相同的元件符號來描述。已編號為第一具體實施例、第二具體實施例等的具體實施例係為了方便描述，且並不意圖具有任何其他意義或提供本發明限制。
為了說明的目的，本文所使用的術語“水平(horizontal)”係定義為與積體電路的平面或表面平行之平面，無論其定位。術語“垂直(vertical)”係指垂直所定義的“水平”之方向。術語諸如：“在…上面(above)”、“在…下面(below)”、“底部(bottom)”、“上方(top)”、“側邊”(如在“側壁”)、“較高(higher)”、“較低(lower)”、“上面的(upper)”、“於…上(over)”以及”在…之下(under)，係相對於水平平面而定義，術語“在…之上(on)”係指在元件間有直接接觸。本文所使用之術語“處理(processing)”係包含材料的沈積、圖案化、曝光、顯影、蝕刻、清潔、製模，以及/或材料的移除或如所需要形成上述結構。本文所使用之術語”系統(system)”代表且係指依照使用術語之上下文，本發明之方法及設備。
現請參閱第1圖，顯示於本發明第一具體實施例中之積體電路封裝件系統100的上視圖。上視圖繪示覆蓋積體電路封裝件系統100的屏蔽102。屏蔽102之中心水平部分104係較高於鄰接積體電路封裝件系統100之四邊的周邊水平部分106。在中心水平部分104以及週邊水平部分106之間為非水平部分108。
現請參閱第2圖，顯示沿著第1圖的線2--2之積體電路封裝件系統100的剖面圖。剖面圖繪示以黏著劑(adhesive)214(諸如：晶粒附接黏著劑)設置於晶粒附接墊(die-attach pad)212上的積體電路晶粒210，和第一導腳216。封裝體218(諸如：環氧模製化合物)覆蓋積體電路晶粒210以及第一導腳216。屏蔽102保形地覆蓋封裝體218的上表面。
屏蔽102能以多種不同的傳導材料形成。例如，屏蔽102能由金屬、傳導樹脂、箔以及傳導膜形成。屏蔽102可能連接至接地基準(ground reference)或者其他電壓位準之基準以提供對於積體電路封裝件系統100的電磁干擾屏蔽。
第一導腳216的一部份為第一導腳216的頂側220半蝕刻以形成較低部分222，以使得封裝體218能在第一導腳216的較低部分222和屏蔽102之間。封裝體218能避免屏蔽102和第一導腳216之間的電性短路。
積體電路晶粒210具有非主動面(non-active side)224以及主動面(active side)226，其中，主動面226包含製作在其上的主動電路。在此實施例中，非主動面224較佳面對晶粒附接墊212。晶粒附接墊212和第一導腳216係共平面。內部互連228(諸如：接合線或帶狀接合線)可以連接主動面226和晶粒附接墊212之間，以及主動面226和第一導腳216之間。
為了說明的目的，第一導腳216和晶粒附接墊212皆顯示為連接至主動面226上的相同接合墊(bond pad)。雖然，應瞭解的是晶粒附接墊212和第一導腳216可能不必連接至主動面226上的相同位置。例如，晶粒附接墊212可以電性連接至接地基準以及第一導腳216可以連接至積體電路晶粒210上之不同接合墊。
現請參閱第3圖，顯示沿著第1圖的線3--3之積體電路封裝件系統100的剖面圖。剖面圖繪示以黏著劑214設置於晶粒附接墊212上以及於角落導腳(corner lead)330上的積體電路晶粒210。封裝體218係於積體電路晶粒210和角落導腳330之上。
角落導腳330自晶粒附接墊212延伸出去。於晶粒附接墊212的相對端部之角落導腳330的一部分較佳地從封裝體218暴露。屏蔽102係形成於角落導腳330的暴露端部上以及較佳電性連接至角落導腳330。在實施例例中，屏蔽102可以通過角落導腳330和晶粒附接墊212連接至接地基準，以提供對於積體電路封裝件系統100的EMI屏蔽。
現請參閱第4圖，顯示沿著第1圖的線4--4之積體電路封裝件系統100的剖面圖。剖面圖繪示設置於晶粒附接墊212以及第二導腳432上的積體電路晶粒210。封裝體218係於積體電路晶粒210、晶粒附接墊212以及第二導腳432上。
第二導腳432的上部係較佳從封裝體218暴露。屏蔽102係形成於第二導腳432之上部以及較佳地電性連接至第二導腳432。在實施例中，屏蔽102可以透過第二導腳432連接至接地基準或其他電壓位準的基準，以提供對於積體電路封裝件系統100的EMI屏蔽。
亦發現本發明提供可撓性EMI之結構和製造，而提供低封裝高度、低成本以及改良的良率。第一導腳的半蝕刻使得第一導腳和封裝體上的保形屏蔽隔離。這使得第一導腳能夠用於其他功能，諸如：訊號導腳，而不限於提供用於屏蔽的基準。角落導腳、第二導腳或兩者的組合可以對提供EMI功能的屏蔽提供接地連接。
現請參閱第5圖，顯示用於形成第1圖之積體電路封裝件系統100的導腳框502的一部分之上視圖。上視圖繪示晶粒附接墊212、繫桿(tie bar)534、屏障桿(dam bar)536、第一導腳216以及第二導腳432。第一導腳216和第二導腳432係自屏障桿536延伸出來。第一導腳216包括鄰近屏障桿536之較低部分222。可從第2圖之第一導腳216的頂側220半蝕刻較低部分222。
繫桿534連接屏障桿536與晶粒附接墊212之間。屏障桿536在積體電路封裝件系統100的製造製程期間支撐導腳。屏障桿536係以諸如為分割(singulation)製程的製造製程移除。屏障桿536的移除可以自繫桿534形成角落導腳330。
現請參閱第6圖，顯示在本發明的第二具體實施例中，沿著第1圖的線2--2之第1圖上視圖所例示之積體電路封裝件系統600的剖面圖。剖面圖繪示在晶粒附接墊612與封裝體618上之屏蔽602。剖面圖亦繪示以黏著劑614(諸如：晶粒附接黏著劑)設置在晶粒附接墊612之下的積體電路晶粒610。封裝體618(諸如：環氧模製化合物)可能在積體電路晶粒610以及第一導腳616上。屏蔽602在封裝體618上。
屏蔽602能以多種不同的傳導材料製成。例如，屏蔽602能由金屬、傳導樹脂、箔、傳導膜或傳導環氧化物形成。屏蔽602可能連接至接地基準或者其他電壓位準之基準，以提供對於積體電路封裝件系統600的電磁干擾(EMI)屏蔽。
第一導腳616的一部分係自頂側620向下半蝕刻以形成較低部分622，以使得封裝體618能隔離第一導腳616的較低部分622和屏蔽602。封裝體618能避免屏蔽602和第一導腳616之間的電性短路。
積體電路晶粒610具有非主動面624以及主動面626，其中，主動面626包含製作在其上的主動電路。在此實施例中，非主動面624較佳地面對晶粒附接墊612。封裝體618可暴露晶粒附接墊612。屏蔽602可能耦合至晶粒附接墊612之暴露部分。具有連接至接地基準的屏蔽602，晶粒附接墊612亦可以作用為部分EMI屏蔽。
內部互連628(諸如：接合線或帶狀接合線)可以連接主動面626和第一導腳616的非水平內部分，以及連接晶粒附接墊612和第一導腳616的非水平內部分之間。為了說明的目的，積體電路晶粒610和晶粒附接墊612皆連接至第一導腳616的相同位置。然而，應瞭解的是，晶粒附接墊612和積體電路晶粒610可以連接至第一導腳616的不同位置。例如，晶粒附接墊612可以藉由第一導腳616，在預定位置連接至接地基準。
積體電路封裝件系統600可具有相似於第2圖的積體電路封裝件系統100之結構。例如，積體電路封裝件系統600也可以包含第4圖的第二導腳432或第3圖的角落導腳330，以使得屏蔽602可以耦合至其一或兩者，用於接地或基準連接。
現請參閱第7圖，顯示在本發明的第二具體實施例中，沿著第1圖的線2--2之第1圖上視圖所例示之積體電路封裝件系統700的剖面圖。剖面圖繪示於晶粒附接墊712和封裝體718上的屏蔽702。剖面圖也繪示用諸如為晶粒附接劑之黏著劑714設置於晶粒附接墊712下方的積體電路晶粒710。封裝體718，諸如：環氧模製化合物，可位於積體電路晶粒710和第一導腳716上。屏蔽702係於封裝體718上。
屏障702能以多種不同的傳導材料製成。例如，屏蔽702能由金屬、傳導樹脂、箔或傳導膜形成。屏蔽702可能連接至接地基準或者其他電壓位準之基準，以提供對於積體電路封裝件系統700的電磁干擾(EMI)屏蔽。
第一導腳716的一部分係自頂側720向下半蝕刻以形成較低部分722，以使得封裝體718能隔離第一導腳716的較低部分722和屏蔽702。封裝體718能避免屏蔽702和第一導腳716之間的電性短路。
積體電路晶粒710具有非主動面724以及主動面726，其中，主動面726包含製作在其上的主動電路。在此實施例中，主動面726較佳面對晶粒附接墊712。封裝體718可暴露晶粒附接墊712。屏蔽702可耦合至晶粒附接墊712之暴露部分。具有連接至接地基準的屏蔽702，晶粒附接墊712亦可作用為部分EMI屏蔽。
內部互連728(諸如：接合線或帶狀接合線)可以連接主動面726和第一導腳716的頂側，以及連接晶粒附接墊712的非水平內部分和第一導腳716的頂側720之間。為了說明的目的，積體電路晶粒710和晶粒附接墊712皆連接至第一導腳716的相同位置。然而，應瞭解的是，晶粒附接墊712和積體電路晶粒710可以連接至第一導腳716的不同位置。例如，晶粒附接墊712可以藉由第一導腳716，在預定位置連接至接地基準。
積體電路封裝件系統700可能具有相似於第2圖的積體電路封裝件系統100之結構。例如，積體電路封裝件系統700也可以包含第4圖的第二導腳432或第3圖的角落導腳330，以使得屏蔽702可以耦合至其一或兩者，用於接地或基準連接。
現請參閱第8圖，顯示在附接積體電路晶粒210之步驟中之第2圖的結構。剖面圖繪示以黏著劑設置於晶粒附接墊212上之積體電路晶粒210。顯示具有較低部分222之第一導腳216鄰近晶粒附接墊212。視需要具有晶粒附接墊212。
現請參閱第9圖，顯示於連接內部互連228的步驟中的第8圖之結構。剖面圖繪示設置於晶粒附接墊212上的積體電路晶粒210。內部互連228可連接積體電路晶粒210和晶粒附接墊212之間，以及積體電路晶粒210和第一導腳216之間。
現請參閱第10圖，顯示於形成封裝體218的步驟中之第9圖之結構。剖面圖繪示設置於晶粒附接墊212上且連接第一導腳216的積體電路晶粒210。封裝體218可以用很多種方式形成。例如，第9圖的結構可以置於模製槽(mold chase)(未顯示)之間並且可能經過模製製程以形成封裝體218。
現請參閱第11圖，顯示於形成屏蔽102的步驟中之第10圖之結構。剖面圖繪示形成在積體電路晶粒210、晶粒附接墊212、內部互連228以及第一導腳216上的封裝體218。屏蔽102係保形地形成於封裝體218之上表面上。屏蔽102能以多種不同的方式形成。例如，屏蔽102能以塗佈(coating)、電鍍(plating)、濺鍍(sputtering)、噴霧(spraying)、塗抹(painting)、滾壓(rolling)和層壓(laminating)形成或被覆在封裝體218上。
現請參閱第12圖，顯示在本發明具體實施例中之用於製造積體電路封裝件系統100的積體電路封裝方法1200的流程圖。方法1200包含在方塊1202中，形成第一導腳和第二導腳；在方塊1204中，連接積體電路晶粒與第一導腳；在方塊1206中，形成封裝體於積體電路晶粒、第一導腳以及第二導腳上，且暴露第二導腳頂側的一部分；以及在方塊1208中，形成屏蔽於封裝體、第一導腳以及第二導腳上，且屏蔽沒有接觸到第一導腳。
本發明的另一個重要的態樣是其有價值地支持和提供減少成本、簡化系統以及增加效能的歷史趨勢。
本發明的這些及其他有價值的態樣因此促進技術的狀態到至少下一個水準。
因此，發現本發明的積體電路封裝件系統提供重要且迄今未知且不可得的解決方法、性能以及功能性態樣，用於改善良率、增加可靠度以及減少電路系統的成本。所得的製程和組態係簡單、有成本效益、不複雜、高度多功能地、準確、靈敏以及有效，並且可以調整已知組件來實施，以快速、有效以及經濟地製造、應用和利用。
儘管本發明係以特定的最佳模式描述，可瞭解到根據上述描述，眾多替代、修飾及變化對本發明所屬技術領域中具有通常知識者而言為顯而易見的。據此，意於包含落入所附之申請專利範圍範疇內的所有這類的替代、修飾及變化。在本文提出的所有事項或顯示於圖式者係理解為說明而非用於限制。
100、600、700．．．積體電路封裝件系統
102、602、702．．．屏蔽
104．．．屏蔽之中心水平部分
106．．．屏蔽之週邊水平部分
108．．．屏蔽之非水平部分
210、610、710．．．積體電路晶粒
212、612、712．．．晶粒附接墊
214、614、714．．．黏著劑
218、618、718．．．封裝體
216、616、716．．．第一導腳
220、620、720．．．第一導腳之頂側
222、622、722．．．第一導腳之較低部分
224、624、724．．．非主動面
226、626、726．．．主動面
228、628、728．．．內部互連
330．．．角落導腳
432．．．第二導腳
502．．．導腳框
534．．．繫桿
536．．．屏障桿
1200．．．積體電路封裝方法
1202、1204、1206、1208．．．方塊
第1圖係在本發明之第一具體實施例中的積體電路封裝件系統的上視圖；
第2圖係沿著第1圖之線2--2的積體電路封裝件系統的剖面圖；
第3圖係沿著第1圖之線3--3的積體電路封裝件系統的剖面圖；
第4圖係沿著第1圖之線4--4的積體電路封裝件系統的剖面圖；
第5圖係於形成第1圖之積體電路封裝件系統的導腳框的一部分之上視圖；
第6圖係於本發明的第二具體實施例中，沿著第1圖的線2--2之第1圖上視圖所例示之積體電路封裝件系統的剖面圖；
第7圖係於本發明的第三具體實施例中，沿著第1圖的線2--2之第1圖上視圖所例示之積體電路封裝件系統的剖面圖；
第8圖係於附接積體電路晶粒的步驟中之第2圖之結構；
第9圖係於連接內部互連的步驟中之第8圖之結構；
第10圖係於形成封裝件封裝體的步驟中之第9圖之結構；
第11圖係於形成屏蔽的步驟中之第10圖之結構；以及
第12圖係於本發明具體實施例中之製造積體電路封裝件系統的積體電路封裝方法的流程圖。
100．．．積體電路封裝件系統
102．．．屏蔽
210．．．積體電路晶粒
212．．．晶粒附接墊
214．．．黏著劑
216．．．第一導腳
218．．．封裝體
220．．．第一導腳之頂側
222．．．第一導腳之較低部分
224．．．非主動面
226．．．主動面
228．．．內部互連

Claims (10)

  1. 一種積體電路封裝方法，包括：形成第一導腳和第二導腳；連接積體電路晶粒與該第一導腳；於該積體電路晶粒、該第一導腳以及該第二導腳上形成封裝體，且暴露該第二導腳頂側的一部分；以及於該封裝體、該第一導腳以及該第二導腳之上形成屏蔽，且該屏蔽並未和該第一導腳接觸，其中，形成該第一導腳包含於該第一導腳的頂側形成較低部分，以及形成該屏蔽包含於該較低部分上形成屏蔽且其間有該封裝體。
  2. 如申請專利範圍第1項之積體電路封裝方法，其中，該較低部分係遠離該積體電路晶粒。
  3. 如申請專利範圍第1項之積體電路封裝方法，其中，於該第二導腳上形成該屏蔽包含於該第二導腳之上形成該屏蔽。
  4. 如申請專利範圍第1項之積體電路封裝方法，復包括：形成角落導腳；以及其中形成該屏蔽包含：於該角落導腳上形成該屏蔽。
  5. 如申請專利範圍第1項之積體電路封裝方法，復包括連接該屏蔽至基準位準。
  6. 一種積體電路封裝件系統，包括：第一導腳； 鄰近該第一導腳之第二導腳；連接該第一導腳之積體電路晶粒；於該積體電路晶粒、該第一導腳以及該第二導腳上的封裝體，且具有暴露的該第二導腳頂側一部分之該第二導腳；以及形成於該封裝體、該第一導腳以及該第二導腳上的屏蔽，且該屏蔽並未和該第一導腳接觸，其中，該第一導腳包含在該第一導腳頂側之較低部分，以及該屏蔽包含於該較低部分上的該屏蔽，而其間有該封裝體。
  7. 如申請專利範圍第6項之積體電路封裝件系統，其中，該較低部分係遠離該積體電路晶粒。
  8. 如申請專利範圍第6項之積體電路封裝件系統，其中，該屏蔽係在該第二導腳上。
  9. 如申請專利範圍第6項之積體電路封裝件系統，復包括：角落導腳；以及其中該屏蔽包括：於該角落導腳上的該屏蔽。
  10. 如申請專利範圍第6項之積體電路封裝件系統，復包括：連接該基準位準的該屏蔽。
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Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US8959762B2 (en) 2005-08-08 2015-02-24 Rf Micro Devices, Inc. Method of manufacturing an electronic module
JP4380748B2 (ja) * 2007-08-08 2009-12-09 ヤマハ株式会社 半導体装置、及び、マイクロフォンパッケージ
US7902644B2 (en) * 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation
DE102009054517B4 (de) 2009-12-10 2011-12-29 Robert Bosch Gmbh Elektronisches Steuergerät
CN102148168B (zh) * 2010-02-04 2015-04-22 飞思卡尔半导体公司 制造具有改进抬升的半导体封装的方法
TWI404187B (zh) * 2010-02-12 2013-08-01 矽品精密工業股份有限公司 能避免電磁干擾之四方形扁平無引腳封裝結構及其製法
US9137934B2 (en) 2010-08-18 2015-09-15 Rf Micro Devices, Inc. Compartmentalized shielding of selected components
US8084300B1 (en) 2010-11-24 2011-12-27 Unisem (Mauritius) Holdings Limited RF shielding for a singulated laminate semiconductor device package
US20120126378A1 (en) * 2010-11-24 2012-05-24 Unisem (Mauritius ) Holdings Limited Semiconductor device package with electromagnetic shielding
US8835226B2 (en) 2011-02-25 2014-09-16 Rf Micro Devices, Inc. Connection using conductive vias
US9627230B2 (en) * 2011-02-28 2017-04-18 Qorvo Us, Inc. Methods of forming a microshield on standard QFN package
US8802555B2 (en) * 2011-03-23 2014-08-12 Stats Chippac Ltd. Integrated circuit packaging system with interconnects and method of manufacture thereof
US8969136B2 (en) 2011-03-25 2015-03-03 Stats Chippac Ltd. Integrated circuit packaging system for electromagnetic interference shielding and method of manufacture thereof
US9030841B2 (en) * 2012-02-23 2015-05-12 Apple Inc. Low profile, space efficient circuit shields
US8853834B2 (en) * 2012-12-13 2014-10-07 Powertech Technology Inc. Leadframe-type semiconductor package having EMI shielding layer connected to ground
US9807890B2 (en) 2013-05-31 2017-10-31 Qorvo Us, Inc. Electronic modules having grounded electromagnetic shields
CN104576565A (zh) * 2013-10-18 2015-04-29 飞思卡尔半导体公司 具有散热体的半导体器件及其组装方法
CN105070710A (zh) * 2015-09-01 2015-11-18 苏州日月新半导体有限公司 集成电路封装体及其形成方法
US11127689B2 (en) 2018-06-01 2021-09-21 Qorvo Us, Inc. Segmented shielding using wirebonds
US11219144B2 (en) 2018-06-28 2022-01-04 Qorvo Us, Inc. Electromagnetic shields for sub-modules
US11114363B2 (en) 2018-12-20 2021-09-07 Qorvo Us, Inc. Electronic package arrangements and related methods
US11515282B2 (en) 2019-05-21 2022-11-29 Qorvo Us, Inc. Electromagnetic shields with bonding wires for sub-modules
DE102019131857B4 (de) * 2019-11-25 2024-03-07 Infineon Technologies Ag Ein halbleiterbauelement mit einer dose, in der ein halbleiterdie untergebracht ist, der von einer einkapselung eingebettet ist

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679975A (en) * 1995-12-18 1997-10-21 Integrated Device Technology, Inc. Conductive encapsulating shield for an integrated circuit

Family Cites Families (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2530056B2 (ja) 1989-09-14 1996-09-04 株式会社東芝 樹脂封止型半導体装置及びその製造方法
US5166772A (en) 1991-02-22 1992-11-24 Motorola, Inc. Transfer molded semiconductor device package with integral shield
JPH06275759A (ja) 1993-03-17 1994-09-30 Fujitsu Ltd 半導体装置及びその製造方法
US5294826A (en) 1993-04-16 1994-03-15 Northern Telecom Limited Integrated circuit package and assembly thereof for thermal and EMI management
JPH0786458A (ja) 1993-09-09 1995-03-31 Fujitsu Ltd 半導体装置及びその製造方法
FR2774810B1 (fr) * 1998-02-10 2003-06-06 St Microelectronics Sa Boitier semi-conducteur blinde et procede pour sa fabrication
US6092281A (en) 1998-08-28 2000-07-25 Amkor Technology, Inc. Electromagnetic interference shield driver and method
US6734539B2 (en) 2000-12-27 2004-05-11 Lucent Technologies Inc. Stacked module package
US6707168B1 (en) 2001-05-04 2004-03-16 Amkor Technology, Inc. Shielded semiconductor package with single-sided substrate and method for making the same
US6847115B2 (en) 2001-09-06 2005-01-25 Silicon Bandwidth Inc. Packaged semiconductor device for radio frequency shielding
US6603193B2 (en) 2001-09-06 2003-08-05 Silicon Bandwidth Inc. Semiconductor package
US7187060B2 (en) 2003-03-13 2007-03-06 Sanyo Electric Co., Ltd. Semiconductor device with shield
US20070071268A1 (en) * 2005-08-16 2007-03-29 Analog Devices, Inc. Packaged microphone with electrically coupled lid
US7582951B2 (en) 2005-10-20 2009-09-01 Broadcom Corporation Methods and apparatus for improved thermal performance and electromagnetic interference (EMI) shielding in leadframe integrated circuit (IC) packages
US7626247B2 (en) 2005-12-22 2009-12-01 Atmel Corporation Electronic package with integral electromagnetic radiation shield and methods related thereto
DE112006003664B4 (de) * 2006-02-01 2011-09-08 Infineon Technologies Ag Herstellung eines QFN-Gehäuses für eine integrierte Schaltung und damit hergestelltes QFN-Gehäuse und Verwendung eines Leiterrahmens dabei
US7479692B2 (en) 2006-11-09 2009-01-20 Stats Chippac Ltd. Integrated circuit package system with heat sink
US20080157302A1 (en) * 2006-12-27 2008-07-03 Lee Seungju Stacked-package quad flat null lead package
US7902644B2 (en) 2007-12-07 2011-03-08 Stats Chippac Ltd. Integrated circuit package system for electromagnetic isolation

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5679975A (en) * 1995-12-18 1997-10-21 Integrated Device Technology, Inc. Conductive encapsulating shield for an integrated circuit

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