TWI493632B - 具有無彎曲晶片之積體電路封裝件系統 - Google Patents

具有無彎曲晶片之積體電路封裝件系統 Download PDF

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Publication number
TWI493632B
TWI493632B TW101111657A TW101111657A TWI493632B TW I493632 B TWI493632 B TW I493632B TW 101111657 A TW101111657 A TW 101111657A TW 101111657 A TW101111657 A TW 101111657A TW I493632 B TWI493632 B TW I493632B
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Taiwan
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layer
semiconductor wafer
adhesive layer
stress relaxation
integrated circuit
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TW101111657A
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English (en)
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TW201237970A (en
Inventor
Byung Tai Do
Il Kwon Shim
Antonio B Dimaano Jr
Heap Hoe Kuan
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Stats Chippac Ltd
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Publication of TW201237970A publication Critical patent/TW201237970A/zh
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Publication of TWI493632B publication Critical patent/TWI493632B/zh

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Description

具有無彎曲晶片之積體電路封裝件系統
本發明係大致關於一種積體電路封裝件系統，且更詳而言之，係關於一種晶片在指狀引線(leadfinger)上之積體電路封裝件系統。
目前電腦工業進行的目標為提升構件的微小化、更好的積體電路(IC)封裝密度、較高性能及較低成本；由於技術的進步，當發行新一代的IC產品時，傾向減少製造該些產品的裝置數量，並同時增加該些產品的功能性。現代消費型電子產品，尤其是個人可攜式裝置，例如：行動電話、數位相機、記憶卡、MP3播放器及其他個人音樂播放器(Personal music player,PMP)，均需增加功能，以配合日漸縮小的實體空間。
半導體封裝結構不斷朝微小化及薄型化的方向突破，以增加封裝其中之構件密度，同時減少由半導體封裝結構所形成之產品的尺寸，這回應了對於資訊與通訊設備的愈趨減少的尺寸、厚度、和成本、連同愈趨增加性能的連續增加的需求。
這些增加的對於微小化之需求是值得特別注意，例如：在可攜式資訊與通訊裝置(如行動電話、免持式行動電話耳機(hands-free cell phone headsets)、個人數位助理(PDA)、攝錄影機(camcorder)、筆記型個人電腦等)中，不斷將所有的這些裝置製作得更小和更薄，以改善它們之可攜化；故加入至這些裝置中之大型積體電路(large-scale integrated circuit，LSI)封裝件需要製作得更小和更薄，且用以收容及保護LSI封裝件的封裝組構亦需製作得更小和更薄。
許多習知半導體晶粒(或晶片)封裝件的型式為：以樹脂(例如環氧樹脂模製化合物)將一半導體晶片模製(mold)成封裝件；該封裝件具有一導線架(leadframe)，且該導線架具有突出於該封裝件本體之引線(lead)，以提供用以在該晶片與外部裝置之間訊號轉換的路徑；其他習知封裝件組構具有直接形成在該封裝件表面的接觸端點(contact terminal)或墊(pad)。
這樣習知半導體封裝件之製法步驟為：晶粒接合(die-bonding)製程(將該半導體晶片安裝至導線架上)、線接合(wire-bonding)製程(將該半導體晶片電性連接該導線架之指狀引線)、模製製程(用環氧樹脂包覆包含該晶片及導線架之組合件的預定部分，以形成封裝件本體)、以及修整(trimming)製程(使組合件之各者完成為個別單獨的封裝件)。
接著藉由對應焊接其外部引線或接觸墊至電路板上之對應圖案來安裝以此方式製作成的該半導體封裝件，以從而啟動在該封裝件中之半導體裝置與該電路板之間的電力與訊號的輸入/輸出(I/O)操作。
在電子工業中眾所皆知的例示半導體封裝件係為球柵陣列(ball-grid array,BGA)；BGA封裝件一般係包括：例如印刷電路板(PCB)之基板，且其中半導體晶粒具有安裝至該基板頂側(top side)的許多接合墊(bond pad)，以藉線接合把該接合墊電性連接至該PCB頂側上之一系列金屬跡線(trace)；此系列金屬跡線經由位於該PCB外周圍附近的一系列通孔(via)以連接至該PCB背面上之第二系列金屬跡線；該第二系列金屬跡線之各者之終端具有貼有(attach)導電焊料球(conductive solder ball)之接觸墊；一般而言，該半導體晶粒及該線接合被包覆在模製化合物內。
現今已採用更輕薄短小之封裝件設計及安裝/接合組構，以回應進一步微小化之持續需求；同時，使用者要求半導體封裝件在更加嚴峻的操作條件下有更好之可靠度。
在一解決方案中，係為將一黏著層敷設(apply)於該晶圓平面上，而非敷設於該個別晶片上，以改善生產力及降低製造成本；該黏著層需部分固化(cure)，以使該黏著層可用來將該晶片貼至該指狀引線上。
因為對於半導體裝置有增進微小化及增進更大的封裝密度之需求，所以變得期望使半導體晶圓厚度薄到小於250μm(大約10密爾(mil))，不幸地，對封裝製程而言，該厚度之晶圓面臨挑戰。
在固化部分該黏著層後，由於該晶圓之矽及該黏著層之材料之間的熱膨脹係數(Coefficient of Thermal Expansion,CTE)不吻合(mismatch)，將使晶圓產生翹曲(warp)或彎曲(bow)，此翹曲將造成問題，因為該晶圓將無法平放以黏合(taping)、切割(dicing)、及/或晶粒貼合(die attaching)。
故，對於積體電路封裝系統仍維持需要較低成本、較高性能、提升微小化、及較高封裝密度，以提供且支援具有達到最佳薄度、高密度佔用面積(footprint)之能力之半導體系統。鑑於商業競爭壓力持續增長、連同於市場中消費者期望的增長及對於有意義的產品差異性的機會縮小，解決這些問題是關鍵的；此外，節省成本、改善效率與性能、及對抗競爭壓力的需求使得更加迫切地要找到這些問題的答案關鍵。
這些問題的答案已經長期被尋找，但是先前的發展並未教示或建議任何解決方案，且因此，這些問題的答案已經長期難倒熟習此技藝之人士。
本發明提供一種積體電路封裝系統，包括：半導體晶片；位於該半導體晶片上的應力緩和層(stress-relieving layer)；位於該應力緩和層上的黏著層；以及接合至該黏著層的電性互連(electrical interconnect)。
本發明之某些實施例具有除上述那些之外或取代上述那些的其他態樣。該些態樣在熟習此技藝之人士在閱讀下列詳細描述並參照所附圖示之後將變得顯而易見。
下列實施例將以足夠的細節來描述，以使得熟習此技藝之人士能製作並使用本發明，要了解，其他實施例以本揭露為基礎將是明顯的，可在不背離本發明範圍下作系統、製程、或機械的改變。
於下列敘述中，係給定多個詳細說明以提供本發明之完整瞭解，然而，顯而易見的，該發明之實施可不需這些詳細細節。為避免模糊本發明，一些已知的電路、系統組構、及製程步驟未詳細地揭露。
同樣地，顯示該系統實施例的圖示係為半概略的輪廓(semi-diagrammatic)且未依比例，而特別地，一些尺寸為清楚呈現而誇大地顯示於圖示中。在多個實施例中揭露及描述某些共同特徵，為清楚及容易說明、描述及理解，彼此相似和相同特徵將一般以相同參考編號來描述。已經把該些實施例作編號以方便描述，且並沒有任何其他含意。
為了說明的原因，在此使用的用語「水平(horizontal)」係定義為平行該指狀引線的平面或底面，無論其定位。該用語「垂直(vertical)」係指垂直於剛定義的該水平之方向。例如「在…上面(above)」、「在…下面(below)」、「底部(bottom)」、「頂部(top)」、「側邊(side)」(如在「側壁(sidewall)」中)、「較高(higher)」、「較低(lower)」、「上面的(upper)」、「在…上方(over)」以及「在…之下(under)」的用語，係相對該水平平面而定義。
在此使用的用語「在…上(on)」係指在元件間有直接接觸，在此使用的用語「處理(processing)」係包含材料的設置、圖案化、曝光、顯影、蝕刻、清潔、及/或材料的移除或形成所述結構所需之修整，在此使用的用語「系統(system)」意指且視作依照使用該用語的上下文的本發明之方法及設備。
現在參閱第1圖，係為本發明之第一實施例中的積體電路封裝件系統100之剖視示意圖；該積體電路封裝件系統100包括至少一積體電路(IC)晶粒或晶片，例如半導體晶片102。
在該半導體晶片102之下是應力緩和層104及黏著層106。
已經得知藉由具有低彈性模數(modulus of elasticity)的該應力緩和層104與具有高彈性模數的該黏著層106，以可在固化過程中最小化或消除該半導體晶片102的翹曲。一般而言，「高彈性模數」層係定義為具有比「低彈性模數」層還高之彈性模數，其中，該高彈性模數層之模數大約為該低彈性模數層之模數的十倍。
於一實施態樣中，該應力緩和層104具有低模數，其範圍係小於100MPa，而該黏著層106則具有高模數，其範圍係大於1GPa。
該應力緩和層104及該黏著層106係可敷設為薄膜、帶體(tape)或塗佈層(coating)，且可部分或完全固化；該應力緩和層104及該黏著層106亦可具有黏著特性，並結合其他物質，以及能夠將該半導體晶片102結合至電性互連；該電性互連係例如為指狀引線108。
該半導體晶片102藉由接合線110以電性連接該指狀引線108，且該半導體晶片102包覆在包覆體(encapsulant)112中。
現在參閱第2圖，係為依據本發明之第一實施例之製造中間階段中之晶圓200之剖視示意圖；該晶圓200一般係由矽或其他半導體材料所組成，且具有製造於該材料上或中的積體電路(未圖示)。
現在參閱第3圖，係為第2圖之結構上形成該應力緩和層104後之示意圖；該晶圓200具有主動面300及背面(backside)302，且該應力緩和層104已經藉由例如滾動(rolling)或壓按(pressing)帶體或薄膜、旋轉塗佈(spin coat)、噴塗(spray)、或網印塗佈層的製程來使形成於該背面302上。
現在參閱第4圖，係為第3圖之結構在部分或完全固化該應力緩和層104之過程之示意圖；熱或光(如紫外線)源400施加熱或光402以部分或完全固化；要了解，一些應力緩和材料可不用施加熱或光地自行固化(self-curing)。
現在參閱第5圖，係為第4圖之結構上形成該黏著層106後之示意圖；該黏著層106可藉由滾動或壓按帶體或薄膜、與旋轉塗佈、噴塗、或網印塗佈層來形成。
現在參閱第6圖，係為第5圖之結構在部分或完全固化該黏著層106之過程之示意圖；熱或光源600施加熱或光602以部分或完全固化該黏著層106；要了解，一些黏著材料可不用施加該熱或光602地自行固化。
現在參閱第7圖，係為安裝第6圖之結構且切割該晶圓200並形成個別半導體晶片102後之示意圖；已經將具有該應力緩和層104及該黏著層106之晶圓200安裝於切割帶體(dicing tape)700上，且已經沿著線702將該結構切割，以形成該半導體晶片102。
現在參閱第8圖，係為該半導體晶片102於晶粒貼合(die-attach)後之示意圖；該半導體晶片102係於該應力緩和層104上，該應力緩和層104係於該黏著層106上；將該黏著層106晶粒貼合至該指狀引線108，以使該半導體晶片102位於該指狀引線108之間與上方；一般而言，該指狀引線108係仍為導線架(未圖示)之部分，而該導線架安裝於可選擇的(optional)導線架帶體(leadframe tape)800上。
現在參閱第9圖，係為第8圖之結構在完全固化該應力緩和層104及該黏著層106之過程之示意圖；熱或光源900施加熱或光902以完全固化；要了解，該加強固化製程是可選擇的且僅使用於先前步驟有使用部分固化之時。
現在參閱第10圖，係為第9圖之結構在該接合線110線結合於該半導體晶片102與該指狀引線108之間後之示意圖。
現在參閱第11圖，係為第10圖之結構經包覆(encapsulation)後之示意圖；該包覆體112包覆該半導體晶片102、該應力緩和層104、該黏著層106、該指狀引線108、及該接合線110。
應注意，該應力緩和層104及該黏著層106之固化完成可選擇地於該包覆製程後實現。
現在參閱第12圖，係為第11圖之結構在移除第11圖之該導線架帶體800並單一化成為該積體電路封裝件系統100後之示意圖。
現在參閱第13圖，係為本發明之第二實施例中積體電路封裝件系統1300之剖面示意圖；該積體電路封裝件系統1300包含於該指狀引線108上方之該半導體晶片102。
該半導體晶片102具有該應力緩和層104及該黏著層106的黏著層部份(adhesion layer portion)1302，且該黏著層部份1302鄰近該半導體晶片102之切割側(diced side)1306；該黏著層部份1302選擇性地形成於該應力緩和層104上且正好在該指狀引線108上方，這樣的方式是藉由提供最少的發生CTE不吻合的材料，以避免晶圓翹曲。
該半導體晶片102藉由結合線110以連接該指狀引線108且包覆在包覆體1304中。
現在參閱第14圖，係為本發明之第三實施例中積體電路封裝件系統1400之剖面示意圖；該積體電路封裝件系統1400包含該半導體晶片102及該應力緩和層104。
於應力緩和層104之下的是特別厚的黏著層1402，該黏著層1402係厚到足以形成於該指狀引線108之側面上方；該黏著層1402除了接合至該指狀引線108之頂面外，亦結合至該指狀引線108之側面以有效覆蓋該指狀引線108，這對該指狀引線108提供了引線固定(lead-locking)的功能，且消除線接合製程中的回彈(bounce)指狀引線108的問題。
該半導體晶片102藉由接合線110以線接合至該指狀引線108且該結構包覆在包覆體1404中。
現在參閱第15圖，係為本發明之第四實施例中積體電路封裝件系統1500之剖面示意圖；該積體電路封裝件系統1500包含該半導體晶片102、該應力緩和層104、及該黏著層106。
於該黏著層106之下的是額外的應力緩和層1502，該額外的應力緩和層1502有助於進一步消除晶圓翹曲。
該半導體晶片102藉由接合線110以線接合至該指狀引線108且該結構包覆在包覆體1504中。
現在參閱第16圖，係為用以製造該積體電路封裝件系統的積體電路封裝方法1600之流程圖。該積體電路封裝方法1600係包含：方塊1602中，提供具有主動面及背面之積體電路晶圓；方塊1604中，於該背面上形成應力緩和層；方塊1606中，於該應力緩和層上形成黏著層；方塊1608中，將該積體電路晶圓切割成半導體晶片，且該半導體晶片之背面上具有該應力緩和層及該黏著層；以及方塊1610中，將該半導體晶片安裝於指狀引線上方。
因此，已經得知本發明之積體電路封裝件系統方法與設備提供重要、先前未知且無法得到之解決方案、能力、及功能態樣；該導致的步驟與組構是明確的、有成本效益的、不複雜的、非常多功能的、精確的、靈敏度高的、與有效的、且可藉由改造已知組件來實現，以迅速的、有效的、與經濟的製造、應用、與利用。
因本發明係以結合特定的最佳模式來描述，要了解的是，眾多替代的、修改的及各種變化將因前述說明而為熟悉此項技藝的人士了解所明瞭，據此，其係傾向包含在本申請專利範圍內的所有這類替代的、修改的及各種變化，在此提出的所有事項或顯示於附圖中的係為範例之說明而非用於限制。
100、1300、1400、1500．．．積體電路封裝件系統
102．．．半導體晶片
104．．．應力緩和層
106、1402．．．黏著層
108．．．指狀引線
110．．．接合線
112、1304、1404、1504．．．包覆體
200．．．晶圓
300．．．主動面
302．．．背面
400、600、900．．．熱或光源
402、602、902‧‧‧熱或光
700‧‧‧切割帶體
702‧‧‧線
800‧‧‧導線架帶體
1302‧‧‧黏著層部份
1306‧‧‧切割側
1502‧‧‧額外的應力緩和層
1600‧‧‧積體電路封裝方法
1602、1604、1606、1608、1610‧‧‧方塊
第1圖係為本發明之第一實施例中的積體電路封裝件系統之剖面示意圖；
第2圖係為依據本發明之第一實施例之製造中間階段中之晶圓之剖面示意圖；
第3圖係為第2圖之結構上形成該應力緩和層後之示意圖；
第4圖係為第3圖之結構在部分或完全固化該應力緩和層之過程之示意圖；
第5圖係為第4圖之結構上形成該黏著層後之示意圖；
第6圖係為第5圖之結構在部分或完全固化該黏著層之過程之示意圖；
第7圖係為安裝第6圖之結構且切割該晶圓並形成個別半導體晶片後之示意圖；
第8圖係為該半導體晶片於晶粒貼合後之示意圖；
第9圖係為第8圖之結構在完全固化該應力緩和層及該黏著層之過程之示意圖；
第10圖係為第9圖之結構在該接合線線結合於該半導體晶片與該指狀引線之間後之示意圖；
第11圖係為第10圖之結構經包覆後之示意圖；
第12圖係為第11圖之結構在移除該導線架帶體並單一化成為該積體電路封裝件系統後之示意圖；
第13圖係為本發明之第二實施例中積體電路封裝件系統之剖面示意圖；
第14圖係為本發明之第三實施例中積體電路封裝件系統之剖面示意圖；
第15圖係為本發明之第四實施例中積體電路封裝件系統之剖面示意圖；以及
第16圖係為用以製造該積體電路封裝件系統的積體電路封裝方法之流程圖。
100．．．積體電路封裝件系統
102．．．半導體晶片
104．．．應力緩和層
106．．．黏著層
108．．．指狀引線
110．．．接合線
112．．．包覆體

Claims (9)

  1. 一種積體電路封裝件系統，係包括：半導體晶片；應力緩和層，係位於該半導體晶片上；黏著層，係位於該應力緩和層上；以及電性互連，係接合至該黏著層；其中，該黏著層之厚度大於該應力緩和層之厚度；以及該黏著層係位於該電性互連上及其側面上方。
  2. 如申請專利範圍第1項所述之系統，其中：該黏著層係位於鄰近該半導體晶片之切割側面的該應力緩和層之選擇區域上；以及該半導體晶片藉由該黏著層而安裝於該電性互連上。
  3. 如申請專利範圍第1項所述之系統，復包括：額外的應力緩和層，係位於該黏著層上，且該額外的應力緩和層使該半導體晶片保持於該電性互連上。
  4. 如申請專利範圍第1項所述之系統，復包括：接合線，該接合線將該半導體晶片電性連接至該電性互連；以及包覆體，該包覆體包覆該半導體晶片、該接合線及該電性互連。
  5. 如申請專利範圍第1項所述之系統，其中： 該應力緩和層係低模數應力緩和層；該黏著層係高模數黏著層；該低模數應力緩和層與該高模數黏著層係完全固化；以及該電性互連係指狀引線。
  6. 如申請專利範圍第5項所述之系統，其中：該高模數黏著層係位於鄰近該半導體晶片之切割側面的該低模數應力緩和層之選擇區域上；以及該半導體晶片藉由該高模數黏著層而安裝於該指狀引線上。
  7. 如申請專利範圍第5項所述之系統，其中：該高模數黏著層之厚度大於該低模數應力緩和層之厚度；以及該高模數黏著層係位於該指狀引線上及其側面上方。
  8. 如申請專利範圍第5項所述之系統，復包括：額外的低模數應力緩和層，係位於該高模數黏著層上，且該額外的低模數應力緩和層使該半導體晶片保持於該指狀引線上。
  9. 如申請專利範圍第5項所述之系統，復包括：接合線，該接合線將該半導體晶片電性連接至該指狀引線；以及包覆體，該包覆體包覆該半導體晶片、該接合線及該指狀引線。
TW101111657A 2007-09-20 2008-09-12 具有無彎曲晶片之積體電路封裝件系統 TWI493632B (zh)

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