TWI506707B - 具有導線架插入件的積體電路封裝系統及其製造方法 - Google Patents

具有導線架插入件的積體電路封裝系統及其製造方法 Download PDF

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Publication number
TWI506707B
TWI506707B TW097147769A TW97147769A TWI506707B TW I506707 B TWI506707 B TW I506707B TW 097147769 A TW097147769 A TW 097147769A TW 97147769 A TW97147769 A TW 97147769A TW I506707 B TWI506707 B TW I506707B
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Taiwan
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integrated circuit
substrate
spacer
package
ball
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TW097147769A
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English (en)
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TW200939363A (en
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Dongsam Park
Youngsik Cho
Sang-Ho Lee
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Stats Chippac Ltd
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Description

具有導線架插入件的積體電路封裝系統及其製造方法 [相關申請案之交叉參考]
本申請案係主張於2007年12月17日所提出申請之美國專利臨時申請案，序號61/014,438的利益，於此併入該專利申請案之內容，以供參考。
本發明大致上係關於積體電路封裝系統，且尤係關於用以形成具有插入件的三維堆疊封裝件的系統。
積體電路被使用於許多可攜式電子產品(如行動電話、可攜式電腦、錄音機等)。積體電路也被使用於許多較大型的電子系統，如汽車、飛機、工業控制系統等等。幾乎對於所有的應用而言，對於裝置的尺寸縮減與效能的增進之需求仍持續增加。如今對於可攜式電子產品的強烈需求係正處於高峰，可攜式電子產品已變得相當普遍且經常進行尺寸上的縮減。
為了增加電路密度並加強功能性，晶圓製造努力將電晶體或電容器的特徵尺寸縮減。具有次微米線寬的裝置係相當普遍，使得個別晶片中通常含有數百萬個電子裝置。縮減特徵尺寸在改善電子系統上已經相當成功，且未來的持續發展係可預期的。然而，特徵尺寸的進一步縮減正遭遇顯著的阻礙。此等阻礙包含缺陷(defect)密度的控制、光學系統解析度的限制以及處理材料與配備的取得。因此，注意力遂漸漸轉移至利用半導體封裝而達到對於系統 效能加強與更小的元件尺寸的不間斷之要求。
用以支援新的應用程式所需的某些功能係以不同的製程技術為基礎。例如，高容量記憶體係以不同於高速處理器的製程技術所製造。此種情形使得以上兩者無法於相同的矽晶圓上製造，但是不同的製程技術可被封裝在一起以實現具有高度空間效率的元件。
傳統設計的缺點包含母板的接置表面上相對較大的封裝件覆蓋面積(footprint)。該覆蓋面積通常係該封裝件的最大尺寸，即x-y尺寸。在接置空間有限的應用(如呼叫器、可攜式電話以及個人電腦…等)中，並不期望有較大的覆蓋面積。為了增加封裝件內的電路系統數目而不增加該封裝件的面積以使得該封裝件不必佔用電路板上更多的空間，製造者將兩個或更多個晶粒堆疊於單一封裝件內。不幸的是，電性互連的充分重疊(overlap)與較大的覆蓋面積頂部封裝件困擾著先前的堆疊封裝件技術或層疊封裝(package on package)設計。
因此，對於具有能夠支援高輸入/輸出數裝置以及高品質堆疊封裝件設計的插入件之積體電路封裝系統的需求持續存在著。有鑑於對於在較小空間中具有更多功能的需求不斷增加，找出這些問題的解答越形重要。有鑑於日益激烈的商業競爭壓力，伴隨日益增長的消費者預期以及市場定位上有意義的產品區隔機會日益縮小，找出這些問題的解答係相當關鍵且重要。此外，對於降低成本、改善效率與效能、以及面對競爭壓力使得找出這些問題的解答的需 求益形迫切。
如何克服上述該些問題已為人們所長期探討，但先前的發展並未教示或建議任何解決方案，所以，在所屬技術領域中具有通常知識者已長期盼望有解決該些問題的方法。
本發明提供一種積體電路封裝系統的製造方法，包含：形成基板；將基底積體電路接置於該基板上；在該基底積體電路之上形成導線架插入件；將積體電路封裝件耦接於球墊片上；以及在該基板、該基底積體電路與該導線架插入件上形成元件封裝件，其中在該基底積體電路之上形成導線架插入件，係藉由：提供金屬薄片、將積體電路晶粒接置於該金屬薄片上、在該積體電路晶粒與該金屬薄片上注入模製封裝件本體、以及從未受到該模製封裝件本體所保護的金屬薄片形成該球墊片、接合指或者兩者的組合。
本發明提供一種積體電路封裝系統，包含：基板；接置於該基板上的基底積體電路；位在該基底積體電路之上的導線架插入件，包含：球墊片、接合指或兩者的組合、接置於該等球墊片之上的積體電路晶粒、以及位在該積體電路晶粒、該等球墊片和該等接合指上的模製封裝件本體；耦接於該球墊片上的積體電路封裝件；以及位在該基板、該基底積體電路與該導線架插入件上的元件封裝件。
本發明之某些實施例具有其他步驟或元件用以增加或 替代以上所述者。藉由閱讀下列所述並參考附圖，技術領域中具有通常知識者將清楚明瞭該等步驟或元件。
以下實施例係充分詳細描述以使熟悉本領域之技藝人士可製造及使用本發明，咸了解基於此揭露內容可明瞭其他實施例，而且，其系統、製程或機構上的變化可在不悖離本發明之範疇下進行。
以下說明將給定許多明確的細節，以提供對本發明完整的了解。然而，顯然本發明得於無該些明確細節下施行。為了避免模糊本發明，一些習知的電路、系統組構與製程步驟將不再詳細敘述。
用來例示本發明實施例的附圖為部分圖示而非按比例繪製，特別是某些圖中的尺寸，是為使說明書清晰而特別放大。類似地，雖然該等圖式一般為了方便說明均係顯示類似的定向，但此等圖式的描述對於大部份而言均係任意的。一般而言，本發明可操作於任何定向(orientation)。
揭露及描述在多個實施例中的某些共同特徵，為清楚及容易說明、描述及理解，通常相似及相同的特徵將以相同元件符號來敘述。為便於描述，實施例是以第一實施例、第二實施例等予以編號，並非用以呈現其他意義或用以限定本發明。
為說明起見，本發明說中所用“水平面(horizontal)”一詞，定義為與本發明積體電路平行的表面或平面，而無關於其定向。“垂直(vertical)”一詞，意指與前項所定 義的水平面垂直的方向。其他用語，諸如“上方(above)”、“下方(below)”、“底部(bottom)”、“頂部(top)”、“側(如“側壁”)”、“較高”、“較低”、“上面的(upper)”、“之上(over)”、以及“之下(under)”，是相對於該水平面而定義的。本說明書中所使用的“在…上(on)”一詞，是意指元件間有直接接觸。
本說明書中所使用的“處理(processing)”一詞，是形成所述構造時所需之步驟，包含：材料或光阻的沉積、圖案化、曝光、顯影、蝕刻、清理以及/或者是材料或光阻的移除。
參閱第1圖，顯示在本發明第一實施例中具有導線架插入件之積體電路封裝系統100沿著第3圖之剖面線1-1的剖面圖。該積體電路封裝系統100的剖面圖描述積體電路晶粒102藉由黏著劑104(如晶粒接附材料)而被接置於球墊片108的陣列106上。接合指(bond finger)110可圍繞在該陣列106的周圍。電性互連102(如接合線)可將該積體電路晶粒102耦接至該等接合指110。模製封裝件本體114可藉由將環氧模製化合物(epoxy molding compound)注入於該積體電路晶粒102、該黏著劑104、該等球墊片108、該等接合指110以及該等電性互連112上而形成。
已發現到，該積體電路封裝系統100可提供用以形成相較於傳統上具有較小垂直高度的三維堆疊積體電路封裝件的方法。此點對於降低終端應用(未圖示)的整體垂直高度係不可或缺的。
在該陣列106中的該等球墊片108的編號與位置僅為範例而實際的編號可能有所不同。該等接合指110的位置與編號也僅為舉例。可以有多於一列以上的接合指110圍繞在該陣列106的周圍。
參閱第2圖，顯示在本發明第一實施例中的導線架插入件基底200的上視圖。該導線架插入件基底200的上視圖描述已印有壓紋圖案的金屬薄片202(如銅薄片)可使得該等接合指110圍繞在該金屬薄片202的周圍。該等球墊片108可被圖案化於該金屬薄片202的中央區域。該壓紋製程可為沖壓(stamping)製程、蝕刻製程或兩者的組合。
信號路徑204可將該等球墊片108耦接至該等接合指110。在藉由該信號路徑204耦接的該等球墊片108與該等接合指110之間可為一對一的對應關係。該金屬薄片202的中央區域內可形成絕緣屏蔽(isolation shield)206。該絕緣屏蔽206可藉由短路環(shorting bridge)208，例如較該信號路徑204寬的信號路徑，而被耦接至一個以上的接合指110。
該絕緣屏蔽206可用以控制用於高速信號收發的信號路徑204的阻抗。當第1圖中該積體電路晶粒102正在運作時，該絕緣屏蔽206所具有的額外好處係可作為散熱器(heat spreader)。該絕緣屏蔽206也可用以降低該等信號路徑204之間的電磁干擾(electro magnetic interference)。
該等球墊片108、該等接合指110以及該等信號路徑204的圖案僅為舉例而在實際實現時可能有所不同。該絕 緣屏蔽206的形狀以及甚至於該絕緣屏蔽206的存在均僅為舉例而實際情形可能有所不同。
參閱第3圖，顯示在本發明第一實施例中的積體電路封裝系統100的上視圖。該積體電路封裝系統100的上視圖描述該模製封裝件本體114將該等接合指110以及該等信號路徑204予以包裝(encase)。該黏著劑104可防止該等球墊片108與該絕緣屏蔽206被該模製封裝件本體114所包裝。以上情況僅為舉例，而該模製封裝件本體114可能將該等信號路徑204、該黏著劑104或者該絕緣屏蔽206予以包裝。該等信號路徑204可被半蝕刻(half etch)，以致該模製封裝件本體114故意將該等信號路徑204覆蓋。該等球墊片108與該等接合指110將保持曝露以用於進一步的電性連接。
該剖面線1-1顯示出第1圖以及接下來各個圖式的位置與方向。該等球墊片108和該等接合指110的編號與位置僅為舉例，而實際的編號與位置可能有所變化。未連接於該信號路徑204的測試墊片302可形成於該積體電路封裝系統100的周圍且配置在該等接合指110之間。該測試墊片302可耦接至第1圖的該積體電路晶粒102而可用於其他內部連接(internal connection)。
參閱第4圖，顯示具有增加的互連數目之導線架插入件400的上視圖。該導線架插入件400的上視圖描述該模製封裝件本體114將除了該等接合指110以及該等球墊片108以外的所有元件予以包裝。雖然圖中顯示該等接合指 110係以單一列環繞該導線架插入件400的周圍，但此僅為舉例且可能具有其他組構。該等球墊片108的陣列106可置放成如圖所示的交錯陣列或者是如第3圖所述的並排陣列。該等球墊片108的圖案可為任何可能的圖案。
參閱第5圖，顯示該積體電路封裝系統的第一應用500大致上類似於第3圖之剖面線1-1的剖面圖。該第一應用500的剖面圖描述基底積體電路502(如導線接合(wire bond)類型的積體電路或者覆晶積體電路)藉由該黏著劑104而被接置於基板504上。該基板504可具有元件側506以及系統側508。該基底積體電路502可藉由該等電性互連112耦接至該元件側506。積體電路間隔件510可被置放於該基底積體電路502與該等電性互連112上。
該積體電路封裝系統100可利用朝向該基底積體電路502置放的模製封裝件本體114而被接置於該積體電路間隔件510上。該等接合指110可藉由該等電性互連112而被耦接至該元件側506。元件封裝件512可形成於該元件側506、該基底積體電路502、該等電性互連112、該積體電路間隔間510以及該等接合指110上。該等球墊片108可保持曝露以接著連接至電路封裝件513(如積體電路封裝件、離散元件或是以上兩者的組合)。
該元件側506可經由接觸通孔(contact via)514而耦接至該系統側508。系統互連516(如銲錫球(solder ball)、銲錫凸塊(solder bump)、銲錫柱(solder column)或焊接凸塊(stud bump))可被耦接至該系統側508上的該等接點 通孔514。該等系統互連516、該基底積體電路502、該積體電路晶粒102、該等球墊片108或是上述各者的組合之間可形成電性連接。
參閱第6圖，顯示該積體電路封裝系統的第二應用600大致上類似於第3圖之剖面線1-1的剖面圖。該第二應用600的剖面圖描述該基底積體電路502(導線接合類型的積體電路或者覆晶積體電路)藉由該黏著劑104而被接置於該基板504上。該基板504可具有元件側506以及系統側508。該基底積體電路502可藉由該等電性互連112耦接至該元件側506。該積體電路間隔件510可被置放於該基底積體電路502與該等電性互連112上。
該積體電路封裝系統100可利用朝向該基底積體電路502置放的模製封裝件本體114而被接置於該積體電路間隔件510上。該等接合指110可藉由該等電性互連112而耦接至該元件側506。封裝件本體602可形成於該元件側506、該基底積體電路502、該等電性互連112、該積體電路間隔件510、該等接合指110以及內部元件604(如積體電路封裝件、離散元件或兩者的組合)上。該內部元件604可藉由晶片互連606(如銲錫球、銲錫凸塊、銲錫柱或焊接凸塊)而接置於該等球墊片108上。
該元件側506可藉由該等接觸通孔514被耦接至該系統側508。該等系統互連516(如銲錫球、銲錫凸塊、銲錫柱或焊接凸塊)可被耦接至該系統側508上的該等接觸通孔514。該等系統互連516、該基底積體電路502、該積體 電路晶粒102、該等內部元件604或者上述各者的組合之間可形成電性連接。
參閱第7圖，顯示在導線架製造準備階段中的導線架插入件基底700大致上類似於第3圖之剖面線1-1的剖面圖。該導線架插入件基底700的剖面圖描述具有該等球墊片108的陣列106與該等接合指110的壓紋圖案之金屬薄片。該壓紋圖案可藉由壓擠(pressing)、蝕刻、雷射修整(laser trimming)或是上述各者的組合而形成於該金屬薄片上。
該導線架插入件基底700可具有其他形成於該金屬薄片202表面上之結構。如第2圖的該絕緣屏蔽206、第2圖的該等信號路徑204、第2圖的短路環208或者上述各者的組合均可作為上述之結構。本圖中所示之結構僅為簡化之範例。
參閱第8圖，顯示第一導線架插入件配件800大致上類似於第3圖之剖面線1-1的剖面圖。該第一導線架插入件組合800之剖面圖描述該積體電路晶粒102藉由該黏著劑104被接置於該導線架插入件基底700的該等球墊108上。該等電性互連112可將該積體電路晶粒102與該等接合指110耦接。
參閱第9圖，顯示第二導線架插入件組合900大致上類似於第3圖之剖面線1-1的剖面圖。該第二導線架插入件組合900之剖面圖描述該模製封裝件本體114形成於該積體電路晶粒102、該黏著劑104、該等球墊片108、該等 接合指110以及該等電性互連112上。
一旦該模製封裝件本體114就定位，該第二導線架插入件組合900可進行蝕刻製程將過剩的材料自該金屬薄片202移除。在蝕刻製程之後所保留下來的結構係第1圖之該積體電路封裝系統100。
參閱第10圖，顯示本發明進一步實施例中的積體電路封裝系統的製造方法1000之流程圖。該方法1000包含：於步驟1002形成基板；於步驟1004將基底積體電路接置於該基板上；於步驟1006藉由：提供金屬薄片、將積體電路晶粒接置於該金屬薄片上、在該積體電路晶粒與該金屬薄片上注入模製封裝件本體、以及從未受到該模製封裝件本體所保護的金屬薄片形成球墊片、接合指或是兩者的組合，從而在該基底積體電路之上形成導線架插入件；於步驟1008將積體電路封裝件耦接於該球墊片上；以及，於步驟1010在該基板、該基底積體電路與該導線架插入件上形成元件封裝件。
本發明所產生的方法、製程、設備、裝置、產品及/或系統係直接、具成本效益、簡單不複雜、具高度彈性與效率，可輕易地適用於有效率且具經濟效益的積體電路封裝系統製造，並且完全相容於傳統的製造方法或製程技術。本發明的另一重要態樣係本發明強力地支持並促進降低成本、簡化系統以及增進效能的歷史趨勢。
本發明的這些以及其他態樣因而將技術狀態提升到至少下一個層次。
雖然已結合特定的最佳模式來描述本發明，但應了解到，有鑑於前述敘述，對許多熟習該技術領域者而言，許多的替代、修飾和變化將變得顯而易見。因此，係意欲涵蓋落入所附之申請專利範圍之範疇內的所有此等替代、修飾和變化。本說明書所揭示的所有內容或顯示的附圖係用於解釋本發明，而非用於限制本發明之範疇。
100‧‧‧具有導線架插入件之積體電路封裝系統
102‧‧‧積體電路晶粒
104‧‧‧黏著劑
106‧‧‧陣列
108‧‧‧球墊片
110‧‧‧接合指
112‧‧‧電性互連
114‧‧‧模製封裝件本體
200‧‧‧導線架插入件基底
202‧‧‧金屬薄片
204‧‧‧信號路徑
206‧‧‧絕緣屏蔽
208‧‧‧短路環
302‧‧‧測試墊片
400‧‧‧導線架插入件
500‧‧‧第一應用
502‧‧‧基底積體電路
504‧‧‧基板
506‧‧‧元件側
508‧‧‧系統側
510‧‧‧積體電路間隔件
512‧‧‧元件封裝件
513‧‧‧電路封裝件
514‧‧‧接觸通孔
516‧‧‧系統互連
600‧‧‧第二應用
602‧‧‧封裝件本體
604‧‧‧內部元件
606‧‧‧晶片互連
700‧‧‧導線架插入件基底
800‧‧‧第一導線架插入件組合
900‧‧‧第二導線架插入件組合
1000‧‧‧方法
1002、1004、1006、1008、1010‧‧‧步驟
第1圖係本發明第一實施例中具有導線架插入件之積體電路封裝系統沿著第3圖之剖面線1-1的剖面圖；第2圖係本發明第一實施例的導線架插入件基底的上視圖；第3圖係本發明第一實施例的積體電路封裝系統的上視圖；第4圖係具有增加的互連數目之導線架插入件的上視圖；第5圖係該積體電路封裝系統的第一應用大致上類似於第3圖之剖面線1-1的剖面圖；第6圖係該積體電路封裝系統的第二應用大致上類似於第3圖之剖面線1-1的剖面圖；第7圖係在導線架製造準備階段的導線架插入件基底大致上類似於第3圖之剖面線1-1的剖面圖；第8圖係第一導線架插入件組合大致上類似於第3圖之剖面線1-1的剖面圖；第9圖係第二導線架插入件組合大致上類似於第3 圖之剖面線1-1的剖面圖；以及第10圖係本發明進一步實施例的積體電路封裝系統的製造方法之流程圖。
1000‧‧‧可接置之積體電路封裝方法
1002、1004、1006、1008、1010‧‧‧步驟

Claims (20)

  1. 一種積體電路封裝系統的製造方法，包括：形成基板；將基底積體電路接置於該基板上；在該基底積體電路之上形成導線架插入件，係藉由：提供金屬薄片，將積體電路晶粒接置於該金屬薄片上，在該積體電路晶粒與該金屬薄片上注入模製封裝件本體，以及從未受到該模製封裝件本體所保護的該金屬薄片形成球墊片、接合指和測試墊片，該測試墊片配置在一些接合指之間；將電路封裝件耦接於該球墊片上；以及在該基板、該基底積體電路與該導線架插入件上形成元件封裝件。
  2. 如申請專利範圍第1項所述之方法，其中，形成該球墊片和該接合指包含在該球墊片與該接合指之間形成信號路徑。
  3. 如申請專利範圍第1項所述之方法，復包括在該基底積體電路與該導線架插入件的該模製封裝件本體之間接置積體電路間隔件。
  4. 如申請專利範圍第1項所述之方法，復包括在該基底積體電路、該接合指、該基板或是上述各者的組合之間耦 接電性互連。
  5. 如申請專利範圍第1項所述之方法，復包括在該球墊片與該接合指之間形成絕緣屏蔽。
  6. 一種積體電路封裝系統的製造方法，包括：形成基板，包含在該基板中形成接觸通孔；將基底積體電路接置於該基板上，包含在該基底積體電路和該基板之間施加黏著劑；在該基底積體電路之上形成導線架插入件，係藉由：壓紋金屬薄片，包含藉由壓擠、蝕刻、雷射修整或其組合形成陣列，將積體電路晶粒接置於該金屬薄片上，包含耦接測試墊片至該積體電路晶粒，在該積體電路晶粒與該金屬薄片上注入模製封裝件本體，包含注入環氧模製化合物，以及從未受到該模製封裝件本體所保護的該金屬薄片蝕刻球墊片、接合指和測試墊片，包含在該球墊片和該接合指之間形成一對一連接，該測試墊片配置在一些接合指之間；將電路封裝件耦接於該球墊片上包含耦接積體電路、離散元件或其組合；以及在該基板、該基底積體電路與該導線架插入件上形成元件封裝件。
  7. 如申請專利範圍第6項所述之方法，其中，蝕刻該球墊片和該接合指包含在該球墊片與該接合指之間蝕刻信 號路徑，包含藉由在該信號路徑附近放入絕緣屏蔽以控制阻抗。
  8. 如申請專利範圍第6項所述之方法，復包括在該基底積體電路和該導線架插入件的該模製封裝件本體之間接置積體電路間隔件，包含在該積體電路間隔件中提供電性互連。
  9. 如申請專利範圍第6項所述之方法，復包括在該基底積體電路、該接合指、該基板或其組合之間耦接電性互連，包含在該基底積體電路、該積體電路晶粒、該電路封裝件或其組合之間偶接信號。
  10. 如申請專利範圍第6項所述之方法，復包括在該球墊片與該接合指之間壓紋絕緣屏蔽，包含在該絕緣屏蔽和該測試墊片之間耦接短路環。
  11. 一種積體電路封裝系統，包括：基板；基底積體電路，係接置於該基板上；導線架插入件，係於該基底積體電路之上，包含：球墊片、接合指和測試墊片，該測試墊片配置在一些接合指之間，積體電路晶粒，係接置於該球墊片之上，以及模製封裝件本體，係於該積體電路晶粒、該球墊片和該接合指上；電路封裝件，係耦接於該球墊片上；以及元件封裝件，係於該基板、該基底積體電路與該導 線架插入件上。
  12. 如申請專利範圍第11項所述之系統，其中，該球墊片和該接合指包含介於該球墊片與該接合指之間的信號路徑。
  13. 如申請專利範圍第11項所述之系統，復包括介於該基底積體電路與該導線架插入件的該模製封裝件本體之間的積體電路間隔件。
  14. 如申請專利範圍第11項所述之系統，復包括介於該基底積體電路、該接合指、該基板或是上述各者的組合之間的電性互連。
  15. 如申請專利範圍第11項所述之系統，復包括介於該球墊片與該接合指之間的絕緣屏蔽。
  16. 如申請專利範圍第11項所述之系統，復包括：接觸通孔，係於該基板中；黏著劑，係介於該基底積體電路和該基板之間；以及其中：該測試墊片係耦接至該積體電路晶粒。
  17. 如申請專利範圍第16項所述之系統，其中，該球墊片和該接合指包含介於該球墊片與該接合指之間的信號路徑，且具有在該信號路徑附近的絕緣屏蔽。
  18. 如申請專利範圍第16項所述之系統，復包括介於該基底積體電路和該導線架插入件的該模製封裝件本體之間的積體電路間隔件，包含在該積體電路間隔件中的電 性互連。
  19. 如申請專利範圍第16項所述之系統，復包括介於該基底積體電路、該接合指、該基板或其組合之間的電性互連，包含藉由系統互連偶接至該基底積體電路、該積體電路晶粒、該電路封裝件或其組合的信號。
  20. 如申請專利範圍第16項所述之系統，復包括介於該球墊片與該接合指之間的絕緣屏蔽，包含介於該絕緣屏蔽和該測試墊片之間的短路環。
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