TWI446460B - 用於封裝件堆疊之積體電路封裝件系統 - Google Patents

用於封裝件堆疊之積體電路封裝件系統 Download PDF

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Publication number
TWI446460B
TWI446460B TW097113453A TW97113453A TWI446460B TW I446460 B TWI446460 B TW I446460B TW 097113453 A TW097113453 A TW 097113453A TW 97113453 A TW97113453 A TW 97113453A TW I446460 B TWI446460 B TW I446460B
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Taiwan
Prior art keywords
integrated circuit
package
surface conductor
array substrate
area array
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TW097113453A
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English (en)
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TW200849417A (en
Inventor
Rajendra D Pendse
Flynn Carson
Il Kwon Shim
Seng Guan Chow
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Stats Chippac Ltd
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Publication of TW200849417A publication Critical patent/TW200849417A/zh
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Publication of TWI446460B publication Critical patent/TWI446460B/zh

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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
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    • H01L23/49805—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers the leads being also applied on the sidewalls or the bottom of the substrate, e.g. leadless packages for surface mounting
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Description

用於封裝件堆疊之積體電路封裝件系統 [優先權之主張]
本申請案主張於2007年4月23日所提出申請之美國臨時專利申請案第60/913,526號之優先權，於此併八該專利申請案之主題標的，以供參考。
本申請案含有關於共同申請(co－pending)之美國專利申請案第11/354,806號之主題標的。該相關申請案係讓渡予STATS ChipPAC有限公司。
本申請案也含有關於共同申請之美國專利申請案第11/307,615號之主題標的。該相關申請案係讓渡予STATS ChipPAC有限公司。
本發明大致上係關於半導體封裝方式，且尤係關於一種用於堆疊區域陣列積體電路封裝件之積體電路封裝系統。
電子工業界持續尋找更輕、更快、更小、多功能、更可靠及更節省成本的產品。為了努力滿足這種需求，已發展出用於多晶片封裝件(multi－chip package,MCP)與晶片堆疊封裝件之封裝件組裝技術。這些型態之封裝件係於單一封裝件中結合兩個或更多個半導體晶片，從而實現增加記憶體密度、多功能性與/或減少封裝件面積(footprint)。
然而，在單一封裝件中使用數個晶片會有同時減少可靠度與良率(yield)的傾向。如果於後組裝測試(post assembly testing)期間，在多晶片或晶片堆疊封裝件中只有一顆晶片無法滿足功能與效能規格，則整個封裝件會失敗，導致良好的晶片會隨同該失敗的晶片一同被丟棄。因此，多晶片或晶片堆疊封裝件會降低組裝程序的生產力。
一種三維的封裝件堆疊方式藉由堆疊數個已組裝之封裝件(每一個均含有單一晶片且已通過必要的測試)來滿足良率的問題，從而改善最後合成封裝件的良率及可靠度。然而，封裝件堆疊傾向於使用引線框架(lead frame)形態的封裝件而不是區域陣列形態的封裝件。引線框架形態的封裝件一般係利用邊緣位置(edge－located)端點例如外部引線，而區域陣列形態的封裝件一般係利用表面分布(surface－distributed)端點例如焊珠(solder ball)。當與對應之引線框架形態的封裝件比較時，區域陣列形態的封裝件可因此提供較大的端點數與/或較小的面積。
因此，對於使用封裝件堆疊之積體電路封裝件系統仍然有需求。考慮到消費者電子產品發展速率與對於低生產成本之多功能裝置永不滿足的需求，發現這些問題的解決辦法是越來越迫切。考慮到持續增加(ever－increasing)的商業競爭壓力，以及漸增的消費者期待與在市場上對於有意義產品產生區隔的機會變小，發現這些問題的解決辦法是必要的。此外，對於節省成本、改善功效與性能以及面對競爭壓力的需求，對於尋求這些問題的解答之迫切必要增加更大的急迫性。
這些問題之解決辦法長期以來一直被尋求，但先前發 展尚未教示或建議任何解決方案，因此這些問題之解決辦法已長期困惑在此技術領域具有通常知識者。
本發明提供一種積體電路封裝方法，包含：形成區域陣列基板；在該區域陣列基板上安裝表面導體；在該區域陣列基板上與該表面導體上形成壓模封裝件本體；在該壓模封裝件本體上提供臺階；以及藉由該臺階暴露該表面導體。
本發明的某些實施例除了上述範例以外或代替上述範例外還具有其他態樣。當透過參考附加圖示來研讀以下詳細的說明，這些態樣對於技術領域具有通常知識之人將會變得明顯。
以下實施例係充分詳細描述以使熟悉本領域之技藝人士可製造及使用本發明，其他實施例依此揭露可明瞭而理解，而且其系統、製程或機構上的改變並未悖離本發明之範疇。
於下列敘述中，係給定多個詳細說明以提供本發明之完整瞭解，然而，該發明之實施為顯而易見的則未有這些詳細細節。為避免模糊本發明，一些已知的電路、系統結構及製程步驟未詳細地揭露。同樣地，本發明實施例該些圖的顯示係為概略的且未有比例，且特別地，一些尺寸為清楚呈現本發明係誇大地顯示於圖示中。另外，在多個實施例中揭露及描述某些共同特徵，為清楚及容易說明、描 述及理解，彼此相似及相同特徵將一般以相同參考編號來描述。
為說明的原因，在此使用的“水平(horizontal)”係定義為平行該積體電路的平面或表面，無論其定位；該“垂直(vertical)”名稱係指垂直所定義的“水平”之方向，稱“在...上面(above)”、“在...下面(below)”、“底部(bottom)”、“上方(top)”、“側邊”(如在“側壁”)、“較高(higher)”、“較低(lower)”、“上面的(upper)”、“覆於...上(over)”以及“在...之下(under)”，係相對該水平平面而定義，稱“在...上(on)”係指在元件間有直接接觸，在此稱“系統(system)”意指且係指依照上下文其係使用的本發明之方法及裝置。在此稱”處理(processing)”包括衝壓(stamping)、鍛造(forging)、圖案化、曝光、顯影、蝕刻、清洗、與/或如需要於形成所述結構之材料或雷射修整之移除。
參考第1圖，顯示本發明之實施例中用於封裝件堆疊之積體電路封裝件系統100之截面圖。該積體電路封裝件系統100之截面圖繪示具有組件側邊104與系統側邊106之區域陣列基板102。該區域陣列基板102可為薄板玻璃環氧樹脂(laminate glass epoxy resin)、軟性磁帶(flexible tape)、陶瓷、無機材料、低介質材料、半導體材料、或類似物。第一黏著劑108可在該組件側邊104上。第一積體電路110可被放置於第一黏著劑108上且藉由電子互連線(electrical interconnect)114電性連接至接觸焊點112。
實質上類似於第一黏著劑108的第二黏著劑116可被放置於第一積體電路110之主動側邊上。第二積體電路118可被安裝於該第二黏著劑116上。該電子互連線114可將該第二積體電路118電性耦合至該接觸焊點112。
表面導體120(例如焊珠、焊柱(solder column)、焊凸(solder bump)或螺栓凸塊(stud bump))可被安裝於該接觸焊點112上。該表面導體120可由錫、鉛、金、銅、金屬合金或其他導電材料製成。該表面導體120可藉由壓印(coining)或塑模前的加壓而被壓平。
具有核心部位123的壓模封裝件本體122可被形成於該區域陣列基板102之組件側邊104、該第一積體電路110、該接觸焊點112、該電子互連線114、該第二積體電路118、以及該表面導體120上。該壓模封裝件本體122可由環氧塑模化合物形成，並具有提供該表面導體120之暴露部分的入口(access)之臺階124(例如與該區域陣列基板102共平面且環繞該核心部位123的區域)。該表面導體120之上層部分可藉由薄膜促進塑模程序(film assisted molding process)保持塑模化合物的清潔，藉此，薄膜被施加於該表面導體120之仍保持暴露的部分。該薄膜於該壓模封裝件本體122形成後可被移除。其他材料或程序可被用於保持該表面導體120之暴露部分的清潔，例如插入於模具中的高溫有機材料。
該核心部位123可突出於該臺階124之上且包圍該第一積體電路110、該第二積體電路118、與該電子互連線 114。該核心部位123的尺寸可被調整以容納具有較高線圈迴路(用於多列焊墊之晶粒)之電子互連線114。
形成於該區域陣列基板102之系統側邊106上之系統接觸點126可透過通孔(via)128連接於該接觸焊點112。該接觸焊點112、該通孔128與系統接觸點126的結合可提供通過該區域陣列基板102之電子路徑。系統互連體130，例如焊珠、焊柱、焊凸、或螺栓凸塊，可提供至下一級的系統(無顯示)的電性連接。第1圖繪示所有接觸焊點112直接地耦合於該系統接觸點126，但此僅為一種範例的方式。於實際實施時，會在該第一積體電路110、該第二積體電路118、該接觸焊點112、該表面導體120、該系統互連體130、或上述結合體之間形成電性連接。
經發現，該臺階124可提供本發明有用的態樣。該壓模封裝件本體122比起目前的設計可使用較少的環氧塑模合成物。當提供堆疊式封裝(package－on－package)平台時也可容納堆疊更多的積體電路以減少最後產品之全部封裝件高度。該壓模封裝件本體122之突出部分在可於回焊(reflow)期間作為用於上層封裝件之支座(stand－off)，該支座可避免上層封裝件遭到過度崩解(over－collapsing)之。在臺階124之區域中有該壓模封裝件本體122的存在可增加具有該表面導體120之區域陣列基板102的剛性(rigidity)以及在製作或組裝程序期間協助避免該區域陣列基板102的翹曲(warping)。
參考第2圖，顯示使用第1圖用於封裝件堆疊之積體 電路封裝件系統100之積體電路堆疊200之截面圖。該積體電路堆疊200之截面圖繪示具有藉由晶片互連體204耦合該表面導體120之區域陣列裝置202(例如覆晶積體電路)之積體電路封裝件系統100。該晶片互連體204可為焊珠、焊柱、焊凸、或螺栓凸塊，用以將該區域陣列裝置202電性連接至該積體電路封裝件系統100。該積體電路堆疊200之封裝件高度206可小於先前技術封裝件一臺階高度208。
經發現，該壓模封裝件本體122可於回焊程序期間支撐該區域陣列裝置202，因此避免該晶片互連體204的過度崩解。也了解到該壓模封裝件本體122可作為焊阻層(solder resist)，以避免該晶片互連體204延伸超過該表面導體120之暴露部分。可控制該臺階124之尺寸，以在該區域陣列裝置202上容許較小直徑之晶片互連體204。此較小直徑之晶片互連體204可容許更多個晶片互連體204在給定區域中。
參考第3圖，顯示使用第1圖用於封裝件堆疊之積體電路封裝件系統100之封裝件堆疊300之截面圖。該封裝件堆疊300之截面圖繪示具有藉由該晶片互連體204耦合於該表面導體120之區域陣列裝置302(例如球形陣列封裝件(ball grid array package))之積體電路封裝件系統100。該區域陣列裝置302於組裝之回焊程序期間可被該壓模封裝件本體122支撐。
該封裝件堆疊300可共同如上述積體電路封裝件系統100之所有態樣。這些態樣可包括減少的高度與加強的可 製造性(manufacturability)。
參考第4圖，顯示使用第1圖用於封裝件堆疊之積體電路封裝件系統100之中介層(interposer)堆疊400之截面圖。該中介層堆疊之截面圖繪示具有區域陣列裝置401之積體電路封裝件系統100，該區域陣列裝置401包括藉由該晶片互連體204耦合於該表面導體120之中介層402。該中介層402於組裝之回焊程序期間可被該壓模封裝件本體122支撐。
該中介層402可具有中介層系統側邊404與中介層組件側邊406。分離式組件408(例如電阻、電容、電感、二極體、或類似物)可被耦合於該中介層402之中介層組件側邊406上的中介層接觸點410。積體電路晶片412也可被耦合於該中介層接觸點410。
這樣的配置在中介層堆疊400之設計中可容許大量的彈性。任何安裝於該中介層402之中介層組件側邊406上的組件均可被電性連接於該積體電路封裝件系統100或被耦合於中介層堆疊400之系統板(無顯示)中之任何組件。雖然積體電路晶片412係顯示作為球形陣列裝置，此僅為範例，且該積體電路晶片412可為四邊扁平無接腳(quad flt no－lead,QFN)、引腳晶片承載器(leaded chip carrier,LCC)、或其他形態的封裝組件。
參考第5圖，顯示使用第1圖用於封裝件堆疊之積體電路封裝件系統100在另外實施例的中介層堆疊500之截面圖。該中介層堆疊500之截面圖繪示(以反轉位置)具有 耦合至該表面導體120之系統互連體130之積體電路封裝件系統100。包括具有中介層系統側邊504與中介層組件側邊506之中介層502之區域陣列裝置501可藉由該晶片互連體204被耦合於該區域陣列基板102之系統接觸點126。
該中介層502可支撐兩個或更多個積體電路晶片412。在此組構中，該中介層堆疊500之高度可比目前所能實行的高度還低。經發現，該壓模封裝件本體122之突出物於回焊組裝程序期間可作為支撐。該壓模封裝件本體122於回焊期間可避免該系統互連體130的過度崩解。
參考第6圖，顯示本發明之第一另外實施例中用於封裝件堆疊之積體電路封裝件系統600之截面圖。該積體電路封裝件系統600之截面圖繪示具有該組件側邊104與該系統側邊106之區域陣列基板102。該區域陣列基板102可為薄板玻璃環氧樹脂、軟性磁帶、陶瓷、無機材料、低介質材料、半導體材料、或類似物。該接觸焊點112可置於該區域陣列基板102之組件側邊104上。該表面導體120可被耦合於在臺階124之區域中之接觸焊點112。該覆晶積體電路602可藉由凸塊604(例如焊凸、螺栓凸塊、焊珠、或類似物)被耦合於該接觸焊點112。
該接觸焊點112可透過通孔128被耦合於該系統接觸點126。該系統互連體130可被耦合於該區域陣列基板102之系統側邊106上的系統接觸點126。雖然第6圖繪示所有接觸焊點112直接地耦合於該系統接觸點126，但此僅 為範例之方式。於實際實施時，會在該覆晶積體電路602、該接觸焊點112、該表面導體120、該系統互連體130、或上述結合體之間形成電性連接。
該壓模封裝件本體122可形成於該區域陣列基板102之組件側邊104、該表面導體120、該覆晶積體電路602、與該凸塊604上。經發現，藉由容許壓模封裝件本體去包圍該覆晶積體電路602與該凸塊604，可改善全部封裝件疲勞壽命(fatigue life)與可靠度。
參考第7圖，顯示本發明之第二實施例中用於封裝件堆疊之積體電路封裝件系統700之截面圖。該積體電路封裝件系統700之截面圖繪示具有該組件側邊104與該系統側邊106之區域陣列基板102。該區域陣列基板102可為薄板玻璃環氧樹脂、軟性磁帶、陶瓷、無機材料、低介質材料、半導體材料、或類似物。該接觸焊點112可置於該區域陣列基板102之組件側邊104上。該表面導體120可被耦合於在臺階124之區域之接觸焊點112。該覆晶積體電路602可藉由凸塊604被耦合於該接觸焊點112，例如焊凸、螺栓凸塊、焊珠、或類似物。
該接觸焊點112可透過通孔128被耦合於該系統接觸點126。該系統互連體130可被耦合於該區域陣列基板102之系統側邊106上的系統接觸點126。雖然第7圖係繪示所有接觸焊點112直接地耦合於該系統接觸點126，此僅為範例之方式。於實際實施時，會在該覆晶積體電路602、該接觸焊點112、該表面導體120、該系統互連體130、或 上述結合體之間形成電性連接。
該壓模封裝件本體122可形成於該區域陣列基板102之組件側邊104、該表面導體120、該覆晶積體電路602、與該凸塊604上。於此組構中，該覆晶積體電路602之非主動表面(inactive surface)可被暴露於該封裝件之外部。經發現，藉由容許壓模封裝件本體去包圍該覆晶積體電路602與該凸塊604，可改善全部封裝件疲勞壽命與可靠度。
參考第8圖，顯示使用第6圖用於封裝件堆疊之積體電路封裝件系統600之封裝件堆疊800之截面圖。該封裝件堆疊800之截面圖繪示具有藉由該晶片互連體204耦合於該表面導體120之區域陣列裝置302(例如球形陣列封裝件)之積體電路封裝件系統600。該區域陣列裝置302於組裝之回焊程序期間可被該壓模封裝件本體122支撐。
該封裝件堆疊800可共用如上述積體電路封裝件系統600之所有態樣。這些態樣可包括減少的高度與加強的可製造性。
參考第9圖，顯示使用第7圖用於封裝件堆疊之積體電路封裝件系統700之封裝件堆疊900之截面圖。該封裝件堆疊900之截面圖繪示(以反轉位置)具有耦合該表面導體120之系統互連體130之積體電路封裝件系統700。
該積體電路晶片412可被直接地耦合於該系統接觸點126。在此組構中，該封裝件堆疊900之高度可比目前所能實行的高度還低。經發現，該壓模封裝件本體122之突出物於回焊組裝程序期間可作為支撐。該壓模封裝件本體 122於回焊期間可避免該系統互連體130的過度崩解。
雖然積體電路晶片412係顯示作為球形陣列裝置，但是此僅為範例且該積體電路晶片412可為四邊扁平無接腳(QFN)、引腳晶片承載器(LCC)、或其他形態的封裝組件。此組構可支撐數個積體電路晶片412或該分離式組件408與該積體電路晶片412的組合體。
參考第10圖，顯示本發明之第三實施例中用於封裝件堆疊之積體電路封裝件系統1000之截面圖。該積體電路封裝件系統1000之截面圖繪示具有該組件側邊104與該系統側邊106之區域陣列基板102。該區域陣列基板102可為薄板玻璃環氧樹脂、軟性磁帶、陶瓷、無機材料、低介質材料、半導體材料、或類似物。該接觸焊點112可置於該區域陣列基板102之組件側邊104上。該表面導體120可被耦合於在臺階124之區域之接觸焊點112。
嵌入式晶片1002(例如晶圓級晶片封裝件、再分配線晶粒(redistributed line die)、區域陣列封裝件、或類似物)可以黏著劑1004被安裝於該組件側邊104上。該嵌入式晶片1002可藉由該電子互連線114被電性耦合至該接觸焊點112。該晶片互連體204可被電性耦合於該嵌入式晶片1002的主動表面(active surface)上之互連焊點1006。
該壓模封裝件本體122可被形成於該區域陣列基板102之組件側邊104、該表面導體120、該嵌入式晶片1002、該電子互連線114、與該晶片互連體204上。該晶片互連體204以類似該表面導體120的方式部分地暴露於該壓模 封裝件本體122之外。第一區域陣列裝置1008(例如球形陣列、覆晶積體電路、或類似物)可被耦合至該表面導體120於臺階124之區域中的暴露部分。
第二區域陣列裝置1010可被同樣地安裝於臺階124之其他部位中之表面導體120。第三外部晶片1012(例如覆晶、四邊扁平無接腳晶片、或類似物)可被耦合於晶片互連體204中嵌入於嵌入式晶片1002上之壓模封裝件本體122中的暴露部分。
該接觸焊點112可透過通孔128被耦合於該系統接觸點126。該系統互連體130可被耦合於該區域陣列基板102之系統側邊106上的系統接觸點126。雖然第10圖係繪示所有接觸焊點112直接地耦合於該系統接觸點126，但是此僅為範例之方式。於實際實施時，會在該嵌入式晶片1002、該第一區域陣列裝置1008、該第二區域陣列裝置1010、該第三外部晶片1012、該接觸焊點112、該表面導體120、該系統互連體130、或上述結合體之間形成電性連接。
參考第11圖，顯示本發明之實施例中用於製造使用封裝件堆疊之積體電路封裝件系統100之積體電路封裝方法1100之流程圖。該方法1100包含於方塊1102中形成區域陣列基板；於方塊1104中在該區域陣列基板上安裝表面導體；於方塊1106中在該區域陣列基板上與該表面導體上形成壓模封裝件本體；於方塊1108中在該壓模封裝件本體上提供臺階；以及於方塊1110中藉由該臺階暴露該表面導 體。
經發現，本發明因此具有數個態樣。
本發明之一種已意外被發現的態樣可提供能減少最後產品的垂直高度之堆疊式封裝系統。藉由於較小的空間增加功能數量，可達成兩個消費者電子產品之主要目的；較高的晶片密度與簡化的系統板路徑。
本發明之用於封裝件堆疊之積體電路封裝件系統的另一態樣可提供基板額外的剛性，使已完成的產品變得更可靠且較容易去製造。
本發明再另一重要的態樣為有價值地支援與服務關於降低成本、簡化系統與增加效能的歷史傾向。
關於本發明這些有價值的態樣最後促進科技的狀態至少進入下一個等級。
因此，已發現本發明之積體電路封裝件系統對於在最小空間提供多重功能之堆疊式裝置提供重要、迄今為止仍未知且不可獲得之解答、性能與實用的態樣。所產生之簡單明確、低成本、不複雜、較多功能且有效的程序與組構能藉由採用習知技術被意外地且不明顯地實施，且因此能立即適用於完全相容習知製造程序與技術之堆疊式裝置有效率地與經濟地製造。所產生之程序與組構係簡單明確、低成本、不複雜、較多功能、準確、敏感與有效，且能藉由採用習知組件來實施用於預備好、有效率與經濟之製程、應用與利用。
因該發明係以一特定的最佳模式而描述，眾多替代 的、修改的及各種變化，因前述說明而為熟悉此項技藝的人士了解所顯而易見的，據此，其係傾向包含所有這類替代的、修改的及各種變化皆於包含的專利範圍內，在此提出的所有事項或顯示於附圖係為範例之說明而非用於限制。
100‧‧‧積體電路封裝件系統
102‧‧‧區域陣列基板
104‧‧‧組件側邊
106‧‧‧系統側邊
108‧‧‧第一黏著劑
110‧‧‧第一積體電路
112‧‧‧接觸焊點
114‧‧‧電子互連線
116‧‧‧第二黏著劑
118‧‧‧第二積體電路
120‧‧‧表面導體
122‧‧‧壓模封裝件本體
123‧‧‧核心部位
124‧‧‧臺階
126‧‧‧系統接觸點
128‧‧‧通孔
130‧‧‧系統互連體
200‧‧‧積體電路堆疊
202、302、401、501‧‧‧區域陣列裝置
204‧‧‧晶片互連體
206‧‧‧封裝件高度
208‧‧‧臺階高度
300、800、900‧‧‧封裝件堆疊
400、500‧‧‧中介層堆疊
402、502‧‧‧中介層
404、504‧‧‧中介層系統側邊
406、506‧‧‧中介層組件側邊
408‧‧‧分離式組件
410‧‧‧中介層接觸點
412‧‧‧積體電路晶片
600、700、1000‧‧‧積體電路封裝件系統
602‧‧‧覆晶積體電路
604‧‧‧凸塊
1002‧‧‧嵌入式晶片
1004‧‧‧黏著劑
1006‧‧‧互連焊點
1008‧‧‧第一區域陣列裝置
1010‧‧‧第二區域陣列裝置
1012‧‧‧第三外部晶片
1100‧‧‧積體電路封裝方法
1102、1104、1106、1108、1110‧‧‧方塊
第1圖是本發明之實施例中用於封裝件堆疊之積體電路封裝件系統之截面圖；第2圖是使用第1圖用於封裝件堆疊之積體電路封裝件系統之積體電路堆疊之截面圖；第3圖是使用第1圖用於封裝件堆疊之積體電路封裝件系統之封裝件堆疊之截面圖；第4圖是使用第1圖用於封裝件堆疊之積體電路封裝件系統之中介層堆疊之截面圖；第5圖是使用第1圖用於封裝件堆疊之積體電路封裝件系統在另外實施例的中介層堆疊之截面圖；第6圖是本發明之第一實施例中用於封裝件堆疊之積體電路封裝件系統之截面圖；第7圖是本發明之第二實施例中用於封裝件堆疊之積體電路封裝件系統之截面圖；第8圖是使用第6圖用於封裝件堆疊之積體電路封裝件系統之封裝件堆疊之截面圖；第9圖是使用第7圖用於封裝件堆疊之積體電路封裝件系統之封裝件堆疊之截面圖； 第10圖是本發明之第三實施例中用於封裝件堆疊之積體電路封裝件系統之截面圖；以及第11圖是本發明之實施例中用於製造使用封裝件堆疊之積體電路封裝件系統之積體電路封裝方法之流程圖。
1100、1102、1104、1106、1108、1110‧‧‧方塊

Claims (10)

  1. 一種積體電路封裝方法(1100)，包括：形成區域陣列基板(102)；於該區域陣列基板(102)上安裝表面導體(120)；施加可移除之薄膜或材料於該表面導體(120)的部份上；在該區域陣列基板(102)上與該表面導體(120)上以臺階(124)環繞核心部位(123)形成壓模封裝件本體(122)，藉此使該核心部位(123)突出於該臺階(124)之上並作為支座，其中該臺階(124)提供該表面導體(120)之入口；以及安裝區域陣列裝置(202)，該區域陣列裝置(202)係由突出於該壓模封裝件本體(122)之上的該核心部位(123)所支撐。
  2. 如申請專利範圍第1項之方法(1100)，其中，安裝該區域陣列裝置(202)包括耦合該區域陣列裝置(202)於該表面導體(120)。
  3. 如申請專利範圍第1項之方法(1100)，其中，形成該壓模封裝件本體(122)包含：將第一積體電路(110)電性連接於該區域陣列基板(102)；將第二積體電路(118)放置於該第一積體電路(110)上；以及將塑模化合物(122)注入於該基板(102)、該表面導體 (120)、該第一積體電路(110)、與該第二積體電路(118)上。
  4. 如申請專利範圍第1項之方法(1100)，其中，安裝該表面導體(120)包含：在該區域陣列基板(102)上形成接觸焊點(112)；在該區域陣列基板(102)之相對側邊(106)上形成系統接觸點(126)；以及在該接觸焊點(112)與該系統接觸點(126)之間耦合通孔(128)。
  5. 如申請專利範圍第1項之方法(1100)，其中，形成該壓模封裝件本體(122)係包含：從該核心部位(123)減少臺階高度(208)用以形成環繞該核心部位(123)且與包含暴露該表面導體(120)的該區域陣列基板(102)共平面之之區域。
  6. 一種積體電路封裝件系統(100)，包括：區域陣列基板(102)；安裝於該區域陣列基板(102)上之表面導體(120)；可移除之薄膜或材料，係施加於該表面導體(120)的部份上；壓模封裝件本體(122)，係在該區域陣列基板(102)上與該表面導體(120)上以臺階(124)環繞核心部位(123)而形成，藉此使該核心部位(123)突出於該臺階124之上並作為支座，其中，該臺階(124)提供入口至該表面導體(120)；以及區域陣列裝置(202)，係安裝於該壓模封裝件本體 (122)上且由突出於該壓模封裝件本體(122)之上的該核心部位(123)所支撐。
  7. 如申請專利範圍第6項之系統(100)，其中，該區域陣列裝置(202)係耦合於該表面導體(120)。
  8. 如申請專利範圍第6項之系統(100)，其中，該壓模封裝件本體(122)包含：電性連接至該區域陣列基板(102)之第一積體電路(110)；於該第一積體電路(110)上之第二積體電路(118)；以及於該區域陣列基板(102)、該表面導體(120)、該第一積體電路(110)、與該第二積體電路(118)上之塑模化合物(122)。
  9. 如申請專利範圍第6項之系統(100)，其中，該表面導體(120)包含：於該區域陣列基板(102)上，具有該表面導體(120)安裝於其上之接觸焊點(112)；於該區域陣列基板(102)的相對側邊(106)上之系統接觸點(126)；以及位於該接觸焊點(112)與該系統接觸點(126)間之通孔(128)。
  10. 如申請專利範圍第6項之系統(100)，其中，該壓模封裝件本體(122)包含：從該核心部位(123)減少之臺階高度(208)，該核心 部位(123)包括環繞與具有該表面導體(120)暴露於外的該區域陣列基板(102)共平面之該核心部位(123)之區域。
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