TWI646607B - 無芯積體電路封裝系統及其製造方法 - Google Patents

無芯積體電路封裝系統及其製造方法 Download PDF

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Publication number
TWI646607B
TWI646607B TW103110435A TW103110435A TWI646607B TW I646607 B TWI646607 B TW I646607B TW 103110435 A TW103110435 A TW 103110435A TW 103110435 A TW103110435 A TW 103110435A TW I646607 B TWI646607 B TW I646607B
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Taiwan
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integrated circuit
base substrate
base
forming
circuit device
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TW103110435A
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TW201505109A (zh
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杜拜泰
阿內 史諾紗 崔斯玻特
金成洙
艾絲莉 尤索夫
尹仁相
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星科金朋有限公司
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Abstract

用於製造積體電路封裝系統的系統及方法，其係包括：形成基礎基板，其係包括：提供犧牲載板，安裝金屬片於該犧牲載板上，鋪設頂部跡線至該金屬片，形成導電凸柱於該頂部跡線上，形成覆蓋該金屬片、該頂部跡線及該導電凸柱的基礎囊封物，使該頂部跡線由該基礎囊封物的頂面露出，以及移除該犧牲載板及該金屬片；安裝積體電路裝置於該基礎基板上；以及用頂部囊封物囊封該積體電路裝置及該基礎基板。

Description

無芯積體電路封裝系統及其製造方法
本申請案主張申請於2013年3月21日之美國臨時專利申請案序號61/804,158的權益，以及併入它的專利標的作為參考資料。
本發明大體有關於一種積體電路封裝系統，且更特別的是，有關於一種無芯積體電路封裝系統。
積體電路封裝件為用於高效能電子系統的建構區塊以提供使用於產品的應用，此類產品例如有汽車、口袋型個人電腦、手機、智慧型可攜式軍用裝置、航空太空船酬載、以及一大串需要支援複雜功能之小型緊湊電子設備的其他類似產品。
小型產品，例如手機，可包含許多各有不同大小及形狀的積體電路封裝件。裝置(例如，手機)內的每個積體電路封裝件可包含大量的複雜電路。每個積體電路封裝件內的電路使用電氣連接與其他積體電路封裝件內的其他電路一起工作及通訊。
產品必須在世界市場中競爭且吸引許多消 費者或買主以獲得成功。對產品極重要的是，持續改善特徵、效能及可靠性，並同時減少產品成本、產品尺寸，以及可快速上市供消費者或買主購買。
產品內的電路數及電氣連接數為改善任何產品之特徵、效能及可靠性的關鍵。此外，實作電路及電氣連接的方式可決定封裝大小、封裝方法及個別封裝設計。企圖由於設計彈性、功能增加、有倍增效應性(leveragability)及IO連接性能增加而沒能提供針對簡化製造加工、較小尺寸、較低成本的完整解決方案。
因此，積體電路系統仍須改善良率、熱冷卻、低輪廓、改善製造及改善可靠性。鑑於持續遞增的商業競爭壓力，以及消費者預期的增長和市場上產品差異化的有利機會在遞減，找出問題的答案越來越重要。鑑於持續遞增的商業競爭壓力，以及消費者預期的增長和市場上產品差異化的有利機會在遞減，找出問題的答案至關重要。
另外，減少成本，改善效率及效能，以及滿足競爭壓力以及滿足競爭壓力的需要也增加必需找出問題答案的急迫性。長期以來大家都在尋找這些問題的解決方案，但是先前的開發沒有教導或建議任何解決方案，因此熟諳此藝者一直在逃避解決這些問題的方案。
本發明提供一種積體電路封裝系統之製造方法，其係包括：形成基礎基板，其係包括：提供犧牲載板(sacrificial carrier)，安裝金屬片於該犧牲載板上，鋪設 頂部跡線(top trace)至該金屬片，形成導電凸柱(conductive stud)於該頂部跡線上，形成覆蓋該金屬片、該頂部跡線及該導電凸柱的基礎囊封物(base encapsulation)，使該頂部跡線由該基礎囊封物的頂面露出，以及移除該犧牲載板及該金屬片；安裝積體電路裝置於該基礎基板上；以及用頂部囊封物囊封該積體電路裝置及該基礎基板。
本發明提供一種積體電路封裝系統，其係包括：基礎基板，該基礎基板包括：基礎囊封物，嵌入該基礎囊封物的頂部跡線，該頂部跡線與該基礎囊封物的頂面共面，以及在該頂部跡線上的導電凸柱，該導電凸柱嵌入該基礎囊封物，該導電凸柱與該頂部跡線共面；在該基礎基板上的積體電路裝置；以及囊封該基礎基板及該積體電路裝置的頂部囊封物。
本發明之某些具體實施例具有其他的步驟或元件可供加入或取代以上述所提及的。熟諳此藝者閱讀以下參考附圖的詳細說明可明白該等步驟或元件。
100‧‧‧積體電路封裝系統
102‧‧‧基礎基板
104‧‧‧基礎囊封物
106‧‧‧頂面
108‧‧‧底面
110‧‧‧導電凸柱
112‧‧‧頂部跡線
114‧‧‧積體電路裝置
116‧‧‧互連面
118‧‧‧非主動面
120‧‧‧晶片互連線
122‧‧‧頂部囊封物
124‧‧‧系統互連線
130‧‧‧底部凹處
132‧‧‧頂部凹處
300‧‧‧積體電路封裝系統
302‧‧‧配線互連線
400‧‧‧積體電路封裝系統
402‧‧‧堆疊式裝置
404‧‧‧堆疊式互連線
500‧‧‧積體電路封裝系統
502‧‧‧重分佈層
602‧‧‧犧牲載板
604‧‧‧金屬片
902‧‧‧黏著劑
1501‧‧‧連接盤接觸面
1502‧‧‧介電層
1504‧‧‧底部跡線
1600‧‧‧積體電路封裝系統
1602‧‧‧條帶
1604‧‧‧重疊輪緣
1606‧‧‧模具搭接部
1700‧‧‧積體電路封裝系統
1702‧‧‧凸緣
1816‧‧‧頂部錫球墊
1820‧‧‧周邊凹槽
1900‧‧‧方法
1902‧‧‧形成基礎基板
1904‧‧‧安裝積體電路裝置
1906‧‧‧囊封該積體電路裝置
第1圖根據本發明第一具體實施例圖示積體電路封裝系統沿著第2圖之直線1-1繪出的橫截面圖。
第2圖為積體電路封裝系統的上視圖。
第3圖根據本發明第二具體實施例圖示積體電路封裝系統沿著第2圖之直線1-1繪出的橫截面圖。
第4圖根據本發明第三具體實施例圖示積體電路封裝 系統沿著第2圖之直線1-1繪出的橫截面圖。
第5圖根據本發明第四具體實施例圖示積體電路封裝系統沿著第2圖之直線1-1繪出的橫截面圖。
第6圖圖示處於沉積製造階段的第1圖基礎基板之一部份。
第7圖圖示處於基礎囊封物製造階段的第6圖結構。 第8圖圖示處於載板移除製造階段的第7圖結構。
第9圖圖示處於蝕刻製造階段的第8圖結構。
第10圖圖示處於貼晶製造階段的第9圖結構。
第11圖圖示處於互連線附接製造階段的第10圖結構。
第12圖圖示處於頂部囊封物製造階段的第11圖結構。
第13圖圖示處於研磨製造階段的第11圖結構。
第14圖圖示處於系統互連線製造階段的第13圖結構。
第15圖圖示積體電路封裝系統之替代製程流程及積體電路封裝系統的實施例。
第16圖的部份視圖實施例圖示條帶或晶圓級尺度上的積體電路封裝系統。
第17圖的部份視圖實施例圖示條帶或晶圓級尺度上的積體電路封裝系統。
第18圖的詳細圖圖示第1圖導電凸柱的第1圖頂部凹處。
第19圖的流程圖根據本發明另一具體實施例圖示積體電路封裝系統的製造方法。
以下充分詳述數個具體實施例使得熟諳此藝者能製作及使用本發明。應瞭解，基於本揭示內容顯然仍有其他的具體實施例，以及在不脫離本發明範疇的情形下，可做出系統、方法或機械改變。
在以下的說明中，給出許多特定細節是為了讓讀者徹底了解本發明。不過，顯然在沒有該等特定細節下仍可實施本發明。為了避免混淆本發明，因此不詳細揭示一些眾所周知的電路、系統組態及製程步驟。
同樣，圖示系統具體實施例的附圖為半圖解式且不按比例繪製，特別是，圖中有些尺寸為了圖示清楚而加以誇大。同樣，儘管附圖中的視圖為了便於描述而大體以相同的方向圖示，然而大部份是用任意的方式描繪附圖。大體而言，可用任何方位操作本發明。
在揭示及描述有共同特徵的多個具體實施例時，為了便於清晰地圖解、描述及理解，通常類似及相同的特徵會用相同的元件符號描述。
為了解釋，本文所用的術語“水平面”是定義為與半導體封裝件之平面或表面平行的平面，而不管它的方向。術語“垂直”係指與剛才所定義之水平面垂直的方向。諸如“上方”、“下方”、“底面”、“頂面”、“側面”(如“側壁”)、“高於”、“低於”、“上面”、“上方”、以及“下面”之類的術語都是以水平面來定義，如附圖所示。術語“在…上”意指元件之間的直接接觸。
本文所用之術語“加工”包括另一製程步驟、沉積材料或光阻劑、圖案化、曝光、顯影、蝕刻、清洗、及/或移除材料或光阻劑，如在形成述及結構時要做的。
本發明的具體實施例有犧牲載板，其係用以保護底面封裝件的有機或金屬片或兩者之組合。在載板上面的引線指狀物(leadfinger)或跡線材料可為有凸柱的標準鎳、鈀、金或等效物。凸柱下的鍍覆直徑小於凸柱直徑讓更多空間可用於引線指狀物或跡線。凸柱的暴露或未鍍覆區可能或不部份蝕刻。
該凸柱可為銅、銅合金或其他高度導電金屬。該引線指狀物或跡線可具有視需要的選擇性鍍覆於用於打線接合型版本的接合指狀物(bond finger)上。以覆晶型而言，引線指狀物或跡線可由銅、銅合金、錫、錫合金或其他高度導電材料製成。有機保焊劑(organic solder ability preserve，OSP)上的銅或有銅的焊上墊(solder-on-pad，SOP)為視需要的。積層板或網印選項可為簡化製程代用品以及可接納有鎳-鈀-金或等效鍍覆於暴露凸柱上的LGA版本。
以多層選項或重分佈層(redistribution layer)建立選項而言，可用在多層之間有介電隔離材料的機械、雷射或微影製程建立通孔(via)。在金屬或引線指狀物或跡線面上可有視需要的層。底面保護可用防焊劑(solder resist)、壓模化合物(mold compound)或其他囊封材料。
本發明的具體實施例可處於有配線互連線及覆晶半導體裝置的混合組態。無軌或無載板方法可供翹 曲控制用。
第1圖根據本發明的第一具體實施例圖示積體電路封裝系統100沿著第2圖之直線1-1繪出的橫截面圖。積體電路封裝系統100可包括例如半導體封裝件。該橫截面圖包括本發明實施例的覆晶，其係包括焊球及連接盤網格陣列(land grid array，LGA)封裝互連線兩者，然而只圖示焊球封裝互連線。
積體電路封裝系統100可包括基礎基板102。基礎基板102可提供積體電路封裝系統100之結構的支撐。基礎基板102可包括頂面106及與頂面106相反的底面108。
基礎基板102可包括無半導體芯或電介質膜芯的無芯基板。例如，基礎基板102包括作為支撐平台的基礎囊封物104。基礎囊封物104可包括用於容納或支撐基礎基板102內之結構的材料。例如，基礎囊封物104可包括囊封用膜、環氧樹脂壓模化合物(EMC)、膜中線(wire-in-film)材料、囊封物、層合(lamination)、網印材料、或等效材料。
基礎基板102可包括導電凸柱110。導電凸柱110或凹入凸柱可提供由頂面106至底面108的電氣連接。導電凸柱110可包括例如通孔、支柱及椿。導電凸柱110嵌入基礎基板102。基礎基板102使導電凸柱110與另一導電凸柱110隔離。
導電凸柱110的凹入量可取決於基礎囊封 物104的厚度或垂直高度。例如，凹入高度可為7至17微米。導電凸柱110的直徑可為250至300微米。
導電凸柱110可包括底部凹處(bottom recess)130與頂部凹處(top recess)132。底部凹處130減少焊球或在底面108裝在導電凸柱110、上之其他互連線的高度。頂部凹處132可用形成於基礎基板102上的囊封物提供模具鎖定效益。
基礎基板102可包括頂部跡線112，其係被定義為用於提供電子訊號及電力重分佈的導電結構。頂部跡線112可包括例如重分佈層、可繞線跡線、以及嵌入配線。頂部跡線112嵌在基礎囊封物104內以及從基礎基板102的頂面106露出。
頂部跡線112的頂面可與基礎基板102的頂面106共面，這提供頂部跡線112的結構支撐及保護。頂部跡線112可包括鎳(Ni)、鈀(Pd)、金(Au)或等效導電金屬或合金。積體電路封裝系統100可包括頂部跡線112的多個實例。
積體電路封裝系統100可包括裝在頂部跡線112及基礎基板102上的積體電路裝置114。積體電路裝置114被定義為有用以實現主動電路之一或更多積體電晶體的半導體裝置。
例如，積體電路裝置114可包括互連線、被動裝置或彼等之組合。例如，覆晶或晶圓級晶片可為積體電路裝置114的代表，當前實施例圖示處於覆晶組態的積 體電路裝置114。不過，積體電路裝置114也可處於已打線組態，或堆疊式裝置的混合或組合。
積體電路裝置114可包括用於附接至基礎基板102之頂部跡線112的互連面116。積體電路裝置114的互連面116可包括製作於其上的接點。積體電路裝置114也可包括為互連面116之反面的非主動面118。
積體電路封裝系統100可包括晶片互連線120。晶片互連線120提供電氣連接以及可包括例如焊球、焊線(bond wire)或焊料。晶片互連線120提供積體電路裝置114與基礎基板102之間的電氣連接。晶片互連線120可附接至積體電路裝置114的互連面116。
積體電路封裝系統100可包括頂部囊封物122，它被定義為用於氣密性密封半導體裝置以及用於提供機械及環境保護的蓋體。可形成覆蓋或在積體電路裝置114、晶片互連線120、頂部跡線112及導電凸柱110上面的頂部囊封物122。頂部囊封物122可填入提供頂部囊封物122與基礎基板102之模具鎖定的頂部凹處132。
積體電路封裝系統100可包括在底面108安裝至導電凸柱110的系統互連線124。系統互連線124提供電氣連接以及可包括例如焊球、銲錫凸塊或焊接接點。系統互連線124提供頂部跡線112與外部組件或系統(未圖示)之間的電氣連接。
已發現，有基礎囊封物104之基礎基板102的組態及組合物簡化構造及減少由單一半導體材料構成之 基板的材料成本。例如，基礎囊封物104使用積層板、環氧樹脂或網印材料可簡化構造以及提供頂部跡線112及導電凸柱110的保護。有基礎囊封物104及嵌入跡線及凸柱的基礎基板102去除耗時半導體印刷方法的需要.
已發現，有底部凹處130的導電凸柱110減少總封裝高度，產生更薄及更細的封裝件。已發現，有頂部凹處132的導電凸柱110提供有頂部囊封物122的模具鎖定特徵。該模具鎖定特徵防止頂部囊封物122與基礎基板102剝開、分離及翹曲。
已發現，有基礎囊封物104、頂部跡線112及導電凸柱110的基礎基板102提供導電支撐結構而不破壞諸如鑽孔及雷射剝離之類的方法。該等導電結構在囊封前配置，這可去除在後續製程步驟中鑽孔的需要。可保留構造材料以及去除清洗步驟，這可減少總製造步驟及改善生產良率。
已發現，有導電凸柱110嵌在基礎囊封物104內的基礎基板102提供球柵陣列(ball-grid array，BGA)組態的多樣性以及有少樣變體的連接盤網格陣列(LGA)組態。積體電路封裝系統100提供與LGA及BGA組態相容的通用封裝件。
第2圖圖示積體電路封裝系統100的上視圖。圖示頂部囊封物122的頂面。
第3圖根據本發明的第二具體實施例圖示積體電路封裝系統300沿著第2圖之直線1-1繪出的橫截 面圖。該橫截面圖包括本發明的打線具體實施例。該具體實施例可具有焊球及LGA封裝互連線，然而只圖示焊球封裝互連線。
積體電路封裝系統300類似於第1圖的積體電路封裝系統100，除了積體電路封裝系統300不包括第1圖的晶片互連線120以外。積體電路封裝系統300可包括基礎基板102，導電凸柱110，頂部跡線112，頂部囊封物122，及系統互連線124。
積體電路裝置114圖示成其係處於打線組態，然而應瞭解，積體電路裝置114可處於如第1圖所示的覆晶組態。積體電路裝置114的互連面116與基礎基板102方向相反。積體電路封裝系統300可包括配線互連線302。
配線互連線302可提供裝在基礎基板102上之裝置的電氣連接。例如，配線互連線302可附接至積體電路裝置114用以提供積體電路裝置114與頂部跡線112之間的電氣連接。頂部跡線112可包括選擇性鍍覆於接合指狀物用以附接至配線互連線302。
已發現，有基礎囊封物104之基礎基板102的組態及組合物簡化構造及減少由單一半導體材料構成之基板的材料成本。例如，基礎囊封物104使用積層板、環氧樹脂或網印材料可簡化構造以及提供頂部跡線112及導電凸柱110的保護。有基礎囊封物104及嵌入跡線及凸柱的基礎基板102去除耗時半導體印刷方法的需要.
已發現，有底部凹處130的導電凸柱110減少總封裝高度，產生更薄及更細的封裝件。已發現，有頂部凹處132的導電凸柱110提供有頂部囊封物122的模具鎖定特徵。該模具鎖定特徵防止頂部囊封物122與基礎基板102剝開、分離及翹曲。
已發現，有基礎囊封物104、頂部跡線112及導電凸柱110的基礎基板102提供導電支撐結構而不破壞諸如鑽孔及雷射剝離之類的方法。該等導電結構在囊封前配置，這可去除在後續製程步驟中鑽孔的需要。可保留構造材料以及去除清洗步驟，這可減少總製造步驟及改善生產良率。
已發現，有導電凸柱110嵌在基礎囊封物104內的基礎基板102提供球柵陣列(BGA)組態的多樣性以及有少樣變體的連接盤網格陣列(LGA)組態。積體電路封裝系統100提供與LGA及BGA組態相容的通用封裝件。
第4圖根據本發明的第三具體實施例圖示積體電路封裝系統400沿著第2圖之直線1-1繪出的橫截面圖。該橫截面圖包含本發明的覆晶及打線組態或混合組態。該具體實施例可具有焊球及連接盤網格陣列(LGA)封裝互連線，然而只圖示焊球封裝互連線。
積體電路封裝系統400可包括第1圖的組件，包括基礎基板102、導電凸柱110、頂部跡線112、頂部囊封物122、積體電路裝置114、晶片互連線120及系統互連線124。
積體電路封裝系統400類似於第1圖的積體電路封裝系統100，除了積體電路封裝系統400包括裝在積體電路裝置114上面的堆疊式裝置402以外。堆疊式裝置402被定義為有用以實現主動電路之一或更多積體電晶體的半導體裝置。
堆疊式裝置402圖示成其係處於打線組態，然而應瞭解，積體電路裝置114可處於覆晶組態。堆疊式裝置402用黏著劑附接至積體電路裝置114。堆疊式裝置402包括小於積體電路裝置114之橫向尺寸的橫向尺寸或寬度，這允許堆疊式裝置402裝在積體電路裝置114上面。
積體電路封裝系統400包括堆疊式互連線404，其係提供裝在基礎基板102上之裝置的電氣連接。堆疊式互連線404可包括打線用以使堆疊式裝置402附接至基礎基板102。頂部跡線112可包括選擇性鍍覆於接合指狀物用以附接至堆疊式互連線404。
已發現，有基礎囊封物104之基礎基板102的組態及組合物簡化構造及減少由單一半導體材料構成之基板的材料成本。例如，基礎囊封物104使用積層板、環氧樹脂或網印材料可簡化構造以及提供頂部跡線112及導電凸柱110的保護。有基礎囊封物104及嵌入跡線及凸柱的基礎基板102去除耗時半導體印刷方法的需要.
已發現，有底部凹處130的導電凸柱110減少總封裝高度，產生更薄及更細的封裝件。已發現，有 基礎囊封物104、頂部跡線112及導電凸柱110的基礎基板102提供導電支撐結構而不破壞諸如鑽孔及雷射剝離之類的方法。該等導電結構在囊封前配置，這可去除在後續製程步驟中鑽孔的需要。可保留構造材料以及去除清洗步驟，這可減少總製造步驟及改善生產良率。
已發現，有導電凸柱110嵌在基礎囊封物104內的基礎基板102提供球柵陣列(BGA)組態的多樣性以及有少樣變體的連接盤網格陣列(LGA)組態。積體電路封裝系統100提供與LGA及BGA組態相容的通用封裝件。
第5圖根據本發明第四具體實施例圖示積體電路封裝系統500沿著第2圖中之直線1-1繪出的橫截面圖。該橫截面圖包括本發明的打線具體實施例。該具體實施例可具有焊球及連接盤網格陣列(LGA)封裝互連線，然而只圖示焊球封裝互連線。
積體電路封裝系統500類似於第3圖的積體電路封裝系統300，除了積體電路封裝系統300包括重分佈層502以外。積體電路封裝系統300可包括基礎基板102，導電凸柱110，頂部跡線112，第1圖的頂部囊封物122，以及第1圖的系統互連線124。
積體電路裝置114圖示成處於打線組態，然而應瞭解，積體電路裝置114可處於如第1圖所示的覆晶組態。積體電路封裝系統300可包括配線互連線302。
配線互連線302可提供裝在基礎基板102上之裝置的電氣連接。例如，配線互連線302可附接至積 體電路裝置114用以提供積體電路裝置114與頂部跡線112之間的電氣連接。頂部跡線112可包括選擇性鍍覆於用以附接至配線互連線302的接合指狀物。
重分佈層502或多層可包括被介電材料包圍的跡線。重分佈層502可直接裝在有頂部跡線112嵌在介電材料內的基礎基板102上。來自重分佈層502的跡線可直接附接至頂部跡線112以及可嵌在基礎囊封物104內。導電凸柱110可與重分佈層502的跡線直接接觸以及配線互連線302可附接至頂部跡線112。
已發現，有基礎囊封物104之基礎基板102的組態及組合物簡化構造及減少由單一半導體材料構成之基板的材料成本。例如，基礎囊封物104使用積層板、環氧樹脂或網印材料可簡化構造以及提供頂部跡線112及導電凸柱110的保護。有基礎囊封物104及嵌入跡線及凸柱的基礎基板102去除耗時半導體印刷方法的需要。已發現，有底部凹處130的導電凸柱110減少總封裝高度，產生更薄及更細的封裝件。
無意中發現，有基礎囊封物104、頂部跡線112及導電凸柱110的基礎基板102提供導電支撐結構而不破壞諸如鑽孔及雷射剝離之類的方法。該等導電結構在囊封前配置，這可去除在後續製程步驟中鑽孔的需要。可保留構造材料以及去除清洗步驟，這可減少總製造步驟及改善生產良率。
已發現，有導電凸柱110嵌在基礎囊封物 104內的基礎基板102提供球柵陣列(BGA)組態的多樣性以及有少樣變體的連接盤網格陣列(LGA)組態。積體電路封裝系統100提供與LGA及BGA組態相容的通用封裝件。
第6圖圖示處於沉積製造階段的第1圖基礎基板102之一部份。提供犧牲載板602與金屬片604。犧性載板602可包括例如金屬載板，SUS板，FR4板，或聚合物加強板。
金屬片604可包括導電材料，例如銅。金屬片604裝設於犧牲載板602上面。金屬片604提供用於安裝導電結構(例如，第1圖的頂部跡線112及第1圖的導電凸柱110)的平台。
金屬片604也可包括有機材料。有有機材料的金屬片604可用來保護頂部跡線112及沉積於其上的導電凸柱110。該有機材料可由碳構成以及提供裝在其上之組件的剛性及結構支撐。
頂部跡線112可直接形成於金屬片604上。導電凸柱110可形成於頂部跡線112之一部份及金屬片604上。導電凸柱110可由與金屬片604相同以及與頂部跡線112不同的材料構成。頂部跡線112面向金屬片604的表面與導電凸柱110面向金屬片604的表面共面。
已發現，藉由允許同時建立第1圖的頂部凹處132，由相同導電材料構成的金屬片604及導電凸柱110減少製造步驟。例如，由移除金屬片604以暴露頂部跡線112時，單一製程也可建立頂部凹處132，而不是單獨使用 用於建立頂部凹處132的蝕刻製程。
第7圖圖示處於基礎囊封物製造階段的第6圖結構。藉由用基礎囊封物104囊封導電凸柱110、頂部跡線112及金屬片604來形成第1圖的基礎基板102。基礎基板102可用環氧樹脂模製化合物(EMC)、網印材料、薄膜、層合、或等效囊封材料形成。導電凸柱110與金屬片604面對的表面可用基礎囊封物104覆蓋。
第8圖圖示處於載板移除製造階段的第7圖結構。第7圖的犧牲載板602被移除而暴露金屬片604。
第9圖圖示處於蝕刻製造階段的第8圖結構。第8圖的金屬片604被移除。在此階段期間，也可用同一個蝕刻製程建立頂部凹處132。此外，可進一步加工頂部凹處132至按照封裝系統之規格要求的特定深度及形狀。
頂部凹處132的凹入量可取決於基礎囊封物104的厚度或垂直高度。例如，頂部凹處132的凹入高度或深度可為10至25微米。
第10圖圖示處於貼晶製造階段的第9圖結構。第3圖的積體電路裝置114可附接至基礎基板102。黏著劑902(例如，膠帶或黏著膏)可用來使積體電路裝置114附接至基礎基板102。
第11圖圖示處於互連線附接製造階段的第10圖結構。第3圖的配線互連線302可用來提供由互連面116至頂部跡線112的電氣連接。可選擇性地鍍覆頂部跡 線112以形成用於附接至配線互連線302的接合指狀物。
第12圖圖示處於頂部囊封物製造階段的第11圖結構。形成覆蓋第3圖之基礎基板102、第3圖之導電凸柱110、第3圖之頂部跡線112、第3圖之積體電路裝置114以及第3圖之配線互連線302的頂部囊封物122。
頂部囊封物122可用環氧樹脂模製化合物(EMC)、薄膜、或等效囊封材料形成。頂部囊封物122可填入蝕刻進入低於基礎基板102頂面之導電凸柱110的頂部凹處132。已發現，在導電凸柱110頂部凹處132內的頂部囊封物122提供模具鎖定優點，這可防止頂部囊封物122與基礎基板102拉開。
第13圖圖示處於研磨製造階段的第11圖結構。可研磨或拋光第3圖之基礎基板102的底面108以便減少高度及使導電凸柱110由基礎基板102的底面108露出。底部凹處130用研磨或拋光形成。導電凸柱110從底面108凹入。
第14圖圖示處於系統互連線製造階段的第13圖結構。系統互連線124可附接至在底部凹處130內的導電凸柱110。替換地，藉由在沒有第3圖的底部凹處130下附接連接盤至導電凸柱110，第13圖的結構可用於LGA組態。連接盤可附接至LGA組態的導電凸柱110。
第15圖圖示積體電路封裝系統100及積體電路封裝系統500的替代製程流程實施例。製造流程可包括圖示於第6圖至第14圖之步驟的變體。
為使解釋簡潔，省略第6圖至第14圖之製造流程的一些製程步驟以強調變更，然而應瞭解，該等變更可包括相同製程步驟的組合。該等實施例可顯示犧牲載板602。
在一實施例中，第1圖的積體電路裝置114圖示成其係安裝至第1圖的基礎基板102。晶片互連線120用在呈覆晶組態的積體電路裝置114，而不是第3圖的配線互連線302。囊封及研磨的製程步驟可與第12圖至第14圖的步驟相同。
該實施例可包括連接盤接觸面1501。連接盤接觸面1501為導電凸柱110的底面。連接盤接觸面1501可用於LGA組態的連接盤附接。
該實施例也包含積體電路封裝系統500的詳細圖。重分佈層502可包括介電層1502與底部跡線(bottom trace)1504。介電層1502直接形成於頂部跡線112及金屬片604上，在此介電層1502的表面與頂部跡線112及金屬片604共面。
為了插入底部跡線1504，可加工、印刷或圖案化介電層1502。包括用於提供電子訊號及電力重分佈之導電結構的底部跡線1504可形成於介電層1502上方以及通過形成於介電層1502中的孔與頂部跡線112直接接觸。在用基礎囊封物104囊封後，底部跡線1504嵌入基礎囊封物104以及用介電層1502隔離頂部跡線112與基礎囊封物104。
重分佈層502也可為多層。積體電路封裝系統500也可包括裝在積體電路裝置114上方的堆疊式裝置402。積體電路封裝系統500的製造流程也可包括層合或網印緣形成積體電路封裝系統500的基礎囊封物104。
無意中發現，介電層1502與底部跡線1504可直接形成於金屬片604及頂部跡線112上，這提供簡化的製程以及共面的表面。此簡化製程排除分開的製造步驟以及允許頂部跡線112及重分佈層502在相同的製造階段期間形成。
也已發現，重分佈層502可用有限的橫向尺寸提供更多繞線選項(routing option)以及封裝件的繞線表面積。重分佈層502提供更多繞線表面積及路徑用於包含在封裝件內或裝在積體電路裝置114上面的多個晶粒。
第16圖圖示在條帶或晶圓級尺度(wafer-level scale)上之積體電路封裝系統1600的部份視圖實施例。積體電路封裝系統1600可類似於積體電路封裝系統300，除了積體電路封裝系統1600已預先切單以外。
該實施例包括積體電路封裝系統300的多個實例供在後面的製造階段切單用。該等多個實例可形成於大基礎載板上。例如，第6圖至第14圖的製造步驟可在大條帶尺度上進行，如積體電路封裝系統1600的實施例所示。積體電路封裝系統1600可包括條帶1602、重疊輪緣1604及模具搭接部(mold overlap)1606。
重疊輪緣1604被定義為突出邊緣、軸環或 肋條用以強化或支撐卡槽(magazine)上的條帶1602。重疊輪緣1604附接或延伸到基礎囊封物104以及可由與基礎囊封物104相同的材料構成。
重疊輪緣1604橫向延伸超出頂部囊封物122的橫向尺寸。重疊輪緣1604藉由在多個封裝件的切單期間提供握持點來提供結構支撐及翹曲控制。重疊輪緣1604減少用頂部囊封物122包住之結構及組件的損傷及震動。
已發現，重疊輪緣1604可提供接觸點用以保持在用於後繼製程的卡槽上，這允許條帶1602使用無軌系統。重疊輪緣1604也可提供用於在條帶層級上的無軌或無載板製程。重疊輪緣1604提供單元層級翹曲控制的效益以及節省用於軌道的構造材料。
模具搭接部1606為頂部囊封物122與基礎基板102相交的邊緣。藉由在基礎囊封物104中提供一凹處，可形成模具搭接部1606。頂部囊封物122形成於基礎囊封物104上，以及基礎囊封物104在該模具搭接部的部份包圍頂部囊封物122的橫向側壁之一部份。已發現，模具搭接部1606提供封裝件的模具鎖定效益以及防止頂部囊封物122與基礎囊封物104分離。
第17圖圖示條帶或晶圓級尺度上之積體電路封裝系統1700的部份視圖實施例。積體電路封裝系統1700可類似於積體電路封裝系統1600，除了積體電路封裝系統1700包括凸緣1702以外。積體電路封裝系統1700可 包括模具搭接部1606。
積體電路封裝系統300可包括附接至基礎囊封物104的凸緣1702。凸緣1702由與基礎囊封物104相同的材料構成以及凸緣1702橫向延伸超出頂部囊封物122。凸緣1702被定義為突出輪緣、軸環或肋條用以強化或支撐卡槽上的條帶1602。
凸緣1702附接或延伸到基礎囊封物104以及可由與基礎囊封物104相同的材料構成。凸緣1702由頂面106伸出但是在底面下切(undercut)而形成比基礎囊封物104之寬度薄的輪緣。凸緣1702藉由在多個封裝件之切單期間提供握持點來提供結構支撐及翹曲控制。凸緣1702減少用頂部囊封物122包住之結構及組件的損傷及震動。
已發現，凸緣1702可提供接觸點用以保持在用於後繼製程的卡槽上，這允許條帶1602使用無軌系統。凸緣1702也可提供用於在條帶層級上的無軌或無載板製程。凸緣1702提供單元層級翹曲控制的效益以及節省用於軌道的構造材料。
第18圖的詳細圖圖示第1圖之導電凸柱110的頂部凹處132。該詳細圖包括導電凸柱110及頂部跡線112的等角視圖及上視圖。該等角視圖包括頂部錫球墊(top ball pad)1816、周邊凹槽(peripheral groove)1820、頂部跡線112及導電凸柱110。該等詳細圖係沿著基礎基板102之橫截面視圖的直線A-A及B-B繪出。
在蝕刻第6圖的金屬片604後，可由頂部跡 線112在導電凸柱110上的一部份形成頂部錫球墊1816。導電凸柱110的表面可包圍頂部錫球墊1816，以及頂部錫球墊1816可部份嵌入導電凸柱110。
可進一步蝕刻導電凸柱110中包圍頂部錫球墊1816的表面用以形成周邊凹槽1820。頂部凹處132可包括周邊凹槽1820。藉由在導電凸柱110中包圍頂部錫球墊1816的區域上開溝來形成周邊凹槽1820。導電凸柱110可包括周邊凹槽1820或導電凸柱110可保持無溝槽，這取決於系統的製造要求。
已發現，周邊凹槽1820可提供結構效益，例如適當的端子直徑及更多跡線空間。此外，周邊凹槽1820或頂部凹處132可提供第1圖之頂部囊封物122的模具鎖定機構。也已發現，部份蝕刻周邊凹槽1820防止頂部錫球墊1816在頂部錫球墊1816建立期間下切。
第19圖的流程圖根據本發明另一具體實施例製造積體電路封裝系統100的方法1900。方法1900包括：在區塊1902，形成基礎基板，其係包括：提供犧牲載板：安裝金屬片於該犧牲載板上，鋪設頂部跡線至該金屬片，形成導電凸柱於該頂部跡線上，形成覆蓋該金屬片、該頂部跡線及該導電凸柱的基礎囊封物，使該頂部跡線由該基礎囊封物的頂面露出，以及移除該犧牲載板及該金屬片；在區塊1904，安裝積體電路裝置於該基礎基板上；以及在區塊1906，用頂部囊封物囊封該積體電路裝置及該基礎基板。
所得方法、製程、設備、裝置、產品及/或系統簡單明瞭、有成本效益、不複雜、高度通用及有效，而且令人意外及不明顯的是，它的具體實作可藉由修改習知技術，從而輕易適合用來有效及經濟地製造完全相容於習知方法或製程及技術的無芯及無載板半導體封裝件系統。
本發明的另一重要方面在於有價值地支援及服務節省成本、簡化系統及提高效能的歷史趨勢。
結果，本發明以上與其他有價值的方面可促進技術狀態至少到下一個階段。
儘管已結合特定的最佳模式來描述本發明，顯然熟諳此藝者基於上述說明應瞭解，仍有許多替代、修改及變體。因此，希望所有的替代、修改及變體皆落入隨附申請專利範圍的範疇。所有迄今為止在本文及附圖中提及的事項應被解釋成只是用來做圖解說明而沒有限定本發明的意思。

Claims (10)

  1. 一種製造積體電路封裝系統之方法，包括：形成基礎基板，係包括：提供犧牲載板，安裝金屬片於該犧牲載板上，鋪設頂部跡線至該金屬片，形成導電凸柱於該頂部跡線上，形成於該金屬片、該頂部跡線及該導電凸柱上方的基礎囊封物，該頂部跡線由該基礎囊封物的頂面露出，以及移除該犧牲載板及該金屬片；安裝積體電路裝置於該基礎基板上；以及以頂部囊封物囊封該積體電路裝置及該基礎基板。
  2. 如申請專利範圍第1項所述之方法，更包括在形成該導電凸柱之後，在該導電凸柱中形成底部凹處。
  3. 如申請專利範圍第1項所述之方法，其中，形成該導電凸柱包括形成與該頂部跡線共面的該導電凸柱。
  4. 如申請專利範圍第1項所述之方法，更包括在該積體電路裝置與該基礎基板之間形成重分佈層。
  5. 如申請專利範圍第1項所述之方法，其中，安裝該積體電路裝置包括在該積體電路裝置與該基礎基板之間附接晶片互連件。
  6. 一種製造半導體封裝件之方法，包括：形成基礎基板，係包括：提供犧牲載板，安裝金屬片於該犧牲載板上，鋪設頂部跡線至該金屬片，形成導電凸柱於該頂部跡線上，形成於該金屬片、該頂部跡線及該導電凸柱的基礎囊封物，該頂部跡線由該基礎囊封物的頂面露出，以及移除該犧牲載板及該金屬片；以及安裝積體電路裝置於該基礎基板上；以頂部囊封物囊封該積體電路裝置及該基礎基板；加工該基礎基板的底面，以暴露該導電凸柱；以及在該底面附接系統互連件至該導電凸柱。
  7. 如申請專利範圍第6項所述之方法，更包括在形成該導電凸柱之後，在該導電凸柱中形成底部凹處及頂部凹處。
  8. 如申請專利範圍第6項所述之方法，其中，安裝該積體電路裝置包括直接安裝該積體電路裝置於該頂部跡線上。
  9. 如申請專利範圍第6項所述之方法，更包括在形成該導電凸柱之後，形成周邊凹槽於該導電凸柱中，該周邊凹槽包圍該頂部跡線與該導電凸柱接觸的一部份。
  10. 如申請專利範圍第6項所述之方法，其中，形成該基礎囊封物包括：形成凸緣於該基礎囊封物上，該凸緣橫向延伸超出該頂部囊封物；以及形成覆蓋該頂部囊封物之側面的模具搭接部。
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Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US9165878B2 (en) * 2013-03-14 2015-10-20 United Test And Assembly Center Ltd. Semiconductor packages and methods of packaging semiconductor devices
TWI587463B (zh) * 2014-11-12 2017-06-11 矽品精密工業股份有限公司 半導體封裝結構及其製法
TWI560818B (en) * 2014-12-05 2016-12-01 Siliconware Precision Industries Co Ltd Electronic package and the manufacture thereof
US9859200B2 (en) * 2014-12-29 2018-01-02 STATS ChipPAC Pte. Ltd. Integrated circuit packaging system with interposer support structure mechanism and method of manufacture thereof
US10128207B2 (en) * 2015-03-31 2018-11-13 Stmicroelectronics Pte Ltd Semiconductor packages with pillar and bump structures
DE112015006855T5 (de) * 2015-08-28 2018-08-16 Intel IP Corporation Mikroelektronik-Packages mit hochintegriertem Mikroelektronik-Dice-Stapel
TWI575619B (zh) * 2015-12-09 2017-03-21 南茂科技股份有限公司 半導體封裝結構及其製作方法
US10381295B2 (en) * 2017-09-12 2019-08-13 Nxp Usa, Inc. Lead frame having redistribution layer
US20190181115A1 (en) * 2017-12-08 2019-06-13 Dialog Semiconductor (Uk) Limited Wafer Level Molded PPGA (Pad Post Grid Array) for Low Cost Package
DE102019130898A1 (de) * 2019-08-16 2021-02-18 Infineon Technologies Ag Zweistufige laserbearbeitung eines verkapselungsmittels eines halbleiterchipgehäuses
FR3147043A1 (fr) * 2023-03-22 2024-09-27 Stmicroelectronics International N.V. Procédé de fabrication d’une pluralité de composants électroniques

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237487A1 (en) * 2007-12-17 2010-09-23 National Semiconductor Corporation Methods and systems for packaging integrated circuits
TW201142968A (en) * 2010-05-20 2011-12-01 Adl Engineering Inc Semiconductor package structure and method for fabricating the same
US20130062761A1 (en) * 2011-09-09 2013-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures for Semiconductor Devices

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5901041A (en) * 1997-12-02 1999-05-04 Northern Telecom Limited Flexible integrated circuit package
KR100394808B1 (ko) * 2001-07-19 2003-08-14 삼성전자주식회사 웨이퍼 레벨 적층 칩 패키지 및 그 제조 방법
KR100701676B1 (ko) * 2004-04-28 2007-03-29 매그나칩 반도체 유한회사 반도체 칩 패키지의 제조 방법
JP2008093727A (ja) * 2006-10-16 2008-04-24 Sintokogio Ltd 鋳型
TWI414048B (zh) * 2008-11-07 2013-11-01 Advanpack Solutions Pte Ltd 半導體封裝件與其製造方法
KR101132304B1 (ko) * 2010-05-06 2012-04-05 주식회사 하이닉스반도체 반도체 패키지 및 그 제조방법
TWI543327B (zh) 2010-08-31 2016-07-21 先進封裝技術私人有限公司 半導體承載元件
CN107369668B (zh) 2011-07-22 2020-08-25 先进封装技术私人有限公司 用于制造半导体封装元件的半导体结构
US20130072012A1 (en) * 2011-09-16 2013-03-21 Bo-Yu Tseng Method For Forming Package Substrate With Ultra-Thin Seed Layer

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20100237487A1 (en) * 2007-12-17 2010-09-23 National Semiconductor Corporation Methods and systems for packaging integrated circuits
TW201142968A (en) * 2010-05-20 2011-12-01 Adl Engineering Inc Semiconductor package structure and method for fabricating the same
US20130062761A1 (en) * 2011-09-09 2013-03-14 Taiwan Semiconductor Manufacturing Company, Ltd. Packaging Methods and Structures for Semiconductor Devices

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