TW201511149A - 具有鍍覆引線之積體電路封裝系統及其製造方法 - Google Patents
具有鍍覆引線之積體電路封裝系統及其製造方法 Download PDFInfo
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Abstract
一種積體電路封裝系統及其製造方法包含:提供具有未處理引線的引線架;在該未處理引線之頂部表面上沉積蝕刻遮罩,該未處理引線具有該蝕刻遮罩與該頂部表面之未遮罩部分;連接積體電路晶粒至該未處理引線;以封裝件主體包覆該引線架,該未處理引線之該頂部表面從該封裝件主體暴露出來;形成可側焊引線,包含形成溝槽在該未處理引線中,該溝槽形成在該蝕刻遮罩之一部分之下包含在該溝槽上方形成該蝕刻遮罩之懸伸物;移除該蝕刻遮罩;以及沉積電鍍在該可側焊引線上。
Description
本發明大致上係關於積體電路封裝系統,且尤係關於具有鍍覆引線之系統。
半導體晶片日益變得更加複雜,絕大部分是受到微型或輕便型電子裝置(例如手機、智慧型手機、個人媒體系統、超輕便型電腦)的小晶片尺寸對於提升處理能力的需求所驅使。
對於封裝積體電路(IC)晶粒,有一些傳統製程。經由範例,許多IC封裝件利用從金屬片衝壓(stamped)或蝕刻之金屬引線架(leadframe)來提供電性互連至外部裝置。晶粒可藉由接合導線(bonding wire)、焊錫凸塊或其他合適的電性連接而電性連接至引線。
一般而言,晶粒與引線架之部分係以模製材料(molding material)包覆以保護晶粒之主動面上脆弱的電子元件,同時讓引線架之選定部分保持暴露以利於電性連接至外部裝置。
針對較小的晶片尺寸,封裝技術已再進化成例如能夠增加引線密度,這能縮小安裝在印刷電路板(PCB)上之封裝件的佔板面積(footprint area)。某些封裝技術可藉由提供數列引線連接至引線架之可任意使用部分(disposable portion)而增加引線密度。
可期望的是,能以額外的方式進一步縮小封裝件尺寸。同時,也期望維持封裝件與連接有足夠的結構完整性。也可期望的是,規劃一種被設計成符合這些目的的封裝製程。現有的封裝方案能夠符合這些目的中的某一些,但可能無法滿足大部分或者全部的這些目的。
因此,仍然需要一種更佳的製造方法。有鑑於對可靠度的需求,尋找這些問題的解答變得日益重要。有鑑於持續增加的市場競爭壓力,以及消費者期望的持續增長和市場上產品差異化的有利機會在遞減,找出問題的答案至關重要。另外,減少成本、改善效率及效能、以及滿足競爭壓力的需要也增加必需找出問題答案的急迫性。
長期以來已在尋找這些問題的解決方案,但是先前的開發沒有教導或建議任何解決方案,因此解決這些問題的方案一直困惑著技術領域中具有通常知識者。
本發明提供一種積體電路封裝系統之製造方法,包含:提供具有未處理引線的引線架;在該未處理引線之頂部表面上沉積蝕刻遮罩,該未處理引線具有該蝕
刻遮罩與該頂部表面之未遮罩部分;連接積體電路晶粒至該未處理引線;以封裝件主體包覆該引線架,該未處理引線之該頂部表面從該封裝件主體暴露出來;形成可側焊引線,包含形成溝槽在該未處理引線中,該溝槽形成在該蝕刻遮罩之一部分之下包含在該溝槽上方形成該蝕刻遮罩之懸伸物;移除該蝕刻遮罩;以及沉積電鍍在該可側焊引線上。
除上述之外或替代上述者,本發明之某些實施例具有其他步驟或元件。對本技術領域中具有通常知識者而言,在配合圖式閱讀下列實施方式之後,該等步驟或元件將變得顯而易見。
2、4、5‧‧‧虛線矩形
100‧‧‧積體電路封裝系統
102‧‧‧晶粒墊
104‧‧‧封裝件主體
106‧‧‧可側焊引線
108‧‧‧電鍍
110‧‧‧無電鍍部分
112‧‧‧溝槽
314‧‧‧引線架
316‧‧‧蝕刻遮罩
318‧‧‧未處理引線
320‧‧‧未遮罩部分
900‧‧‧方法
902、904、906、908、910、912、914‧‧‧方塊
第1圖係本發明之實施例中之積體電路封裝系統的等角俯視圖。
第2圖係由第1圖之虛線矩形所繪之插圖內的第1圖之細節圖。
第3圖係引線架在製造之遮罩階段的等角俯視圖。
第4圖係由第3圖之虛線矩形所繪之插圖內的第3圖之細節圖。
第5圖係在製造之包覆階段中,由第3圖之虛線矩形所繪之插圖內的第3圖之未處理引線的等角俯視圖。
第6圖係在製造之蝕刻階段中第5圖之結構。
第7圖係在製造之電鍍階段中第6圖之結構。
第8圖係在製造之切單階段中第7圖之結構。
第9圖係本發明之另一實施例中製造積體電路封裝系統之方法的流程圖。
以下充分詳細地描述數個具體實施例使得技術領域中具有通常知識者能製作及使用本發明。應瞭解,基於本揭示內容顯然仍有其他的具體實施例,以及在不脫離本發明範疇的情形下,可做出系統、製程或機械改變。
在以下的說明中,給出許多特定細節是為了讓讀者徹底了解本發明。不過,顯然在沒有該等特定細節下仍可實施本發明。為了避免混淆本發明,而不詳細揭示一些眾所周知的電路、系統組態及製程步驟。
同樣,圖示系統具體實施例的附圖為半圖解式且不按比例繪製,特別是,圖中有些尺寸為了圖示清楚而加以誇大。同樣,儘管附圖中的視圖為了便於描述而大體以相同的方向圖示,然而大部份是用任意的方式描繪附圖。大體而言,可用任何方位操作本發明。
在所有圖式中,使用相同的數字來與相同的元件關聯。圍繞圖形的波浪線係用來表示僅顯示結構之一部分。
為了解釋,本文所用之術語“水平面”的定義是與可側焊引線(side-solderable lead)之平面或表面平行的平面,而不管它的方向。術語“垂直”係指與剛才所
定義之水平面垂直的方向。諸如“上方”、“下方”、“底面”、“頂面”、“側面”(如“側壁”)、“高於”、“低於”、“較上面”、“上面”、以及“下面”等等之術語的定義相對於該水平面,如附圖所示。術語“在…上”是意指元件之間的直接接觸。術語“直接在…上”意指一元件與另一元件直接接觸而沒有中介元件。
術語“主動面”意指晶粒、模組、封裝件或電子結構中有活性電路製造於其上或有元件用以連接至晶粒、模組、封裝件或電子結構內之主動電路的那一面。
本文所用之術語“加工”包含沉積材料或光阻劑、圖案化、曝光、顯影、蝕刻、清洗、及/或移除材料或光阻劑,如在形成述及結構時要做的。
現在參照第1圖,其中顯示本發明之實施例中之積體電路封裝系統100的等角俯視圖。等角俯視圖顯示晶粒墊102、封裝件主體104和可側焊引線106。晶粒墊102能具有接附至底面的積體電路晶粒(未圖示),並且被包覆在封裝件主體104中。晶粒墊102能作用成幫助散熱、作為積體電路晶粒的接地面、或其組合。積體電路封裝系統100可以例如是四面扁平無鉛封裝件(Quad Flat No-Lead package;QFN)。
晶粒墊102和可側焊引線106係嵌埋在封裝件主體104中,同時也從封裝件主體104暴露出來。封裝件主體104可保護積體電路晶粒,並且可以是例如環氧模製化合物、樹脂或其他非導電材料之材料。積體電路晶粒
能用例如接合導線之互連件(未圖示)而被連接至可側焊引線106。
晶粒墊102和可側焊引線106可從例如銅之金屬製成,並且在晶粒墊102和可側焊引線106之大部分暴露表面上能具有電鍍108。電鍍108作用為用於經由焊錫而連接至電路板或其他系統的焊錫可濕潤表面(solder-wettable surface),並且可由例如錫、共熔化合物、或其他焊錫可濕潤和導電材料之材料組成。電鍍108能具有5至20μm的厚度,而可側焊引線106能具有符合JEDEC標準或介於0.4mm和1.0mm之間的間距。
可側焊引線106係從封裝件主體104之頂面和側面上暴露出來。可側焊引線106之無電鍍部分110係與封裝件主體104之側同平面的可見部分。可側焊引線106之其他暴露表面(包含可側焊引線106之邊緣裡的溝槽112)係被覆蓋在電鍍108中。可側焊引線106因為溝槽112所提供的額外表面積而具有較大的表面積以供焊錫接觸,所以一旦安裝或焊接在板上就能有更強而可靠的連接來抵抗多向應力。可側焊引線106係用於連接下一層系統或板。
現在參照第2圖,其中顯示由第1圖之虛線矩形2所繪之插圖內的第1圖之細節圖。在此圖中,可看到可側焊引線106之細節,而且在各個可側焊引線106之側可看到溝槽112。溝槽112能具有彎曲形狀或平角表面與彎曲表面之組合,並且結束在可側焊引線106之無電鍍部分110。圍繞第2圖之波浪線係用來表示僅有顯示結構
之一部分。
用於例示,電鍍108係顯示為在封裝件主體104之上,但應瞭解到,電鍍108可以在相對於封裝件主體104的不同位置。例如,電鍍108可與封裝件主體108之表面同平面,或者電鍍108可在封裝件主體108之表面之下凹陷。也應瞭解到,電鍍108之厚度為誇大的視覺效果,該厚度可能比所顯示者更低。
現在參照第3圖,其中顯示引線架314在製造之遮罩階段的等角俯視圖。在此圖中,引線架314係足夠用於製造兩個第1圖之積體電路封裝系統100,但應了解到,引線架314可為任何尺寸。例如,引線架314能足夠用來製造四個、六個、九個或任何其他數量的積體電路封裝系統100。
引線架314被蝕刻遮罩316選擇性地覆蓋在該引線架314之未處理引線(unprocessed leads)318上,使得未處理引線318之未遮罩部分320暴露出來。未處理引線318之未遮罩部分320可在未處理引線318之邊緣處。蝕刻遮罩316將保護引線架314之覆蓋部分不受到後續蝕刻步驟,從而允許引線架314僅被選擇性蝕刻穿過未處理引線318之未遮罩部分320。蝕刻遮罩316可以是例如單層或多層的金屬、保護性有機材料或金屬與有機材料(例如藍墨水、環氧、樹脂等等)之組合。引線架314之未處理引線318係用作為基底以形成在進一步處理後之第1圖的可側焊引線106。
根據用於蝕刻遮罩316的材料而定,能用不同製程來鋪設該蝕刻遮罩316。例如,蝕刻遮罩316可利用如在化學或物理氣相沉積之後的遮罩(masking)、電化學或無電鍍之後的遮罩、遮罩和浸泡(dipping)、印刷(printing)或分配(dispensing)之製程來進行沉積。
用於例示,蝕刻遮罩316係顯示以一端平坦而另一端彎曲的形狀覆蓋未處理引線318之一部分,但應了解到,這只是範例,蝕刻遮罩316之形狀可以不同。舉例而言,蝕刻遮罩316可以是半圓形、三角形或其他的形狀,而蝕刻遮罩316的邊緣可為波浪而非直線。
晶粒墊102係顯示為未連接至引線架314之其他部分,但應了解到,此細節已被省略以求清楚。晶粒墊102可例如經由聯接棒(tie bar)或阻擋棒(dam bar)被連接至引線架314之其他部分。晶粒墊102係顯示為不具有任何未遮罩部份320,但若該晶粒墊102上期望有可側焊特徵,則該晶粒墊102可具有未遮罩部份320。
現在參照第4圖,其中顯示由第3圖之虛線矩形4所繪之插圖內的第3圖之細節圖。在此圖中,可以看到具有未遮罩部份320和蝕刻遮罩316之未處理引線318的細節。蝕刻遮罩316可被選擇性沉積在未處理引線318的頂部上,使未處理引線318的未遮罩部分320暴露出來。
現在參照第5圖,其中顯示,在製造之包覆階段中,由第3圖之虛線矩形5所繪之插圖內的第3圖之未處理引線318的等角俯視圖。在此圖中,封裝件主體104
已被鋪設成覆蓋第3圖中大部分的引線架314,同時使未處理引線318與晶粒墊102的頂部暴露出來。雖然不可見,但積體電路晶粒(未圖示)係安裝在晶粒墊102上並在包覆之前電性連接至未處理引線318。
封裝件主體104可被模製在積體電路晶粒和引線架314上,使得封裝件主體104與未處理引線318和晶粒墊102之表面共平面。在其他部分的未處理引線318被嵌埋在封裝件主體104中的情況下,未處理引線318的頂部表面能被暴露出來。在未處理引線318的頂部表面上從封裝件主體104暴露出來的是蝕刻遮罩316和未遮罩部份320。此包覆步驟能藉由例如射出成形(injection molding)、加壓成形(compression molding)或薄膜輔助成形(film assist molding)之製程來進行。
封裝件主體104被描述為在選擇性鋪設蝕刻遮罩316之後被模製在引線架314上,但應了解到可修改製程。例如,封裝件主體104能先模製在引線架314和積體電路晶粒上,然後選擇性鋪設蝕刻遮罩316在引線架314之暴露部分。
現在參照第6圖,其中顯示在製造之蝕刻階段中第5圖之結構。第3圖之未處理引線318已被蝕刻,而蝕刻遮罩316之一部分已被移除。
經過蝕刻製程,第4圖之未遮罩部分320將從頂部表面向下被移除。例如,等向性蝕刻製程將朝所有方向等速蝕刻,並且當蝕刻劑侵入形成之溝槽的側壁中
時,將在蝕刻遮罩316之一部分之下蝕刻。此蝕刻製程將形成彎曲凹部,而蝕刻遮罩316會在溝槽112上方留下懸伸物(overhang)或懸吊件(dangling piece),若電鍍用作為蝕刻遮罩316則有時稱作「狗耳電鍍(dog ear plating)」。蝕刻劑的選擇係在於蝕刻至未遮罩部分320中而不破壞封裝件主體104或蝕刻遮罩316。例如,未遮罩部份320在未處理引線318邊緣意指溝槽112也在引線之邊緣,在一個邊緣靠著封裝件主體104而另一邊緣(在移除懸伸物之前)在蝕刻遮罩316之懸伸物之下的情況下。
蝕刻製程可被控制成蝕刻穿過大約未處理引線318的半個高度,形成彎曲形狀的溝槽112。在蝕刻步驟之後,移除蝕刻遮罩316之懸伸件。例如,能使用高壓去膠製程移除懸伸物。這造成溝槽112在從頂部觀看時會比未遮罩部分320之原始尺寸還大,因為蝕刻遮罩316被部份移除。在移除懸伸物之後,蝕刻遮罩316之表面積會變得較小。
已發現到,利用蝕刻遮罩316經由蝕刻製程而形成的溝槽112會改善整體連接性。由於溝槽112的形成沒有使用到任何鋸切,所以不會有毛邊產生,而由於毛邊形成是鋸切過程的自然結果,所以在這裡不會有可靠性降低的問題。此外,在從蝕刻製程(不像鋸切製程)形成溝槽112期間,在未處理引線318上不會有物理應力,這也改善了可靠性。
也發現到,在未處理引線318上選擇性鋪設
蝕刻遮罩316會提供溝槽設計彈性。因為溝槽112具有選擇性鋪設蝕刻遮罩316之後的形狀,其可被圖案化成幾乎任何合理的形狀,溝槽112可被設計成相較於鋸切溝槽112有較多的形狀數目。此較大彈性能例如允許表面積的數量增加,以用於稍後的焊錫鋪設和較佳的連接。
已發現到,相較於鋸切製程,在蝕刻製程之後選擇性鋪設蝕刻遮罩316,會對於溝槽112之尺寸提供較佳的控制。所有製程都會有某些誤差,但因為蝕刻製程能比鋸切更緊密地受到控制,所以誤差的容限會較小,導致溝槽112之尺寸會有較少的浪費、較佳的彈性以及較佳的控制。
現在參照第7圖,其中顯示在製造之電鍍階段中第6圖的結構。電鍍階段在蝕刻階段以及移除第3圖之蝕刻遮罩316之後。
蝕刻遮罩316可被完全移除以便製備用於電鍍的可側焊引線106和晶粒墊102。在移除蝕刻遮罩316之懸伸物之後,剩餘的蝕刻遮罩316可用乾拋(dry buffing)製程移除,其也可用來平坦化表面。用來移除蝕刻遮罩316之懸伸物和其餘部分的一種替代製程係用剝除電鍍之後進行的化學去膠來取代高壓去膠。另一種替代製程係用單一乾拋製程移除蝕刻遮罩316之懸伸物和蝕刻遮罩316之其餘部分二者。另一種可能作法是不用另外的去膠步驟而是經由例如化學機械平坦化(CMP)來剝除電鍍,化學機械平坦化能執行去膠功能同時也能移除蝕刻遮罩。
一旦蝕刻遮罩316被移除,可側焊引線106之所有特徵,包含溝槽112、以及從封裝件主體104之頂部暴露之晶粒墊102係利用電鍍製程(例如電鍍、無電鍍、電化學電鍍、印刷、濺鍍或某種形式的氣相沉積)以電鍍108覆蓋。舉例而言,可側焊引線106可具有電鍍108直接沉積在溝槽112之裸金屬上和可側焊引線106之上方表面上。
用於例示,電鍍108係顯示為從封裝件主體104之表面明顯升起,但應了解這僅是視覺效果。電鍍108能以各種厚度鋪設,並且不限於任何特定厚度。厚度的選擇可以視電鍍108的組成物而定。
已發現到,在可側焊引線106之裸金屬上沉積電鍍108會導致較佳的焊錫連接。在可側焊引線106之銅上直接沉積電鍍108允許電鍍108和可側焊引線106之間較佳的接合,這能改善焊錫連接的強度。例如,有可能在層與層之間發生脫層的點變少會增加可靠性和改善連接強度。
現在參照第8圖,其中顯示在製造之切單(singulation)階段中第7圖之結構。在電鍍108已沉積或鋪設在可側焊引線106和晶粒墊102上之後,積體電路封裝系統100能藉由在可側焊引線106的列與列之間進行切割的切單製程形成。切單製程能在積體電路封裝系統100之側暴露可側焊引線106的無電鍍部分110。
現在參照第9圖,其中顯示在本發明之另一
實施例中製造積體電路封裝系統之方法900的流程圖。方法900包含:在方塊902中,提供具有未處理引線的引線架;在方塊904中,沉積蝕刻遮罩在該未處理引線之頂部表面上,該未處理引線具有該蝕刻遮罩與該頂部表面之未遮罩部分;在方塊906中,連接積體電路晶粒至未處理引線;在方塊908中,以封裝件主體包覆該引線架,該未處理引線之該頂部表面從該封裝件主體暴露出來;在方塊910中,形成可側焊引線包含形成溝槽在該未處理引線中,該蝕刻遮罩在該溝槽上方具有懸伸物;在方塊912中,移除該蝕刻遮罩;以及在方塊914中,沉積電鍍在該可側焊引線上。
因此,已發現到本發明之積體電路封裝系統提供重要且迄今未之而不可得的解決方案、性能和用於可靠製造QFN封裝件的功能性態樣。
所得到之方法、製程、設備、裝置、產品及/或系統是直接的、具成本效益的、不複雜的、高度多樣性、準確、敏感且有效的,能夠藉由採用已知組件實施,因而能適於有效率且經濟地製造、應用程式和用途。
本發明之另一重要態樣係在於其有價值地支持和提供降低成本、簡化系統以及增加效能的歷史趨勢。
本發明之這些和其它有價值的態樣因此將技術狀態帶到至少下一層次。
雖然本發明已結合特定最佳模式加以描述,但應了解到,對本技術領域中具有通常知識者而言,配合
先前描述顯然可知本發明有許多替代、修改和變化者。目前為止,在此所提出或在隨附圖式中所顯示之所有事項係應被視為例示性而非限制性的涵義。
900‧‧‧方法
902、904、906、908、910、912、914‧‧‧方塊
Claims (10)
- 一種積體電路封裝系統之製造方法,包括:提供具有未處理引線的引線架;在該未處理引線之頂部表面上沉積蝕刻遮罩,該未處理引線具有該蝕刻遮罩與該頂部表面之未遮罩部分;連接積體電路晶粒至該未處理引線;以封裝件主體包覆該引線架,該未處理引線之該頂部表面從該封裝件主體暴露出來;形成可側焊引線,包含形成溝槽在該未處理引線中,該溝槽形成在該蝕刻遮罩之一部分之下包含在該溝槽上方形成該蝕刻遮罩之懸伸物;移除該蝕刻遮罩;以及沉積電鍍在該可側焊引線上。
- 如申請專利範圍第1項所述之方法,其中,移除該蝕刻遮罩包含應用乾拋製程於該蝕刻遮罩,用以移除該懸伸物和該蝕刻遮罩之其餘部分。
- 如申請專利範圍第1項所述之方法,其中,移除該蝕刻遮罩包含:應用高壓去膠製程於該懸伸物;以及應用乾拋製程於該蝕刻遮罩。
- 如申請專利範圍第1項所述之方法,其中,移除該蝕刻遮罩包含:應用化學去膠製程於該懸伸物與該頂部表面;以及剝除該蝕刻遮罩。
- 如申請專利範圍第1項所述之方法,其中,移除該蝕刻遮罩包含應用化學機械平坦化製程於該蝕刻遮罩。
- 一種積體電路封裝系統之製造方法,包括:提供具有未處理引線的引線架;在該未處理引線之頂部表面上沉積蝕刻遮罩,該未處理引線具有該蝕刻遮罩與該頂部表面之未遮罩部分;連接積體電路晶粒至該未處理引線;以封裝件主體包覆該引線架及該積體電路晶粒,該未處理引線之該頂部表面從該封裝件主體暴露出來;蝕刻穿過該頂部表面之該未遮罩部分以從該未處理引線形成可側焊引線包含形成溝槽在該未處理引線中,該溝槽形成在該蝕刻遮罩之一部分之下包含在該溝槽上方形成該蝕刻遮罩之懸伸物;移除該蝕刻遮罩;以及沉積電鍍在該可側焊引線上。
- 如申請專利範圍第6項所述之方法,其中,提供該引線架包含提供具有晶粒墊的該引線架。
- 如申請專利範圍第6項所述之方法,其中,在頂部表面上沉積該蝕刻遮罩包含在該頂部表面之邊緣處沉積具有該未遮罩部分的該蝕刻遮罩。
- 如申請專利範圍第6項所述之方法,其中,蝕刻穿過該頂部表面之該未遮罩部分包含應用等向性蝕刻製程。
- 如申請專利範圍第6項所述之方法,其中,以該封裝件主體包覆包含包覆該積體電路晶粒。
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US9048228B2 (en) * | 2013-09-26 | 2015-06-02 | Stats Chippac Ltd. | Integrated circuit packaging system with side solderable leads and method of manufacture thereof |
US10892211B2 (en) | 2017-08-09 | 2021-01-12 | Semtech Corporation | Side-solderable leadless package |
CN109243988A (zh) * | 2018-09-14 | 2019-01-18 | 上海凯虹科技电子有限公司 | 封装体及其封装方法 |
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US6611047B2 (en) | 2001-10-12 | 2003-08-26 | Amkor Technology, Inc. | Semiconductor package with singulation crease |
US6608366B1 (en) | 2002-04-15 | 2003-08-19 | Harry J. Fogelson | Lead frame with plated end leads |
US6872599B1 (en) | 2002-12-10 | 2005-03-29 | National Semiconductor Corporation | Enhanced solder joint strength and ease of inspection of leadless leadframe package (LLP) |
US7195953B2 (en) | 2003-04-02 | 2007-03-27 | Yamaha Corporation | Method of manufacturing a semiconductor package using a lead frame having through holes or hollows therein |
JP4141340B2 (ja) | 2003-07-16 | 2008-08-27 | 三洋電機株式会社 | 半導体装置の製造方法 |
JP3789443B2 (ja) | 2003-09-01 | 2006-06-21 | Necエレクトロニクス株式会社 | 樹脂封止型半導体装置 |
JP3994095B2 (ja) * | 2004-06-23 | 2007-10-17 | ローム株式会社 | 面実装型電子部品 |
JP5285289B2 (ja) * | 2008-02-06 | 2013-09-11 | セミコンダクター・コンポーネンツ・インダストリーズ・リミテッド・ライアビリティ・カンパニー | 回路装置およびその製造方法 |
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US8709870B2 (en) | 2009-08-06 | 2014-04-29 | Maxim Integrated Products, Inc. | Method of forming solderable side-surface terminals of quad no-lead frame (QFN) integrated circuit packages |
US8329509B2 (en) | 2010-04-01 | 2012-12-11 | Freescale Semiconductor, Inc. | Packaging process to create wettable lead flank during board assembly |
US8642461B2 (en) * | 2010-08-09 | 2014-02-04 | Maxim Integrated Products, Inc. | Side wettable plating for semiconductor chip package |
US8076181B1 (en) * | 2010-10-22 | 2011-12-13 | Linear Technology Corporation | Lead plating technique for singulated IC packages |
US8569112B2 (en) * | 2012-03-20 | 2013-10-29 | Stats Chippac Ltd. | Integrated circuit packaging system with encapsulation and leadframe etching and method of manufacture thereof |
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SG10201401158WA (en) | 2014-12-30 |
TWI606525B (zh) | 2017-11-21 |
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