JP5285289B2 - 回路装置およびその製造方法 - Google Patents
回路装置およびその製造方法 Download PDFInfo
- Publication number
- JP5285289B2 JP5285289B2 JP2008025929A JP2008025929A JP5285289B2 JP 5285289 B2 JP5285289 B2 JP 5285289B2 JP 2008025929 A JP2008025929 A JP 2008025929A JP 2008025929 A JP2008025929 A JP 2008025929A JP 5285289 B2 JP5285289 B2 JP 5285289B2
- Authority
- JP
- Japan
- Prior art keywords
- lead
- circuit device
- sealing resin
- lead frame
- tie bar
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Images
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
- H01L24/93—Batch processes
- H01L24/95—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
- H01L24/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48245—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic
- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/49—Structure, shape, material or disposition of the wire connectors after the connecting process of a plurality of wire connectors
- H01L2224/491—Disposition
- H01L2224/4912—Layout
- H01L2224/49171—Fan-out arrangements
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/013—Alloys
- H01L2924/0132—Binary Alloys
- H01L2924/01322—Eutectic Alloys, i.e. obtained by a liquid transforming into two solid phases
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/06—Polymers
- H01L2924/078—Adhesive characteristics other than chemical
- H01L2924/07802—Adhesive characteristics other than chemical not being an ohmic electrical conductor
Landscapes
- Engineering & Computer Science (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Lead Frames For Integrated Circuits (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
5(B)参照)、この接着シート48は予め除去されても良いし、そのままリードフレーム10と共にダイシングシート42に貼着されても良い。ここで、リードフレーム10は、封止樹脂36が形成された面が貼着されても良いし、封止樹脂36が形成された面に対向する面が貼着されても良い。
6 ロウ材
7 導電路
8 実装基板
10 リードフレーム
12 ブロック
14 第1支持部
16 第2支持部
18 分割線
20 分割線
22 ハーフ溝
24 貫通溝
26 ユニット
28 アイランド
29 吊りリード
30 リード
32 タイバー
34 貫通孔
36 封止樹脂
38 金属枠
40 ダイシングブレード
42 ダイシングシート
44 半導体素子
46 金属細線
48 接着シート
50 金型
52 上金型
54 下金型
56 キャビティ
60 ゲート
58 エアベント
Claims (7)
- 回路素子と、前記回路素子と電気的に接続されて一部が外部に露出するリードと、前記リードの下面および側面が外部に露出した状態で前記回路素子および前記リードを一体的に被覆する封止樹脂とを備え、
前記リードは、前記封止樹脂の内部から周辺部に向かって裾広がりの形状を有し、
前記リードの幅が最大である箇所で、前記リードの側面が前記封止樹脂から外部に露出することを特徴とする回路装置。 - 前記封止樹脂から露出する前記リードの下面および側面にロウ材が付着されることを特徴とする請求項1に記載の回路装置。
- 前記回路素子は半導体素子であり、
前記リードは、前記半導体素子を取り囲むように複数が配置されると共に、金属細線を経由して前記半導体素子の電極と電気的に接続されることを特徴とする請求項1または請求項2に記載の回路装置。 - 回路素子と電気的に接続される複数のリードから成るユニットが配置され、前記ユニットを囲むタイバーにより前記リードが連結されると共に、前記リードと前記タイバーとの連結部が他の領域の前記リードよりも太く形成されたリードフレームを用意する工程と、
前記各ユニットに回路素子を配置すると共に、前記回路素子と前記リードとを電気的に接続する工程と、
前記リードの裏面が露出された状態で、前記リードおよび前記回路素子が被覆されるように封止樹脂を形成する工程と、
前記ユニット同士の境界にて前記封止樹脂を分離すると共に、前記タイバーを除去することにより、分離された前記封止樹脂の側面から、前記リードの幅が最大である箇所で、前記リードの側面を露出させる工程と、
を具備することを特徴とする回路装置の製造方法。 - 前記リードが前記タイバーに連結される箇所では、前記リードの幅は、前記ユニットの内側から外側に向かって裾広がりの形状を有することを特徴とする請求項4に記載の回路装置の製造方法。
- 前記タイバーの幅は、前記封止樹脂のダイシングに用いられるダイシングソーの幅よりも狭いことを特徴とする請求項4または請求項5に記載の回路装置の製造方法。
- 前記ユニットは、中央部に設けられるアイランドと前記アイランドを取り囲むように配置された複数の前記リードから構成され、
前記回路素子は前記アイランドに固着される半導体素子であり、前記半導体素子と前記リードとは金属細線を経由して接続されることを特徴とする請求項4から請求項6の何れかに記載の回路装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008025929A JP5285289B2 (ja) | 2008-02-06 | 2008-02-06 | 回路装置およびその製造方法 |
TW097146557A TWI408783B (zh) | 2008-02-06 | 2008-12-01 | 電路裝置及其製造方法 |
KR1020080127213A KR101132529B1 (ko) | 2008-02-06 | 2008-12-15 | 회로 장치 및 그 제조 방법 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2008025929A JP5285289B2 (ja) | 2008-02-06 | 2008-02-06 | 回路装置およびその製造方法 |
Publications (3)
Publication Number | Publication Date |
---|---|
JP2009188149A JP2009188149A (ja) | 2009-08-20 |
JP2009188149A5 JP2009188149A5 (ja) | 2011-05-19 |
JP5285289B2 true JP5285289B2 (ja) | 2013-09-11 |
Family
ID=41071115
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP2008025929A Active JP5285289B2 (ja) | 2008-02-06 | 2008-02-06 | 回路装置およびその製造方法 |
Country Status (3)
Country | Link |
---|---|
JP (1) | JP5285289B2 (ja) |
KR (1) | KR101132529B1 (ja) |
TW (1) | TWI408783B (ja) |
Families Citing this family (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US8809119B1 (en) * | 2013-05-17 | 2014-08-19 | Stats Chippac Ltd. | Integrated circuit packaging system with plated leads and method of manufacture thereof |
JP6946870B2 (ja) * | 2017-09-04 | 2021-10-13 | 大日本印刷株式会社 | リードフレーム、半導体装置、および半導体装置の製造方法 |
Family Cites Families (15)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5617459A (en) * | 1979-07-23 | 1981-02-19 | Nec Corp | Information processor |
JPS60206156A (ja) * | 1984-03-30 | 1985-10-17 | Nec Corp | 半導体装置およびその製造方法 |
JPS61144834A (ja) * | 1984-12-18 | 1986-07-02 | Toshiba Corp | 樹脂封止型半導体装置 |
JPS63104457A (ja) * | 1986-10-22 | 1988-05-09 | Hitachi Ltd | リ−ドフレ−ム |
JPH06268140A (ja) * | 1991-02-19 | 1994-09-22 | Hitachi Ltd | 半導体装置およびそれに使用されるリードフレーム |
KR0160146B1 (ko) * | 1992-07-06 | 1998-12-01 | 조희재 | 반도체용 리드 프레임 |
JP3286765B2 (ja) * | 1993-03-09 | 2002-05-27 | 株式会社日立製作所 | 半導体装置 |
US6143981A (en) | 1998-06-24 | 2000-11-07 | Amkor Technology, Inc. | Plastic integrated circuit package and method and leadframe for making the package |
NL1011929C2 (nl) * | 1999-04-29 | 2000-10-31 | 3P Licensing Bv | Werkwijze voor het inkapselen van elektronische componenten, in het bijzonder geintegreerde schakelingen. |
JP2001077232A (ja) * | 1999-09-06 | 2001-03-23 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP3547704B2 (ja) * | 2000-06-22 | 2004-07-28 | 株式会社三井ハイテック | リードフレーム及び半導体装置 |
JP4507452B2 (ja) * | 2001-05-17 | 2010-07-21 | パナソニック株式会社 | 電子部品、その製造方法及び電子回路装置 |
JP2004200243A (ja) * | 2002-12-16 | 2004-07-15 | Kyocera Corp | 半導体素子収納用パッケージおよび半導体装置 |
JP2005166695A (ja) | 2003-11-28 | 2005-06-23 | Mitsui High Tec Inc | リードフレーム及び半導体装置の製造方法 |
JP2006165411A (ja) * | 2004-12-10 | 2006-06-22 | New Japan Radio Co Ltd | 半導体装置およびその製造方法 |
-
2008
- 2008-02-06 JP JP2008025929A patent/JP5285289B2/ja active Active
- 2008-12-01 TW TW097146557A patent/TWI408783B/zh not_active IP Right Cessation
- 2008-12-15 KR KR1020080127213A patent/KR101132529B1/ko not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR20090086147A (ko) | 2009-08-11 |
KR101132529B1 (ko) | 2012-04-02 |
TWI408783B (zh) | 2013-09-11 |
TW200939432A (en) | 2009-09-16 |
JP2009188149A (ja) | 2009-08-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
US10312171B2 (en) | Semiconductor device | |
JP5634033B2 (ja) | 樹脂封止型半導体装置とその製造方法 | |
KR101160694B1 (ko) | 반도체장치의 제조 방법 | |
KR100859624B1 (ko) | 반도체 장치의 제조 방법 | |
JP2011077278A (ja) | 半導体装置およびその製造方法 | |
JP5144294B2 (ja) | リードフレームおよびそれを用いた回路装置の製造方法 | |
US9331041B2 (en) | Semiconductor device and semiconductor device manufacturing method | |
US8609467B2 (en) | Lead frame and method for manufacturing circuit device using the same | |
JP2010087129A (ja) | 回路装置およびその製造方法 | |
US8829685B2 (en) | Circuit device having funnel shaped lead and method for manufacturing the same | |
JP5285289B2 (ja) | 回路装置およびその製造方法 | |
JPH11330314A (ja) | 半導体装置の製造方法及びその構造、該方法に用いるリードフレーム | |
JP4784945B2 (ja) | 半導体装置の製造方法 | |
JP2011035142A (ja) | 回路装置の製造方法 | |
JP2008166621A (ja) | 半導体装置およびその製造方法 | |
JP2009188147A (ja) | 回路装置の製造方法 | |
JP2005116687A (ja) | リードフレーム、半導体装置及び半導体装置の製造方法 | |
JP4079874B2 (ja) | 半導体装置の製造方法 | |
JP2003046053A (ja) | 半導体装置およびその製造方法 | |
JP2011091146A (ja) | 半導体装置の製造方法 | |
JP4597118B2 (ja) | 半導体装置の製造方法 | |
JP2012164799A (ja) | 半導体装置及びその製造方法 | |
JP2015029143A (ja) | 樹脂封止型半導体装置とその製造方法、リードフレーム | |
JP2006049398A (ja) | 樹脂封止型半導体装置の製造方法、そのための封止金型、およびリードフレーム | |
US20180096953A1 (en) | Molded lead frame device |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
A621 | Written request for application examination |
Free format text: JAPANESE INTERMEDIATE CODE: A621 Effective date: 20110127 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20110405 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20110602 |
|
A977 | Report on retrieval |
Free format text: JAPANESE INTERMEDIATE CODE: A971007 Effective date: 20120626 |
|
A131 | Notification of reasons for refusal |
Free format text: JAPANESE INTERMEDIATE CODE: A131 Effective date: 20120703 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20121001 |
|
A711 | Notification of change in applicant |
Free format text: JAPANESE INTERMEDIATE CODE: A711 Effective date: 20130215 |
|
A521 | Request for written amendment filed |
Free format text: JAPANESE INTERMEDIATE CODE: A523 Effective date: 20130405 |
|
TRDD | Decision of grant or rejection written | ||
A01 | Written decision to grant a patent or to grant a registration (utility model) |
Free format text: JAPANESE INTERMEDIATE CODE: A01 Effective date: 20130507 |
|
A61 | First payment of annual fees (during grant procedure) |
Free format text: JAPANESE INTERMEDIATE CODE: A61 Effective date: 20130531 |
|
R150 | Certificate of patent or registration of utility model |
Ref document number: 5285289 Country of ref document: JP Free format text: JAPANESE INTERMEDIATE CODE: R150 |
|
RD04 | Notification of resignation of power of attorney |
Free format text: JAPANESE INTERMEDIATE CODE: R3D04 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |
|
R250 | Receipt of annual fees |
Free format text: JAPANESE INTERMEDIATE CODE: R250 |