JP4079874B2 - 半導体装置の製造方法 - Google Patents
半導体装置の製造方法 Download PDFInfo
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- JP4079874B2 JP4079874B2 JP2003430438A JP2003430438A JP4079874B2 JP 4079874 B2 JP4079874 B2 JP 4079874B2 JP 2003430438 A JP2003430438 A JP 2003430438A JP 2003430438 A JP2003430438 A JP 2003430438A JP 4079874 B2 JP4079874 B2 JP 4079874B2
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- 239000004065 semiconductor Substances 0.000 title claims description 92
- 238000004519 manufacturing process Methods 0.000 title claims description 31
- 238000007789 sealing Methods 0.000 claims description 70
- 238000000034 method Methods 0.000 claims description 50
- 239000011347 resin Substances 0.000 claims description 47
- 229920005989 resin Polymers 0.000 claims description 47
- 238000004080 punching Methods 0.000 claims description 20
- 239000011159 matrix material Substances 0.000 claims description 16
- 238000005520 cutting process Methods 0.000 claims description 5
- 239000000463 material Substances 0.000 description 14
- 239000000853 adhesive Substances 0.000 description 8
- 230000001070 adhesive effect Effects 0.000 description 8
- 238000010586 diagram Methods 0.000 description 7
- 239000004020 conductor Substances 0.000 description 5
- 239000002390 adhesive tape Substances 0.000 description 4
- 239000002184 metal Substances 0.000 description 3
- 229910052751 metal Inorganic materials 0.000 description 3
- 239000000758 substrate Substances 0.000 description 3
- 238000012790 confirmation Methods 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 239000004642 Polyimide Substances 0.000 description 1
- 230000002411 adverse Effects 0.000 description 1
- 230000015572 biosynthetic process Effects 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- 238000005530 etching Methods 0.000 description 1
- 230000001771 impaired effect Effects 0.000 description 1
- 238000002347 injection Methods 0.000 description 1
- 239000007924 injection Substances 0.000 description 1
- 239000012212 insulator Substances 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 238000000465 moulding Methods 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
- 229920001721 polyimide Polymers 0.000 description 1
- 229910000679 solder Inorganic materials 0.000 description 1
- 239000000725 suspension Substances 0.000 description 1
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- H—ELECTRICITY
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- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
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- H01L21/48—Manufacture or treatment of parts, e.g. containers, prior to assembly of the devices, using processes not provided for in a single one of the subgroups H01L21/06 - H01L21/326
- H01L21/4814—Conductive parts
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- H01L2224/32151—Disposition the layer connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
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- H01L2224/48247—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being metallic connecting the wire to a bond pad of the item
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- H01L2224/732—Location after the connecting process
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- H01L2224/97—Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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- H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
- H01L23/495—Lead-frames or other flat leads
- H01L23/49503—Lead-frames or other flat leads characterised by the die pad
- H01L23/49513—Lead-frames or other flat leads characterised by the die pad having bonding material between chip and die pad
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- H01L24/42—Wire connectors; Manufacturing methods related thereto
- H01L24/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L24/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
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- Manufacturing & Machinery (AREA)
- Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
Description
先ず、図4を参照して、この発明の半導体装置の製造方法に適用して好適なマトリクスリードフレームの構造について説明する。
換言すると、支持リード29は、第1及び第2の辺28a及び28bに沿う方向、すなわち列方向に延在している。
この発明の半導体装置の製造方法について、図1及び図2を参照して説明する。
図3(A)、(B)及び(C)を参照して、図1、図2及び図4を参照して説明した製造方法により製造される半導体装置の構成につき説明する。
20:リードフレーム
21:フレーム部
22:スプロケットホール
23:連結部(支持部)
25:パンチ領域
25a:第1パンチ領域
25b:第2パンチ領域
26:リード(外部端子)
27:接着材
28:ダイパッド(チップ搭載部)
28a:第1の辺
28b:第2の辺
28c、28d:対向辺(直交辺)
29:支持リード
30:封止樹脂ブロック列
30a:封止樹脂ブロック
31:封止部
31a:上面
31b:側面
31c:端面
31d:外部端子間封止部
31e:底面
32:ダミー樹脂封止ブロック領域(ダミーチップ搭載領域)
34:ダミー行領域
42:半導体チップ
42a:第1の主表面
42b:第2の主表面
44:電極パッド
46:ボンディングワイヤ
50:金型
50a:上部金型
50b:下部金型
52:凹部(キャビティ)
54:間隙部
54a:表面
Claims (3)
- (1)長尺のリードフレームであって、マトリクス状に設けられていて、前記長尺方向に直交する列方向に延在している第1の辺及び該第1の辺と対向する第2の辺を有している複数のチップ搭載部と、前記リードフレームの長尺方向に沿う行方向に設定されており、複数の前記チップ搭載部のうちの一部を含むダミー行領域と、複数の前記チップ搭載部を離間して囲むフレーム部と、前記列方向に延在しており、該フレーム部及び前記チップ搭載部間を接続するとともに、隣接する前記チップ搭載部同士間を接続して、前記チップ搭載部を支持する支持リードと、前記第1及び第2の辺側で隣接する複数の前記チップ搭載部同士の間に前記チップ搭載部とは離間して設けられている連結部と、前記第1及び第2の辺に対向する前記連結部及び前記フレーム部から、前記第1及び第2の辺に向かって延在する複数のリードとを有する前記リードフレームを準備する工程と、
(2)前記ダミー行領域の複数の前記チップ搭載部を除く、複数の前記チップ搭載部に、電極パッドを有する複数個の半導体チップを搭載し、前記電極パッド及び前記リードをボンディングワイヤにより電気的に接続する工程と、
(3)マトリクス状に設けられている複数個の前記半導体チップのうち、前記列方向に並ぶ複数個の前記半導体チップを格納するキャビティを画成するモールド型を準備する工程と、
(4)前記キャビティ内に前記列を構成する複数個の半導体チップを格納して樹脂封止を行った後、前記モールド型を取り外して、複数の封止樹脂ブロックからなる封止樹脂ブロック列を形成する工程と、
(5)複数の前記封止樹脂ブロックの外周のうち、前記ダミー行領域を除き、前記リードが設けられている側の外周に沿ってパンチ加工して、前記リードを前記フレーム部及び連結部から切り離す工程と、
(6)前記封止樹脂ブロック中の前記支持リードをダイシングにより切断して、個片化する工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記(5)工程は、前記フレーム部及び連結部に、前記リードフレームの延在方向に沿って複数が互いに平行に延在して設けられている前記リードに対して直交する方向にパンチ加工する工程であり、
前記(6)工程は、前記リードの延在方向に沿ってダイシングして、個片化する工程である
ことを特徴とする請求項1に記載の半導体装置の製造方法。 - 前記(5)工程は、前記ダミー行領域の幅に等しい空隙部を有する分割されている直線状ブレードを使用し、前記空隙部を前記ダミー行領域に対応させて、当該ダミー行領域を除き、パンチ加工を行う工程であることを特徴とする請求項2に記載の半導体装置の製造方法。
Priority Applications (3)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2003430438A JP4079874B2 (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
US10/942,799 US7402502B2 (en) | 2003-12-25 | 2004-09-17 | Method of manufacturing a semiconductor device by using a matrix frame |
CNB2004100803707A CN100411120C (zh) | 2003-12-25 | 2004-09-29 | 通过使用一个矩阵框架来制造一个半导体装置的方法 |
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JP2003430438A JP4079874B2 (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
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JP2005191258A JP2005191258A (ja) | 2005-07-14 |
JP4079874B2 true JP4079874B2 (ja) | 2008-04-23 |
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JP2003430438A Expired - Fee Related JP4079874B2 (ja) | 2003-12-25 | 2003-12-25 | 半導体装置の製造方法 |
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US (1) | US7402502B2 (ja) |
JP (1) | JP4079874B2 (ja) |
CN (1) | CN100411120C (ja) |
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CN1774965A (zh) * | 2004-03-30 | 2006-05-17 | 松下电器产业株式会社 | 模块元件及其制造方法 |
US20070132075A1 (en) * | 2005-12-12 | 2007-06-14 | Mutsumi Masumoto | Structure and method for thin single or multichip semiconductor QFN packages |
US7877284B2 (en) * | 2006-06-05 | 2011-01-25 | International Business Machines Corporation | Method and system for developing an accurate skills inventory using data from delivery operations |
JP2015177080A (ja) * | 2014-03-15 | 2015-10-05 | 新日本無線株式会社 | リード内蔵型回路パッケージ及びその製造方法 |
US20210043466A1 (en) * | 2019-08-06 | 2021-02-11 | Texas Instruments Incorporated | Universal semiconductor package molds |
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US5355017A (en) * | 1990-04-06 | 1994-10-11 | Sumitomo Special Metal Co. Ltd. | Lead frame having a die pad with metal foil layers attached to the surfaces |
US6465743B1 (en) * | 1994-12-05 | 2002-10-15 | Motorola, Inc. | Multi-strand substrate for ball-grid array assemblies and method |
JP3892139B2 (ja) * | 1998-03-27 | 2007-03-14 | 株式会社ルネサステクノロジ | 半導体装置 |
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-
2003
- 2003-12-25 JP JP2003430438A patent/JP4079874B2/ja not_active Expired - Fee Related
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2004
- 2004-09-17 US US10/942,799 patent/US7402502B2/en not_active Expired - Fee Related
- 2004-09-29 CN CNB2004100803707A patent/CN100411120C/zh not_active Expired - Fee Related
Also Published As
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CN100411120C (zh) | 2008-08-13 |
JP2005191258A (ja) | 2005-07-14 |
US7402502B2 (en) | 2008-07-22 |
CN1638069A (zh) | 2005-07-13 |
US20050142814A1 (en) | 2005-06-30 |
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