JP3805338B2 - 半導体装置及びその製造方法 - Google Patents
半導体装置及びその製造方法 Download PDFInfo
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- JP3805338B2 JP3805338B2 JP2003378201A JP2003378201A JP3805338B2 JP 3805338 B2 JP3805338 B2 JP 3805338B2 JP 2003378201 A JP2003378201 A JP 2003378201A JP 2003378201 A JP2003378201 A JP 2003378201A JP 3805338 B2 JP3805338 B2 JP 3805338B2
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- semiconductor device
- lead frames
- external terminal
- semiconductor chip
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- 239000004065 semiconductor Substances 0.000 title claims description 190
- 238000004519 manufacturing process Methods 0.000 title claims description 63
- 238000007789 sealing Methods 0.000 claims description 77
- 238000000034 method Methods 0.000 claims description 63
- 239000000853 adhesive Substances 0.000 claims description 13
- 230000001070 adhesive effect Effects 0.000 claims description 13
- 239000000463 material Substances 0.000 claims description 12
- 238000005520 cutting process Methods 0.000 claims description 6
- 238000010586 diagram Methods 0.000 description 19
- 239000011347 resin Substances 0.000 description 9
- 229920005989 resin Polymers 0.000 description 9
- 239000004020 conductor Substances 0.000 description 8
- 238000003825 pressing Methods 0.000 description 3
- KDLHZDBZIXYQEI-UHFFFAOYSA-N Palladium Chemical compound [Pd] KDLHZDBZIXYQEI-UHFFFAOYSA-N 0.000 description 2
- 230000000694 effects Effects 0.000 description 2
- 239000012212 insulator Substances 0.000 description 2
- 239000000758 substrate Substances 0.000 description 2
- RYGMFSIKBFXOCR-UHFFFAOYSA-N Copper Chemical compound [Cu] RYGMFSIKBFXOCR-UHFFFAOYSA-N 0.000 description 1
- 229910000881 Cu alloy Inorganic materials 0.000 description 1
- 239000002390 adhesive tape Substances 0.000 description 1
- 239000000470 constituent Substances 0.000 description 1
- 238000007796 conventional method Methods 0.000 description 1
- 229910052802 copper Inorganic materials 0.000 description 1
- 239000010949 copper Substances 0.000 description 1
- PCHJSUWPFVWCPO-UHFFFAOYSA-N gold Chemical compound [Au] PCHJSUWPFVWCPO-UHFFFAOYSA-N 0.000 description 1
- 239000010931 gold Substances 0.000 description 1
- 229910052737 gold Inorganic materials 0.000 description 1
- 239000007788 liquid Substances 0.000 description 1
- 239000007769 metal material Substances 0.000 description 1
- 229910052763 palladium Inorganic materials 0.000 description 1
- 230000002093 peripheral effect Effects 0.000 description 1
- 238000007747 plating Methods 0.000 description 1
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Description
1−1.半導体装置の製造方法
この発明の第1の実施の形態の半導体装置の製造方法について、図2から図4を参照して説明する。
図5(A)、(B)及び(C)を参照して、図2から図4を参照して説明した第1の実施の形態の製造方法により製造される半導体装置の構成につき説明する。
2−1.半導体装置の製造方法
この発明の第2の実施の形態の半導体装置の製造方法について、図6を参照して説明する。なお、この実施の形態の半導体装置の製造方法及びこの製造方法により製造される半導体装置が、第1の実施の形態と異なる点は、封止部50の形成工程及び封止部50の形状並びに個片化工程にあるので、これらについて説明し、第1の実施の形態と同じ工程及び構成については、図示及びその詳細な説明を省略する。
図7(A)、(B)及び(C)を参照して、第2の実施の形態の製造方法により製造される半導体装置の構成につき説明する。
12:リードフレーム
12a:第1最外側リードフレーム
12b:第2最外側リードフレーム
12c:上面
12d:下面
14:外部端子
20:半導体チップ
20a:第1の主表面
20b:第2の主表面
20c:端面
20d:側面
22:電極パッド
30:接着材
40:ボンディングワイヤ
50:封止部
50a:表面
50b:側面
50c:端面
50d:フレーム間封止部
60:溝部
70:封止層
Claims (14)
- (1)複数の直線状リードフレームを互いに離間して、並列に配列する工程と、
(2)複数の電極パッドを具えている第1の主表面、該第1の主表面に対向する第2の主表面を有する複数個の半導体チップを、複数の前記直線状リードフレームのうち、両側の最外側リードフレームより内側に配列される複数の前記直線状リードフレームにわたり、かつ前記直線状リードフレームの延在方向に互いに離間させて、前記半導体チップの第2の主表面側を接着材を用いて接着して搭載する工程と、
(3)複数の前記電極パッドと、複数の前記直線状リードフレームとをボンディングワイヤにより接続する工程と、
(4)前記半導体チップ及び前記ボンディングワイヤを封止する封止部と、該封止部外に露出して隣接する前記直線状リードフレーム同士の間隙を埋め込むフレーム間封止部とを形成する工程と、
(5)両側の前記最外側リードフレームより内側のリードフレームであって、前記第2の主表面の直下に位置する全ての前記直線状リードフレームを、該直線状リードフレームの延在方向に対して垂直な方向で切断し、前記接着材を露出させる溝部を形成する工程と、
(6)前記複数個の半導体チップ同士の間に露出している前記リードフレーム及び前記フレーム間封止部を切断して、該半導体チップと、前記溝部を挟んで対向する第1外部端子列及び第2外部端子列とを有する半導体装置に個片化する工程と
を含むことを特徴とする半導体装置の製造方法。 - (1)複数の直線状リードフレームを互いに離間して、並列に配列する工程と、
(2)複数の電極パッドを具えている第1の主表面、該第1の主表面に対向する第2の主表面を有する複数個の半導体チップを、複数の前記直線状リードフレームのうち、両側の最外側リードフレームより内側に配列される複数の前記直線状リードフレームにわたり、かつ前記直線状リードフレームの延在方向に互いに離間させて、前記各々の半導体チップの第2の主表面側を接着材を用いて接着して搭載する工程と、
(3)前記複数の電極パッドと、複数の前記直線状リードフレームとをボンディングワイヤにより接続する工程と、
(4)前記複数個の半導体チップ、該複数個の半導体チップそれぞれに接続されている前記ボンディングワイヤを封止する封止層を形成する工程と、
(5)両側の前記最外側リードフレームより内側のリードフレームであって、前記第2の主表面の直下に位置する全ての前記直線状リードフレームを、該直線状リードフレームの延在方向に対して垂直な方向で切断し、前記接着材を露出させる溝部を形成する工程と、
(6)前記複数個の半導体チップ同士の間の封止層及びリードフレームの部分を切断して、該半導体チップと、残存しているリードフレーム部分で形成され、前記溝部を挟んで対向し及び切断による切断面から露出する第1外部端子列及び第2外部端子列を有する半導体装置に個片化する工程と
を含むことを特徴とする半導体装置の製造方法。 - 前記(2)工程は、前記最外側リードフレームを前記半導体チップから露出させて行う工程であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記(3)工程は、前記複数の電極パッドと前記最外側リードフレームより内側のリードフレームとをボンディングワイヤにより接続する工程であることを特徴とする請求項1又は2に記載の半導体装置の製造方法。
- 前記(4)工程は、前記第1外部端子列及び前記第2外部端子列の前記半導体チップが搭載される面の対向面を露出させて前記封止部を形成する工程であることを特徴とする請求項1に記載の半導体装置の製造方法。
- 前記(5)工程は、前記封止部から露出している前記第1外部端子列及び前記第2外部端子列の面積が等しくなる位置で前記直線状リードフレームを切断して前記溝部を形成する工程であることを特徴とする請求項5に記載の半導体装置の製造方法。
- 前記(4)工程は、前記第1外部端子列及び前記第2外部端子列の前記半導体チップが搭載される面の対向面を露出させて前記封止層を形成する工程であることを特徴とする請求項2に記載の半導体装置の製造方法。
- 前記(5)工程は、前記封止層から露出している前記第1外部端子列及び前記第2外部端子列の面積が等しくなる位置で前記直線状リードフレームを切断して前記溝部を形成する工程であることを特徴とする請求項7に記載の半導体装置の製造方法。
- 前記(1)工程に用いられる複数の前記直線状リードフレームは、その両端それぞれがリールに巻きつけられて展張保持されており、前記(2)から前記(6)工程は、当該リールに巻きつけられた前記直線状リードフレーム上で行われることを特徴とする請求項1から8のいずれか一項に記載の半導体装置の製造方法。
- 互いに離間して設けられている複数の第1外部端子と、
前記第1外部端子の配列の延長線上に設けられている複数の第2外部端子と、
複数の電極パッドを有し、前記第1及び第2外部端子上に接着材を用いて搭載されている半導体チップと、
複数の前記電極パッドと前記第1及び第2外部端子それぞれとを接続する複数のボンディングワイヤと、
前記半導体チップと前記ボンディングワイヤとを封止する封止部と、
前記第1外部端子同士の間及び前記第2外部端子同士の間とを封止するフレーム間封止部とを具えており、
前記第1外部端子と前記第2外部端子とは、前記半導体チップの直下に設けられていて、前記接着材を露出させている溝部によって互いに離間されていることを特徴とする半導体装置。 - 複数の前記第1外部端子は、ストライプ状に互いに離間されていることを特徴とする請求項10に記載の半導体装置。
- 前記封止部は、前記第1外部端子及び前記第2外部端子の前記半導体チップが搭載される面の対向面を露出させて設けられていることを特徴とする請求項10に記載の半導体装置。
- 前記封止部と前記フレーム間封止部とは、一体として設けられていることを特徴とする請求項10に記載の半導体装置。
- 前記封止部から露出している前記第1外部端子及び前記第2外部端子の面積が等しくされていることを特徴とする請求項10に記載の半導体装置。
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