JPS5617459A - Information processor - Google Patents

Information processor

Info

Publication number
JPS5617459A
JPS5617459A JP9395579A JP9395579A JPS5617459A JP S5617459 A JPS5617459 A JP S5617459A JP 9395579 A JP9395579 A JP 9395579A JP 9395579 A JP9395579 A JP 9395579A JP S5617459 A JPS5617459 A JP S5617459A
Authority
JP
Japan
Prior art keywords
bus
processors
input
information processor
constitution
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP9395579A
Other languages
Japanese (ja)
Inventor
Masakazu Mise
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP9395579A priority Critical patent/JPS5617459A/en
Publication of JPS5617459A publication Critical patent/JPS5617459A/en
Pending legal-status Critical Current

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  • Multi Processors (AREA)

Abstract

PURPOSE: To obtain an information processor flexible for a circuit constitution of high processing performance equipped with processors and their peripheral equipment in bus groups separately.
CONSTITUTION: Processors APU and BPU, input-output unit IO, input-output control part ADM and memories AM and BM are connected to four buses B1WB4, for example, as shown in the figure. Those buses B1WB4, supervised by bus supervisor BSV, are freely connected by gates G1WG4 for bus connections so as to attain the required functions of the whole processors, thereby constituting the best bus groups. The bus supervisor, consisting of state control circuit STC and refresh control part REF, exercises on-off control over gates G1WG5.
COPYRIGHT: (C)1981,JPO&Japio
JP9395579A 1979-07-23 1979-07-23 Information processor Pending JPS5617459A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP9395579A JPS5617459A (en) 1979-07-23 1979-07-23 Information processor

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP9395579A JPS5617459A (en) 1979-07-23 1979-07-23 Information processor

Publications (1)

Publication Number Publication Date
JPS5617459A true JPS5617459A (en) 1981-02-19

Family

ID=14096838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP9395579A Pending JPS5617459A (en) 1979-07-23 1979-07-23 Information processor

Country Status (1)

Country Link
JP (1) JPS5617459A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957377U (en) * 1982-10-08 1984-04-14 積水化学工業株式会社 rain gutter packing structure
TWI408783B (en) * 2008-02-06 2013-09-11 Sanyo Electric Co Circuit device and manufacturing method thereof

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS5957377U (en) * 1982-10-08 1984-04-14 積水化学工業株式会社 rain gutter packing structure
TWI408783B (en) * 2008-02-06 2013-09-11 Sanyo Electric Co Circuit device and manufacturing method thereof

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