CN104167368A - 具有镀覆的引线的集成电路封装系统及其制造方法 - Google Patents
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Abstract
集成电路封装系统及其制造方法,所述方法包括:提供具有未处理的引线的引线框;在所述未处理的引线的上表面上沉积蚀刻掩模,所述未处理的引线具有所述蚀刻掩模以及所述上表面的未形成掩模的部分;将集成电路管芯连接到所述未处理的引线;利用封装体包封所述引线框,所述未处理的引线的所述上表面从所述封装体露出;形成可侧焊的引线,所述形成可侧焊的引线的步骤包括在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下,所述在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下的步骤包括在所述槽之上形成所述蚀刻掩模的悬垂部分;移除所述蚀刻掩模;以及在所述可侧焊的引线上沉积镀层。
Description
技术领域
本发明总地涉及集成电路封装系统,并且更具体地,涉及具有镀覆的引线(plated lead)的系统。
背景技术
很大程度上受对以用于紧凑的或便携的电子装置(例如移动电话、智能手机、个人媒体系统、超便携计算机)的较小芯片尺寸增大处理能力的需求的驱使,半导体芯片已经变得日益复杂。
针对封装集成电路(IC)管芯存在众多常规工艺。举例来说,许多IC封装使用已经从金属片被冲压或蚀刻来向外部器件提供电气互连的金属引线框(leadframe)。管芯可以通过接合导线、焊接凸起或其他适合的电气连接的方式被电气连接到引线框。
一般来说,管芯和引线框的部分利用模塑材料来包封(encapsulate),以保护管芯的有源侧(active side)的精细电气部件,同时使引线框的被选择的部分露出,来便利到外部器件的电气连接。
响应于较小的芯片尺寸,已经逐步形成了封装技术,例如来使得增大的引线密度能够实现,这可以减少印刷电路板(PCB)上安装的封装的所占面积。某些封装技术可以通过提供连接到引线框的可弃置部分的数行引线来使得这一增大的引线密度能够实现。
以附加方式进一步减小封装尺寸可能是合乎期望的。同时,保持封装和连接的充分结构完整性可能是合乎期望的。还可以是合乎期望的是,构想出被设计来满足这些目标的封装工艺。当前的封装方案可以满足这些目标中的一些,但可能无法满足这些目标中的大部分或全部。
因此,仍然存在对更好的制造方法的需求。鉴于对可靠性的需求,找到针对这些问题的解决办法是越来越关键的。鉴于持续增加的商业竞争压力连同增长的消费者预期以及市场中获得有意义的产品差异机会的逐渐减少,找到这些问题的解决办法是越来越关键的。另外,对于降低成本、提高效率和改善性能以及满足竞争压力的需要为找到这些问题的答案的关键必要性增添了更大的紧迫性。
长久以来一直在寻求对于这些问题的解决方案,但是之前的发展尚未教导或建议任何解决方案,因此,对于这些问题的解决方案长久以来一直困惑本领域的技术人员。
发明内容
本发明提供集成电路封装系统的制造方法:提供具有未处理的引线的引线框;在所述未处理的引线的上表面上沉积蚀刻掩模,所述未处理的引线具有所述蚀刻掩模以及所述上表面的未形成掩模的部分;将集成电路管芯连接到所述未处理的引线;利用封装体(packagebody)包封所述引线框,所述未处理的引线的所述上表面从所述封装体露出;形成可侧焊的(side-solderable)引线,所述形成可侧焊的引线的步骤包括在所述未处理的引线中形成槽,所述在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下的步骤包括在所述槽之上形成所述蚀刻掩模的悬垂部分;移除所述蚀刻掩模;以及在所述可侧焊的引线上沉积镀层。
除了以上提及的步骤或元件之外或者替代以上提及的步骤或元件,本发明的特点实施方案具有其他步骤或元件。当参照附图进行以下详细描述时,通过阅读该详细描述,这些步骤或元件对于本领域的技术人员将变得清楚。
附图说明
图1是本发明的实施方案中的集成电路封装系统的等轴测顶视图。
图2是由图1的虚线矩形2描绘的小图中的图1的详细视图。
图3是在制造的掩模阶段中引线框的等轴测顶视图。
图4是由图3的虚线矩形描绘的小图中的图3的详细视图。
图5是在制造的包封阶段中由图3的虚线矩形5描绘的小图中的图3的未处理的引线的等轴测顶视图。
图6是制造的蚀刻阶段中图5的结构。
图7是制造的镀覆阶段中图6的结构。
图8是制造的分割阶段中图7的结构。
图9是本发明的进一步的实施方案中的集成电路封装系统的制造方法的流程图。
具体实施方式
充分详细地描述以下实施方案,以使得本领域的技术人员能够实现并使用本发明。要理解的是,其他实施方案基于本公开将是显而易见的,并且可以在不脱离本发明的范围的情况下改变系统、处理或机械。
在以下描述中,给出了许多特定细节,以提供本发明的透彻理解。然而,将显而易见的是,可以在没有这些特定细节的情况下实施本发明。为了避免模糊本发明,不详细公开一些公知的电路、系统构造和处理步骤。
示出所述系统的实施方案的附图是半图解式的,并且不按比例绘制,特别是,一些尺寸在附图中为了呈现的清晰度被放大示出。类似地,尽管附图中的视图为了易于描述通常示出类似的方位,但是附图中的这一描绘对于大部分是任意的。一般来讲,可以以任意方位操作本发明。
在所有附图中使用的相同编号涉及相同要素。附图周围的波状线用来示出仅有结构的一部分被示出。
为了说明的目的,本文中所使用的术语“水平面”被定义为与可侧焊的引线的平面或表面平行的平面,而不管可侧焊的引线的方位如何。术语“垂直”是指垂直于刚才定义的水平面的方向。如图所示,诸如“在…上面”、“在…下面”、“底部”、“顶部”、“侧”(如“侧壁”中)、“高于”、“低于”、“上部”、“在…之上/上方(over)”以及“在…下方”的术语是相对于水平面定义的。术语“在…上(on)”意味着在元件之间存在直接接触。术语“直接在……上”意指在一个元件和另一个元件之间存在直接接触而没有介于中间的元件。
术语“有源侧”是指管芯、模块、封装或其上制造有有源电路的电子结构的一侧,或者具有用于连接到管芯、模块、封装或电子结构中的有源电路的元件的一侧。
本文所使用的术语“处理”包括在形成所描述的结构中所需要进行的材料或光阻材料的沉积、图形化、曝光、显影、蚀刻、清洁和/或材料或光阻材料的移除。
现在参照图1,其中示出本发明的实施方案中的集成电路封装系统100的等轴测顶视图。该等轴测顶视图示出管芯载盘102、封装体104以及可侧焊的引线106。管芯载盘102可以具有附接到底侧并且包封在封装体104中的集成电路管芯(未示出)。管芯载盘102可以用来帮助散热、用作集成电路管芯的接地平面或者它们的组合。集成电路封装系统100例如可以为方形扁平无引脚封装(QFN)。
管芯载盘102和可侧焊的引线106被嵌入封装体104,同时也是从封装体104露出的。封装体104可以保护集成电路管芯并且可以为诸如环氧树脂模塑料、树脂或其他不导电材料的材料。集成电路管芯可以利用诸如接合线的互连件(未示出)被连接到可侧焊的引线106。
管芯载盘102和可侧焊的引线106可以由诸如铜的金属制成并且在管芯载盘102和可侧焊的引线106的大部分露出的表面上可以具有镀层108。镀层108用作焊料可润湿(solder-wettable)表面来通过焊料连接到电路板或其他系统,并且可以由诸如锡、共晶化合物或其他焊料可润湿的和导电材料的材料构成。镀层108可以具有5-20μm的厚度,并且可侧焊的引线106可以具有符合JEDEC标准或者介于0.4mm和1.0mm之间的间距。
可侧焊引线106在上表面和侧表面上从封装体104露出。可侧焊引线106的未镀覆部分110是可视的,与封装体104的侧部共面。可侧焊引线106的其他露出的表面,包括可侧焊引线106的边缘中的槽112,被覆盖在镀层108中。由于槽112提供的额外表面面积,可侧焊引线106具有更大的表面面积来用于焊料进行接触,一旦被安装或焊接在板上得到抵抗多方向压力的更强且更可靠的连接。可侧焊引线106用于连接到下一级系统或板。
现在参照图2,其中示出由图1的虚线矩形2描绘的小图中的图1的详细视图。在该视图中,可侧焊引线106可以被详细地看到,并且槽112在每个可侧焊引线106的侧部中是可见的。槽112可以具有弯曲形状或者平的倾斜表面和弯曲表面的组合,并且可以终止于可侧焊引线106的未镀覆部分110处。图2周围的波状线用来示出只有结构的一部分被示出。
出于图示说明的目的,镀层108被示为在封装体104上,但理解的是,镀层108可以相对于封装体104在不同位置。例如,镀层108可以与封装体104的表面共面,或者镀层108可以凹陷于封装体104的表面之下。还要理解的是,镀层108的厚度出于视觉效果的目的是被夸大的,并且镀层108的厚度可以小于所示的样子。
现在参照图3,其中示出制造的掩模阶段中引线框314的等轴测顶视图。在该视图中,引线框314对于制造两个图1的集成电路封装系统100是充分的,但理解的是,引线框314可以具有任何尺寸。例如,引线框314可以对于制造4个、6个、9个或任何其他数目的集成电路封装系统100是充分的。
引线框314在引线框314的未处理的引线318上可选地覆盖有蚀刻掩模316,使未处理的引线318的未形成掩模的部分320露出。未处理的引线318的未形成掩模的部分320可以在未处理的引线318的边缘处。蚀刻掩模316将保护引线框314的被覆盖的部分不受随后的蚀刻步骤的影响,允许引线框314仅被选择性地蚀刻通过未处理的引线318的未形成掩模的部分320。蚀刻掩模316例如可以为单层或多层金属、保护性有机材料或者金属和有机材料(例如,蓝色油墨(Blue Ink)、环氧树脂、树脂等)的组合。引线框314的未处理的引线318被用作基底来在进一步处理之后形成图1的可侧焊引线106。
可以根据何种材料被用于蚀刻掩模316而使用不同工艺来施加蚀刻掩模316。例如,蚀刻掩模316可以使用这样的工艺被沉积,例如其后进行化学或物理汽相沉积的掩模、其后进行电化学镀或无电镀的掩模、掩模和浸渍、印刷或点胶(dispensing)。
出于图示说明的目的,蚀刻掩模316被示出以一端平坦而另一端弯曲的形状覆盖未处理的引线318的一部分,但理解的是,这仅仅是实施例,而蚀刻掩模的316的形状可以是不同的。例如,蚀刻掩模316可以具有半圆、三角的形状或其他的形状,并且蚀刻掩模316可以具有波状而非直的边缘。
管芯载盘102被示出为没有连接到引线框314的其余部分,但理解的是,这一细节已经出于清楚的目的而被省略。管芯载盘102可以通过例如带状杆(tie bar)或坝状杆(dambar)连接到引线框314的其余部分。管芯载盘102被示出不具有任何未形成掩模的部分320,但是如果可侧焊构件在管芯载盘102上是期望的,则管芯载盘102可以具有未形成掩模的部分320。
现在参照图4,其中示出由图3的虚线矩形4描绘的小图中的图3的详细视图。在该视图中,具有未形成掩模的部分320和蚀刻掩模316的未处理的引线318可以被更加详细的看到。蚀刻掩模316可以被选择性地沉积在未处理的引线318的顶部上,使未处理的引线318的未形成掩模的部分320是露出的。
现在参照图5,其中示出在制造的包封阶段中,由图3的虚线矩形5描绘的小图中的图3的未处理的引线318的等轴测顶视图。在该视图中,封装体104已经被施加来覆盖图3的引线框314的大部分,而使未处理的引线318的顶部和管芯载盘102露出。尽管是不可视的,集成电路管芯(未示出)在包封之前,被安装在管芯载盘102上并且电气连接到未处理的引线318。
封装体104可以被模制在集成电路管芯和引线框314上,以至于封装体104与未处理的引线318和管芯载盘102的表面共面。未处理的引线318的上表面可以被露出,而未处理的引线318的其余部分被嵌入封装体104。蚀刻掩模316和未形成掩模的部分320从未处理的引线318的上表面上的封装体104露出。这一包封步骤可以由这样的工艺执行,例如,举例说明,注塑模制、压缩模制或者膜辅助模制(film assist molding)。
封装体104被描述为在蚀刻掩模316的选择性施加之后被模制在引线框314上,但理解的是,工艺可以被改变。例如,封装体104可以被模制在引线框314上并且首先是集成电路管芯且然后是蚀刻掩模316可以被选择性地施加到引线框314的露出的部分。
现在参照图6,其中示出在制造的蚀刻阶段中图5的结构。图3的未处理的引线318已经被蚀刻,并且蚀刻掩模316的一部分已经被移除。
经受蚀刻工艺,图4的未形成掩模的部分320将从上表面被向下移除。例如,各向同性蚀刻工艺将以相等速率在所有方向上进行蚀刻,并且将在蚀刻剂侵蚀所形成的槽的侧壁时在蚀刻掩模316的一部分之下进行蚀刻。该蚀刻工艺将形成弯曲凹入部并且在槽112之上留下蚀刻掩模316的悬垂部分或垂悬件,如果镀层被用作蚀刻掩模316,则有时被称为“狗耳镀层(dog ear plating)”。蚀刻剂被选择来仅蚀刻到未形成掩模的部分320中而不损坏封装体104或蚀刻掩模316。例如,未形成掩模的部分320在未处理的引线318的边缘处意味着槽112也在引线的边缘处,其中一个边缘面对封装体104,并且在悬垂部分移除之前,相对的边缘在蚀刻掩模316的悬垂部分之下。
蚀刻工艺可以被控制来蚀刻通过未处理的引线318的高度的大致一半,形成槽112的弯曲的形状。在蚀刻步骤之后,蚀刻掩模316的悬垂件被移除。例如,高压修边工艺(highpressure deflash process)可以被用来移除悬垂部分。这导致当从顶部看时,槽112大于未形成掩模的部分320的原始尺寸,因为蚀刻掩模316被部分地移除。蚀刻掩模316表面面积在悬垂部分移除之后将会是较小的。
已经发现,通过使用蚀刻掩模316的蚀刻工艺形成的槽112提高整体连接性。因为不进行锯切来形成槽112,所以没有创建毛刺,并且不会由于锯切工艺的自然结果所形成的毛刺而降低可靠性。此外,与锯切工艺不同,在由蚀刻工艺形成槽112期间,没有物理压力置于未处理的引线318上,这也提高可靠性。
此外,已经发现,未处理的引线318上的蚀刻掩模316的选择性施加提供槽设计的灵活性。因为槽112由于蚀刻掩模316的选择性的施加而具有一形状(所述槽112可以被图形化为几乎任何适合的形状),与锯切槽112相比,槽112可以被设计为更多的形状。这一更大的灵活性例如可以允许增大表面面积的量,用于随后施加焊料和更好的连接。
已经发现,随后进行蚀刻工艺的蚀刻掩模316的选择性施加对槽112的尺寸提供比锯切工艺更好的控制。所有工艺都会经历一些偏差,但因为蚀刻工艺可以比锯切被更严格地控制,要考虑的对偏差的容限是较小的,这导致更少的浪费、更大的灵活性以及对槽112的尺寸的更好的控制。
现在参照图7,其中示出制造的镀覆阶段中的图6的结构。镀覆阶段在图3的蚀刻阶段和蚀刻掩模316的移除之后。
蚀刻掩模316可以被完全移除,以制备可侧焊的引线106和管芯载盘102来进行镀覆。在蚀刻掩模316的悬垂部分的移除之后,蚀刻掩模316的剩余部分可以使用干抛光工艺(dry buffing process)被移除,这还用于使表面平面化。移除悬垂部分和蚀刻掩模316的其余部分的可替换的工艺是利用其后去除(stripping)镀层的化学修边来替换高压修边。另一可替换的工艺是利用单一干抛光工艺移除蚀刻掩模316的悬垂部分以及蚀刻掩模316的剩余部分。另一可能性是例如通过可以实现修边作用又移除蚀刻掩模的化学机械平面化(CMP)来去除镀层而不进行单独的修边步骤。
一旦蚀刻掩模316被移除,可侧焊引线106的所有构件(包括槽112)和从封装体104的顶部露出的管芯载盘102使用镀覆工艺(例如电镀、无电镀、电化学镀、印刷、溅射或某种形式的汽相沉积)被覆盖以镀层108。例如,可侧焊引线106可以使镀层108直接沉积在槽112的裸金属以及可侧焊引线106的上面的表面上。
出于图示说明的目的,镀层108被示出为自封装体104的表面是明显升高的,但理解的是,这是出于视觉效果的目的。镀层108可以以各种厚度被施加并且不限于任何特定的厚度。厚度的选择可以取决于镀层108的组成。
已经发现,可侧焊引线106的裸金属上的镀层108导致更好的焊接连接。镀层108直接在可侧焊引线106的铜上的沉积允许镀层108和可侧焊引线106之间的更好的接合,这可以提高焊接连接的强度。例如,在层之间存在分层可能性的点较少,将增加连接的可靠性并且提高强度。
现在参照图8,其中示出制造的分割阶段中图7的结构。在镀层108已经被沉积或施加在可侧焊引线106和管芯载盘102上之后,集成电路封装系统100可以通过在可侧焊引线106的行之间进行切割的分割工艺来形成。分割工艺可以在集成电路封装系统100的侧部露出可侧焊引线106的未镀覆部分110。
现在参照图9,其中示出本发明的进一步实施方案中的集成电路封装系统的制造方法900的流程图。方法900包括:在方框902,提供具有未处理的引线的引线框;在方框904,在未处理的引线的上表面上沉积蚀刻掩模,所述未处理的引线具有蚀刻掩模以及上表面的未形成掩模的部分;在方框906,将集成电路管芯连接到未处理的引线;在方框908,利用封装体包封引线框,未处理的引线的上表面从封装体露出;在方框910,形成可侧焊引线的步骤包括在未处理的引线中形成槽,蚀刻掩模具有在槽之上的悬垂部分;在方框912,移除蚀刻掩模;以及在方框914,在可侧焊引线上沉积镀层。
因此,已经发现,本发明的集成电路封装系统为QFN封装的可靠制造提供重要的、在此前是未知的且不可获得的技术方案、能力以及功能性方面。
所得的方法、处理、设备、装置、产品和/或系统是简单的、成本有效的、不复杂的、高度通用的、精确的、灵敏的且有效的,并且可以通过改装已知的组件来实现以用于准备好的、高效率的且经济的制造、应用和利用。
本发明的另一重要方面是,它有价值地支持并服务于降低成本、简化系统和提高性能的历史趋势。
本发明的这些和其他有价值的方面因此将本技术的状态至少推进到下一个水平。
尽管已经结合特定最佳模式对本发明进行了描述,但是要理解,鉴于前述描述,许多替代方式、修改方式和变化方式对于本领域的技术人员将是显而易见的。因此,意图是涵盖落在所包括的权利要求书的范围内的所有这样的替代方式、修改方式和变化方式。在本文中到目前为止所阐述的或者在附图中所示出的所有内容都要从说明性而非限制性的意义上进行解释。
Claims (10)
1.一种集成电路封装系统的制造方法,所述方法包括:
提供具有未处理的引线的引线框;
在所述未处理的引线的上表面上沉积蚀刻掩模,所述未处理的引线具有所述蚀刻掩模以及所述上表面的未形成掩模的部分;
将集成电路管芯连接到所述未处理的引线;
利用封装体包封所述引线框,所述未处理的引线的所述上表面从所述封装体露出;
形成可侧焊的引线,所述形成可侧焊的引线的步骤包括在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下,所述在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下的步骤包括在所述槽之上形成所述蚀刻掩模的悬垂部分;
移除所述蚀刻掩模;以及
在所述可侧焊的引线上沉积镀层。
2.如权利要求1中所述的方法,其中移除所述蚀刻掩模的步骤包括对所述蚀刻掩模应用干抛光工艺以移除所述蚀刻掩模的所述悬垂部分和剩余部分。
3.如权利要求1所述的方法,其中移除所述蚀刻掩模的步骤包括:
对所述悬垂部分应用高压修边工艺;以及
对所述蚀刻掩模应用干抛光工艺。
4.如权利要求1所述的方法,其中移除所述蚀刻掩模的步骤包括:
对所述悬垂部分和所述上表面应用化学修边工艺;以及
去除所述蚀刻掩模。
5.如权利要求1所述的方法,其中移除所述蚀刻掩模的步骤包括对所述蚀刻掩模应用化学机械平面化工艺。
6.一种集成电路封装系统的制造方法,所述方法包括:
提供具有未处理的引线的引线框;
在所述未处理的引线的上表面上沉积蚀刻掩模,所述未处理的引线具有所述蚀刻掩模以及所述上表面的未形成掩模的部分;
将集成电路管芯连接到所述未处理的引线;
利用封装体包封所述引线框和所述集成电路管芯,所述未处理的引线的所述上表面从所述封装体露出;
蚀刻通过所述上表面的所述未形成掩模的部分来从所述未处理的引线形成可侧焊的引线,所述形成可侧焊的引线的步骤包括在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下,所述在所述未处理的引线中形成槽,所述槽形成在所述蚀刻掩模的一部分之下的步骤包括在所述槽之上形成所述蚀刻掩模的悬垂部分;
移除所述蚀刻掩模;以及
在所述可侧焊的引线上沉积镀层。
7.如权利要求6所述的方法,其中提供所述引线框的步骤包括提供具有管芯载盘的引线框。
8.如权利要求6所述的方法,其中在上表面上沉积蚀刻掩模的步骤包括沉积所述蚀刻掩模使得未形成掩模的部分位于所述上表面的边缘。
9.如权利要求6所述的方法,其中蚀刻通过所述上表面的所述未形成掩模的部分的步骤包括应用各向同性蚀刻工艺。
10.如权利要求6所述的方法,其中利用所述封装体包封的步骤包括包封所述集成电路管芯。
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US9048228B2 (en) * | 2013-09-26 | 2015-06-02 | Stats Chippac Ltd. | Integrated circuit packaging system with side solderable leads and method of manufacture thereof |
US10892211B2 (en) | 2017-08-09 | 2021-01-12 | Semtech Corporation | Side-solderable leadless package |
CN109243988A (zh) * | 2018-09-14 | 2019-01-18 | 上海凯虹科技电子有限公司 | 封装体及其封装方法 |
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TWI606525B (zh) | 2017-11-21 |
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