TW512503B - Integrated circuit package having partially exposed conductive layer - Google Patents

Integrated circuit package having partially exposed conductive layer Download PDF

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Publication number
TW512503B
TW512503B TW90117328A TW90117328A TW512503B TW 512503 B TW512503 B TW 512503B TW 90117328 A TW90117328 A TW 90117328A TW 90117328 A TW90117328 A TW 90117328A TW 512503 B TW512503 B TW 512503B
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Taiwan
Prior art keywords
integrated circuit
conductive layer
circuit package
patent application
item
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Application number
TW90117328A
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English (en)
Inventor
Charles Cohn
Jr Donald Earl Hawk
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Agere Syst Guardian Corp
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Publication of TW512503B publication Critical patent/TW512503B/zh

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    • H—ELECTRICITY
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    • H01L24/42—Wire connectors; Manufacturing methods related thereto
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    • H01L23/488—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor consisting of soldered or bonded constructions
    • H01L23/498—Leads, i.e. metallisations or lead-frames on insulating substrates, e.g. chip carriers
    • H01L23/49827—Via connections through the substrates, e.g. pins going through the substrate, coaxial cables
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  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Wire Bonding (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)

Description

512503 A7 B7 五、發明説明（1 發明領域 本發明一般性地涉及積體電路，更特定言之，本發明涉 及積體電路之封裝以及製造那些封裝之方法。 發明背景 由於球柵陣列（BGA)積體電路封裝（此後稱之爲BGA封裝） 具有許多較其他封裝技術爲優的特性，所以積體電路晶片 廣泛地使用此種封裝技術。BGA封裝可在有限的面積中安 裝多引腳的結構。另外，由於BGA封裝的外部端子既粗且 短，所以較不易受到衝擊損害。除此之外，BGA封裝的接 合銲墊到錫球的跡線長度亦相對較短，此可增進電效能。 圖8是一般的BGA封裝。該BGA封裝包含基板1及積體電 路晶片3，此基板爲雙面或多層結構，積體電路晶片則是以 黏著劑2黏著於基板1之上表面。金屬導線4使多個形成於 積體電路上表面上之接合銲墊3a，與形成於基板1上之接 合銲墊7在電氣上互連。基板1的上表面上亦提供出一塑封 區5 ’將該積體電路晶片3及金屬導電4加以膠封。锡球ό黏 著於基板1的下表面。接合銲墊7利用形成於基板1中之鍍 通孔8，與錫球6連接。 BGA封裝的製造包含以下幾個製程：黏晶製程，以黏著 劑2，將積體電路晶片3黏著於基板1的上中央部。接著， 銲線製程，以金屬導線4，將形成於該積體電路3上表面上 之接合銲墊3a，與形成於基板1上之接合銲墊7予以互連。 封膠製程，以環氧樹脂將積體電路3、金屬導線4以及基板 1之上表面的一邵份加以膠封，形成塑封區5。錫球6的植 -4- 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）
裝 玎
512503 A7 _ B7 五、發明説明（2 ) 球製程，將錫球黏著於基板1的下表面。 雖然BGA封裝有許多優點，但亦有其缺陷。舉個例子， 該多金屬層結構之基板1中將會有大量的通孔，廣佈於電源 環及接地環之間以及各個内平面之間。此造成該等内部的 電源平面及接地平面之導電路徑減少，使電效能退化。於 是，欲發展一種可降低此問題程度之BGA封裝。 發明摘要 本發明係關於積體電路晶片所使用之積體電路封裝（譬如 ，BGA封裝）。該積體電路封裝之基板具有一個腔洞，曝露 出基板内部的導電層，如此，積體電路可與該内部的導電 層直接連接，減少了以鍍通孔從一個導電層連接至另一個 導電層的需要。内部電源平面及接地平面中因鍍通孔的存 在而必須切斷的導電路徑將因此減少，先前技術所受之電 效能退化之苦得以避免或減輕。本發明可更進一步地容納 更多的信號，以及/或者縮減積體電路的尺寸，以增進電效 能。另外，此多接合層之積體電路封裝可令導線間的距離 加寬，此有利於銲線及後續的封膠製程。 舉個例證：該積體電路封裝之基板包含一形成於第一介 電層之上之導電層，以及一形成於該第一導電層之上之第 二介電層。該第二介電層具有一腔洞，曝露出一部份的第 一導電層。積體電路則位在該第二介電層之上，與該第 一導電層之曝露部份連接。 應了解，以上之一般性敘述以及以下詳細地敘述均止於 示範，本發明不限於此。 本紙張尺度適用中國國家標準(CNS) A4規格(210X297公釐)
要説明
配合著附圖閱讀以下的詳細說明，將會對本 ~。必須強調的是，根據半導體工業的慣 J :毋=例1會製。相反地，各部份的尺寸可依說明ί: 而，自由地放大縮小。本說明之圖示包含·· 圖1乃一流程圖，示範說明本發明球柵陣列封裝之程製； 圖2_6乃本發明圖工製程所製造之球栅陣列基板其於 作階段時的簡圖； 、&
圖7是圖5之球栅陣列基板的頂視圖；以及 圖8是傳統球柵陣列封裝之簡圖。 t明之詳細説明 裝 現參考圖式，其中相同的參考數字代表相同的元件。圖1 心流程圖説明本發明積體電路封裝製程之示範用具體實施 例。以下參照著圖2_6，對圖示之製程加以説明。
步驟100，提供出一多層基板10(圖2)。製造多層基板1〇 的程序眾所周知。該基板包含絕緣層2〇，22，24及導電層 30，32 ’34 ’36。導電層3〇, 32, 34, 36可以使用標準 的技術予以圖案化。將這些金屬層圖案化以形成從多層基 板10之頂12至底14之互連態勢。導電層3〇，32，34，36 可以是像銅這樣的金屬，或是其他合適的導電物質。 步驟110 ’使用標準的方法，於該多層基板丨〇中形成像 40及42(圖3)這樣的通孔。該等通孔可以使用譬如，多層 基板10之機械或雷射鑽孔的方式而形成。雖然圖中所示僅 兩個通孔40及42，但該多層基板10中之通孔數可以不止於 本紙張尺度適用中國國豕標準(CNS) A4規格(210 X 297公爱) -6- A7 B7
512503 五、發明説明$ 此。 接著，步驟112，將通孔40、42以及外導電層加以電嫂 。外導電層包括導電層32及36。電鍍的程序爲：先於曝^ 面（包括通孔）上形成一種子層，接著再施以無電極電敏及 電極電鍍。電鍍材料包括，譬如，銅。步驟114，使用眾所 周知之方法，將導電層3 2及3 6圖案化。然後，步驟丨16， 對導電層32及36施以銲錫遮罩46及48，決定出導電層32 及3 6的曝露部份及絕緣層2 2的圖案。 接著，步驟120，於絕緣層22中形成一腔洞5〇(圖5)，曝 露出導電層3 0。使用成型、雷射銑削、電漿蚀刻或其他的 腔洞成形技術均可形成腔洞5 0。導電層3 0的曝露使積禮電 路的接合導線得以直接地銲至多層基板1 〇中至少兩個不同 的接合層上。 一或多個的導電層3 0曝露部份可以形成不同的電源平面 、電源環或電源區。若是做成如此，則積體電路可有多個 接合銲墊互連至該等曝露平面、環或區域。導電層3 〇的曝 露部份除了可作電源平面之外，亦可將之形成爲接地平面 。使用此法將可縮減該用以連接電源或接地之通孔的需求 量或甚至不需使用。亦可將部份的曝露導電層3〇做成包含 一或多個接地平面、電源平面或用以連接信號之組合區域。 步驟130，將導電的導線可接合材料形成於導電層3〇， 32及36所曝露出之導電區域上。該導電材料可包含形成於 鎳上之金。若欲使用此種材料，則應先於導電層3〇，32及 3 6的曝露部份之上鍍鎳，然後再於鎳上鍍金。
裝
k
步驟140’裝置芫成（圖6)。此包含使用黏著劑70，將積 體電路晶片75連接至多層基板1〇。接合導線80形成於積體 電路上之接合銲墊（未顯示）及多層基板1〇上之連接區域及/ 或接合銲墊3 0 a，3 0 b，3 2 a，3 2 b之間。該連接區域所指 的是像接合銲墊這樣的導線可藉此直接連至導電層3 〇及3 2 的區域。最後，使用環氧樹脂將該積體電路晶片及接合導 線予以覆塑，並使用傳統的技術將錫球6 5連接至連接銲墊 6〇(形成於導電層36)上。 在此示範具體實施例中，積體電路晶片75乃是形成於遮 罩7 0區段上（圖6及7 )。雖然圖中僅有一條接合導線連接至 接地平面，但接地平面3 2 a及積體電路7 5之間的互連其實 是可以使用多條接合導線的。因此，該等用以將積體電路 7 5予以接地之多個通孔就毋須在多層基板丨〇中形成。 另外’導電層30之區段30a可以形成一電源平面，電連 接至積體電路晶片7 5。雖然圖中僅有一條接合導線連接至 该電源環3 0 a，但電源環3 0 a及積體電路7 5之間的互連其 實是可以使用多條接合導線的。該等用以將積體電路7 5與 電源平面30a予以互連之多個通孔就毋須在多層基板1〇中 形成。或者，區段3 0 b可以形成電源平面。電源平面、接 地平面或其他的導電層區段可以沿著積體電路的一、二、 二或更多側或甚至環繞著整個積體電路，共同形成一連續 的區域。 雖然本發明已以示範具體實施例爲代表加以説明，但本 發明不限於此些具體實施例。舉個例子，雖然上述示範用 512503 A7 B7 五、發明説明（6 ) 之具體實施例包含有四個導電層，不過本發明仍可應用於 三或更多導電層（以及用以分離這些導電層之相關絕緣層） 之基板。除此之外，腔洞的大小範圍可不僅止於一個介電 層，曝露基板的一或多個導電層。另外，信號線、電源或 接地的連結，或這些組合們連結，均可提供於基板的腔洞 之中。於是，所附之專利應建構成包含由習於此藝人士在 不脱離本發明之眞實精神及範圍的情況下所完成之本發明 的其他變化及具體實施例。 本紙張尺度適用中國國家標準(CNS) A4規格(210 X 297公釐）

Claims (1)

  1. κ、申請專利範圍 1 * 一種積體電路封裝，包含·· 一基板，含有： 一第一介電層； 一第一導電層，具有一第一區，其與/第/ 區絕緣且位於該第一介電層之上；及 位於該第一導電層上之一第二介電層，该第 二介電層具有一腔洞，其中該第一與第二區被 曝露於腔洞之内’該第一區藉由一第彡介電層 而與$亥弟二區絕緣；以及 一積體電路晶片，位於第二介電層之上，且 具有在第一導電層上與第一導電層曝露之第_區連接 之一第一導線以及與曝露之第二區連接之一第二導線。 2·如申請專利範圍第1項之積體電路封裝，其中該第/導 電層包含一連續區域以及該積體電路晶片包含接合銲墊 ，該連續區域與不止一個的該接合銲墊連接。 3·如申請專利範圍第2項之積體電路封裝，其中該連續彥 域是接地平面與電源平面二者之一。 4 ·如申請專利範圍第2項之積體電路封裝，其中該連續區 域至少沿著該積體電路晶片之一側，形成邊界。 5 ·如申請專利範圍第4項之積體電路封裝，其中該連續區 域圍繞著該積體電路。 6·如申請專利範圍第4項之積體電路封裝，其中該連續區 域至少沿著該積體電路晶片之兩側，形成邊界。 7 .如申請專利範圍第1項之積體電路封裝，其中該第/導 本紙張尺度適用中國國家標準(CNS) Α4規格（210 X 297公釐） 512503 A8 ’ B8 C8 ----- -D8 六、申請專利範圍^ ' --~-- 電層之曝露部份包含接地平面及電源+面二者之一。 8.如申請專利範圍第7項之積體電路封裝，其中該第一導 電層之曝露部份包含至少—個信號線所用之連接。 9·如申請專利範圍第1項之積體電路封裝，其中該第一導 電層足曝露部份包含至少一個信號線所用之連接。 1〇·如_請專利範圍第1項之積體電路封裝，另包含一形成 於$亥第一介電層之上之第二導電層。 11· 一種積體電路封裝，包含： 一基板能於其上支撐一積體電路且含有： 一第一介電層； 弟一導電層’具有一第一區，其與一第二 區絕緣且位於該第一介電層之上； 形成於該第一導電層之上之一第二介電層， 該第二介電層具有一腔洞，其中該第一與第二 區被曝露於腔洞之内而分別連接至一積體電路 之第一及第二導線；以及 弟一導電層’位於#亥弟一介電層之上且且 有供定位該積體電路之一地區。 12·如申請專利範圍第η項之積體電路封裝，其中該第一導 電層之曝露部份，形成接地平面及電源平面此二者之一 〇 13.如申請專利範圍第11項之積體電路封裝，其中該第一導 電層之曝露部份，另形成一信號線所用之連接。 本紙張尺度適用中國國家標準(CNS) Α4規格(210 X 297公釐）
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