KR20040037561A - 반도체패키지 - Google Patents
반도체패키지 Download PDFInfo
- Publication number
- KR20040037561A KR20040037561A KR1020020066108A KR20020066108A KR20040037561A KR 20040037561 A KR20040037561 A KR 20040037561A KR 1020020066108 A KR1020020066108 A KR 1020020066108A KR 20020066108 A KR20020066108 A KR 20020066108A KR 20040037561 A KR20040037561 A KR 20040037561A
- Authority
- KR
- South Korea
- Prior art keywords
- conductive
- semiconductor die
- plate
- semiconductor
- substrate
- Prior art date
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/34—Arrangements for cooling, heating, ventilating or temperature compensation ; Temperature sensing arrangements
- H01L23/36—Selection of materials, or shaping, to facilitate cooling or heating, e.g. heatsinks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
- H01L2224/161—Disposition
- H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/481—Disposition
- H01L2224/48151—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
- H01L2224/48221—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
- H01L2224/48225—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
- H01L2224/48227—Connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation connecting the wire to a bond pad of the item
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
- H01L2924/151—Die mounting substrate
- H01L2924/153—Connection portion
- H01L2924/1531—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface
- H01L2924/15311—Connection portion the connection portion being formed only on the surface of the substrate opposite to the die mounting surface being a ball array, e.g. BGA
Landscapes
- Engineering & Computer Science (AREA)
- Chemical & Material Sciences (AREA)
- Materials Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Cooling Or The Like Of Semiconductors Or Solid State Devices (AREA)
Abstract
Description
Claims (3)
- 수지층 내측에 그라운드 플랜이 형성되고, 상,하면에는 다수의 배선패턴이 형성되며, 상기 상,하의 배선패턴, 또는 배선패턴과 그라운드 플랜을 연결하는 다수의 도전성 비아가 형성된 서브스트레이트와, 상기 서브스트레이트의 상면에 위치되고, 하면에는 다수의 본드패드가 형성된 제1반도체 다이와, 상기 제1반도체 다이의 본드패드와 상기 서브스트레이트의 상면에 형성된 배선패턴을 전기적으로 연결하는 다수의 도전성 범프와, 상기 제1반도체 다이의 상면에 접착제로 접착되고, 상면에 다수의 본드패드가 형성된 제2반도체 다이와, 상기 제2반도체 다이의 본드패드와 상기 서브스트레이트의 상면에 형성된 다른 배선패턴을 상호 전기적으로 연결하는 다수의 도전성 와이어와, 상기 서브스트레이트 상면의 제1,2반도체 다이, 도전성 범프 및 도전성 와이어를 수지재로 봉지하여 형성된 봉지부 및 상기 서브스트레이트의 하면에 형성된 배선패턴에 융착된 다수의 도전성 볼로 이루어진 반도체패키지에 있어서,상기 제1반도체 다이와 제2반도체 다이 사이에는 상기 반도체 다이의 열을 외부로 방출시키고, 배선패턴 상호간의 전기적 상호 작용을 억제하기 위해 도전성 플레이트가 더 설치된 것을 특징으로 하는 반도체패키지.
- 제1항에 있어서, 상기 도전성 플레이트는 상기 제1반도체 다이와 제2반도체 다이 사이에 위치되는 제1플레이트와, 상기 제1플레이트에 연결된 동시에 제1반도체 외주연 하부로 경사져 형성된 경사 플레이트와, 상기 경사 플레이트에 연결된 동시에 그라운드 플랜과 도전성 비아로 연결된 소정 배선패턴에 연결되는 제2플레이트로 이루어진 것을 특징으로 하는 반도체패키지.
- 제1항 또는 제2항에 있어서, 상기 도전성 플레이트에는, 봉지 공정중 수지재가 상기 도전성 플레이트 내측으로 용이하게 흘러 들어 가도록, 다수의 통공이 더 형성된 것을 특징으로 하는 반도체패키지.
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0066108A KR100533763B1 (ko) | 2002-10-29 | 2002-10-29 | 반도체패키지 |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR10-2002-0066108A KR100533763B1 (ko) | 2002-10-29 | 2002-10-29 | 반도체패키지 |
Publications (2)
Publication Number | Publication Date |
---|---|
KR20040037561A true KR20040037561A (ko) | 2004-05-07 |
KR100533763B1 KR100533763B1 (ko) | 2005-12-06 |
Family
ID=37335860
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
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KR10-2002-0066108A KR100533763B1 (ko) | 2002-10-29 | 2002-10-29 | 반도체패키지 |
Country Status (1)
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KR (1) | KR100533763B1 (ko) |
Cited By (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100712499B1 (ko) * | 2004-07-09 | 2007-05-02 | 삼성전자주식회사 | 열 배출 효율이 증대된 멀티 칩 패키지 및 그 제조방법 |
KR100770934B1 (ko) * | 2006-09-26 | 2007-10-26 | 삼성전자주식회사 | 반도체 패키지와 그를 이용한 반도체 시스템 패키지 |
KR100908764B1 (ko) * | 2007-07-19 | 2009-07-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR101450761B1 (ko) * | 2013-04-29 | 2014-10-16 | 에스티에스반도체통신 주식회사 | 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법 |
WO2016101151A1 (en) * | 2014-12-23 | 2016-06-30 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
WO2024082332A1 (zh) * | 2022-10-19 | 2024-04-25 | 广东省科学院半导体研究所 | 带有散热板的多芯片互连封装结构及其制备方法 |
Families Citing this family (1)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR101787871B1 (ko) * | 2016-02-05 | 2017-11-15 | 앰코 테크놀로지 코리아 주식회사 | 반도체 디바이스 및 그 제조 방법 |
Family Cites Families (6)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US5977626A (en) * | 1998-08-12 | 1999-11-02 | Industrial Technology Research Institute | Thermally and electrically enhanced PBGA package |
JP2001102495A (ja) * | 1999-09-28 | 2001-04-13 | Toshiba Corp | 半導体装置 |
KR100649869B1 (ko) * | 2000-12-04 | 2006-11-24 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
KR100393099B1 (ko) * | 2000-12-26 | 2003-07-31 | 앰코 테크놀로지 코리아 주식회사 | 반도체패키지 |
KR100706505B1 (ko) * | 2000-12-27 | 2007-04-11 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 |
KR100429885B1 (ko) * | 2002-05-09 | 2004-05-03 | 삼성전자주식회사 | 열방출 특성을 개선한 멀티 칩 패키지 |
-
2002
- 2002-10-29 KR KR10-2002-0066108A patent/KR100533763B1/ko active IP Right Grant
Cited By (8)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR100712499B1 (ko) * | 2004-07-09 | 2007-05-02 | 삼성전자주식회사 | 열 배출 효율이 증대된 멀티 칩 패키지 및 그 제조방법 |
KR100770934B1 (ko) * | 2006-09-26 | 2007-10-26 | 삼성전자주식회사 | 반도체 패키지와 그를 이용한 반도체 시스템 패키지 |
US7902652B2 (en) | 2006-09-26 | 2011-03-08 | Samsung Electronics Co., Ltd. | Semiconductor package and semiconductor system in package using the same |
KR100908764B1 (ko) * | 2007-07-19 | 2009-07-22 | 앰코 테크놀로지 코리아 주식회사 | 반도체 패키지 및 그 제조 방법 |
KR101450761B1 (ko) * | 2013-04-29 | 2014-10-16 | 에스티에스반도체통신 주식회사 | 반도체 패키지, 적층형 반도체 패키지 및 반도체 패키지의 제조방법 |
WO2016101151A1 (en) * | 2014-12-23 | 2016-06-30 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
US9960104B2 (en) | 2014-12-23 | 2018-05-01 | Intel Corporation | Integrated package design with wire leads for package-on-package product |
WO2024082332A1 (zh) * | 2022-10-19 | 2024-04-25 | 广东省科学院半导体研究所 | 带有散热板的多芯片互连封装结构及其制备方法 |
Also Published As
Publication number | Publication date |
---|---|
KR100533763B1 (ko) | 2005-12-06 |
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