TW508825B - Semiconductor device and process of manufacturing the same - Google Patents

Semiconductor device and process of manufacturing the same Download PDF

Info

Publication number
TW508825B
TW508825B TW090110505A TW90110505A TW508825B TW 508825 B TW508825 B TW 508825B TW 090110505 A TW090110505 A TW 090110505A TW 90110505 A TW90110505 A TW 90110505A TW 508825 B TW508825 B TW 508825B
Authority
TW
Taiwan
Prior art keywords
film
oxide film
source
semiconductor substrate
region
Prior art date
Application number
TW090110505A
Other languages
English (en)
Inventor
Hidenori Morimoto
Alberto O Adan
Original Assignee
Sharp Kk
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sharp Kk filed Critical Sharp Kk
Application granted granted Critical
Publication of TW508825B publication Critical patent/TW508825B/zh

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66568—Lateral single gate silicon transistors
    • H01L29/66613—Lateral single gate silicon transistors with a gate recessing step, e.g. using local oxidation
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76202—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO
    • H01L21/76221—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using a local oxidation of silicon, e.g. LOCOS, SWAMI, SILO with a plurality of successive local oxidation steps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823814—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the source or drain structures, e.g. specific source or drain implants or silicided source or drain structures or raised source or drain structures
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8232—Field-effect technology
    • H01L21/8234—MIS technology, i.e. integration processes of field effect transistors of the conductor-insulator-semiconductor type
    • H01L21/8238—Complementary field-effect transistors, e.g. CMOS
    • H01L21/823864—Complementary field-effect transistors, e.g. CMOS with a particular manufacturing method of the gate sidewall spacers, e.g. double spacers, particular spacer material or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66492—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a pocket or a lightly doped drain selectively formed at the side of the gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7833—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's
    • H01L29/7835—Field effect transistors with field effect produced by an insulated gate with lightly doped drain or source extension, e.g. LDD MOSFET's; DDD MOSFET's with asymmetrical source and drain regions, e.g. lateral high-voltage MISFETs with drain offset region, extended drain MISFETs
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/665—Unipolar field-effect transistors with an insulated gate, i.e. MISFET using self aligned silicidation, i.e. salicide

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Insulated Gate Type Field-Effect Transistor (AREA)
  • Metal-Oxide And Bipolar Metal-Oxide Semiconductor Integrated Circuits (AREA)
  • Electrodes Of Semiconductors (AREA)

Description

508825 五、發明說明（1) 發明之背景 1.發明之領域 本發明與一種半導體裝置及其製造方法有關， 一 種含有一金氧半導體電晶體之LDD結構半導甘制 造方法有關。 虹衣置及其製 2 ·相關技術之說明
Ik著半導體積體電路之積體化日漸 金氧半導體電晶體需要進一步小型化。例如； 微未或半微米之閘長度可能要小至〇. 35 ^ -人 0· 18 //in。 u· 〇 或 較小之閘長度有利於高速操作，但盆合 ，減小臨界電壓（Vth)乃诸丨、 θ 成短波迢效應 # & f赘倣j區之有利接觸孔及低電阻。 抑制紐波道效應一般所知有一 . ％ 及2用輕度摻雜汲極（LDD)結構之1 ;，因\源極/汲極區 法就是在源極/汲極區及一何δ牯也有一種方 減少接觸電阻。 f電極表面上形成一矽化膜來 但按照閘長度小型化 若閘長度為〇.5〇至〇.3 ° ’源極/汲極區會較淺。例如 至150 nm，而閘長度若源極/汲極區之深度為2〇〇 會極小而約為8〇 nm。因二時，源極/汲極區之深度 Ϊ一石夕化犋時，需要滅少二在如此淺之源極"及極區上形 右矽基體之量大為減少日士，形成矽化膜所用矽基體之量，。 】達PN接點並使PN接點破穿f化膜會牙透源極/波極區而
五、發明說明（2) g有報告顯示，在電晶體源極/没極區表面上妒成 膜時，會產生-個約為100 長之波尖沿著源極 二/及極區延伸，因而增大源極/汲極區PN接點上之漏電電 流（見日本應用物理學會1 9 9 6年秋季會談摘要π第58 9頁1 、—f圖2所示，在源極/汲極區21上選擇性地生成一單晶或 複=矽層。然後在其上形成一鈦膜並加以熱處理而在單晶 或複晶矽層22表面上形成一矽化鈦膜23(見日本尚未審查曰曰 之Hex 10 (i 998 ) —92 949號專利申請）。按照此一方法，一即 使很多矽消耗於形成矽化鈦膜23，單晶或複晶矽層22仍可 供應石夕而防止矽化鈦膜23穿透源極/汲極區21。 但，在源極/汲極區21上選擇性地生成單晶或複晶矽層 22，單晶或複晶矽層22也澱積在閘電極以之側壁間隔物μ 上。所以矽化鈦膜23也形成於側壁間隔物25上而造成源極 /沒極區21與閘電極24間之短路。 再者，如圖3所示曾有人建議一種方法在矽基體32之一 凹部内放上一個閘電極31來形成有足夠厚度之源極/汲極 ^33(見日本尚未審查之Hei u ( 1 9 9 9 )_1 54749號專利申 叫）。按照此一方法源極/汲極區3 3可有足夠厚度而可防止 矽化膜3 4穿透源極/汲極區3 3。 但與在平面矽基體上形成之金氧半導體電晶體比較，如 此形成之電晶體會增加閘電極31與源極/汲極區32間之寄 生電容而對高速操作有不為影響。 此外，如圖4(a)至4(e)所示日本尚未審查之Hei n
m408 1 7號專利中請中曾建議一種方法在石夕在絕緣物 之基體之矽層41表面上形成一局部氧化矽（LOCOS) 胲 圖4(a))，該LOCOS膜42被蝕刻掉（圖4(b))而使波道 區43變薄（凹入之波道區，圖4(c))然後在基體整個表面上 形成「，屬膜45(圖4(d))而形成一矽化膜46(圖4(e))。因 為此法疋使用s〇i基體，源極/汲極區之深度可藉調整矽 ά之厚度來控制。如此以开》成源極/沒極區之普通步驟 即可形成較大深度之源極/汲極區4 4。 但當此法用於大基體時，必須嚴袼控制因熱處理而在源 極/汲極區内發生之雜質擴散以便調整源極/汲極區之深度_ 。再者，需要一個在閘電極上形成側壁間隔物之額外步驟 以便形成一輕度摻離汲極“卯）區來防止短波道效應及形 成石夕化膜來防止閘電極與源極/汲極區之短路。此外，因 為幵y成LDD區之普通步驟需要熱處理以便形成源極/汲極區 及在形成LDD區之離子植入後需要另一次熱處理以便形成 矽化膜，結果形成之LDD區在橫向擴散太多而會引起防止 短波道之不足。 本發明之簡要說明 本發，鑒於上述之問題而提出。本發明之一個目的是提 t、胃種同度可靠之半導體裝置能以較容易之技術，即使該 半$體裝置在源極/汲極區内包括一區及一矽化膜，來 有效防止短波道效應與短路並提供製造該半導體裝置之方 法0 按照本發明提供之半導體裝置含有：一個隔著一閘絕緣
第7頁 ^08825 五、發明說明（4) > 膜在一半導體基體上形成之閘電極及一個直表面上 化膜且形成於該半導體基心之源極/汲極區，石夕 J/汲極區有一其表面有—部分或全部傾斜之ld :原; 再者，按照本發明所提供製造一半導 下述步驟：在半導體基體上形成一衣置之方法已括 氧化膜；除去部分L0C0S氧化膜成而一在局/酋氧化石夕（L〇C〇S)之 凹處；隨著-閉絕緣膜在該凹户而在+ ¥體干基體上形成一 極與剩餘之L0C0S氧化蹬似*地 閘電極；以該閘電 源極/汲極區；至少在 ' .、、、、蔽罩進行離子植入而形成一 在閘電極兩邊下方之车^虽/及極區表面形成一矽化膜；及 從下面之詳細說明t:體裳置内形成區。 。但應瞭解該詳細說明可看出本發明之此等及其他目的 僅限於說明而已，因熟於歹^出本發明較佳實例之特定舉例 圍佈仍可從該詳細說明^此項技術者在本發明之精神與範 附圖簡介 有各種改變與修改。 圖1(a)至1(h)為說明制、生 分之斷面圖； 衣w本兔明半導體裝置實例主要部 •圖2為說明製造先前 , 卞命骽衣置主要部分之斷面圖 圖3為說明另一彭、生 面圖；及 前技術半導體裝置主要部分之斷
圖4(a)至4(e)為說明X 一 —_ x °先則技術半導體裝置主要
五、發明說明（5) 部分之斷面圖 較佳實例之說明 本發明之半導體梦 -間絕緣膜、要含有形成於-半導體基 半導體記憶裝置中體並無限制，只要是通 半導h n i中者其舉例包括諸如矽、鍺 千V肢及诸如鎵砷、銦鎵砷、 ^鳍 以矽基體為佳。在丰導μ其挪 '卒n寺之硬合半導體 該半導體基體可進一步内2形成-裝置隔 、層間絕緣膜等元件及包Ξ笔：體二電容器與 等。在半導體基體内最好形成’：,電路與半導 包以:H 最好備有裝置隔離膜， 、匕括局部氧化矽（L0C0S)氧化膜、溝道裝置 逼隔離膜等，其中以L0C0S氧化膜為 、、 ，閘絕緣膜之舉例包括氧化矽膜/氮化矽膜或其分 ’其厚度可約為2至1 0 nm。 刀 閘電極只要是以導電膜形成並無特別限制。例如 層或多層之單矽、無定形矽、聚矽等膜及諸如鋼、 屬以及諸如鎢、钽、鈦、鈷、白金等耐熱金屬與含 金屬之矽化物與聚矽化物等。其中最好以聚石夕，尤 有耐熱金屬者，在其表面形成一石夕化膜。閘電極之 約為5 0至2 5 0 nm。特別是若在閘電極表面形成;g夕化 該矽化膜/聚矽之厚度約為20至100 nm/50至2 5 0 nm 極表好形成於在半導體基體表面所形成之凹處内， 體上 之 常用於 堂°» 寺早元 。其中 離區。 電卩且器 體裝置 質區 其舉例 k淺溝 層之 m 可用單 症呂等金 有耐熱 其是含 厚度可 膜時/ 。閘電 下文中
第9頁
^V7〇〇z,J 發明說明（6) ___ 將有說明。如此閘雷士 凹處之半導體基體表面(:面之m;或低於或等於無 主表面。 表面）仁閘電極表面最好高於 源極/沒極區並無特 導體步詈之调托/ u制要其通常之功能為一车 ,D" /原極//及極區即可。最好能在半導㉟美靜# 成一 P或N型雜質槁朝* jg _ V脰基體内形 雜質之錄+=2 ί 導電類型與植人源極/汲極區內 本隹貝之種類與濃度以及源極 =£内 導體基體之特徵而適當選擇。L之冰度均可視所獲半 ^原極/汲極區在其接近閘電極之 LDD區可在源極/汲極區 有LDD Q。該 形成。對稱之LDD區最好彤& Μ货k / 梆A非對％方式 F々主I 野士成於源極/汲極區之兩邊。τ nn
&之表面可部分或全部傾斜·。 ^ LDD 係指LDD區有一部分或全邱盘主'文：所稱<「傾斜」-詞 qnn「i ^王邛與+導體基體主表面有一钭择 莫麵古甘丄ώ ^ 傾斜表面’亦即平面本
之斜度或傾斜半導體基體本身之斜度LDD &之亦隹貝ί辰度並無特別限制’ σ LDD 配置LDD區且可楛古雷γ月& 要疋在源極/汲極區邊緣 、盾代 防止短波道效應即可。 源極/汲極區在其表面置有一 有耐熱金屬之石夕化膜，其 至。“石夕^匕膜最好是 ^#^^80^.150 π,(^ρ，130/6 0 厚度）。 即在矽化膜下雜質擴散層之 在源極/沒極區内，在閘電搞 有-在半導體基綱化膜:之7面=半ί體， 波道區表面間之高度差並無特阳：迢品 该介面與 J限制。此一位置關係之達
JVJOOZ.J 五、發明說明（7) ==式提供半導體基體材料或在-區域内戮積-、：：體材料用於形成源極/汲極區或在一區域二 ;) :、將一二用於在半導體基體表面上形成閑電極:波Ϊ ^ 一W 處理方式組合進行。但為方便起見最好是蝕 人品2内將成為半導體基體表面内波道區之部 該凹處。 又、匕1刀而形成 發明製造該半導體裝置之方法，首先在半導體美 部氧化鄭0S)氧化膜。該確定波道區位土 之LOCOS虱化膜最好根據欲獲得之半導體裝置之安排 ，積。例如以所謂L0C0S方法來提供L〇c〇sft化膜， f導體基體整個表面上形成一氧化矽膜與一氮化矽膜，在 氮化矽膜上形成一欲有組態之開口並加以氧化。L〇c〇s氧 之厚度並無特別限制，可為大約100至30 0 nm。在半 &版f體上形成LOCOS氧化膜前最好在半導體基體一個欲 有之區域形成一裝置隔離膜。該裝置隔離膜可用諸如 LOCOS ’溝道裝置隔離，淺溝道隔離（STI)等已知方法形成 ^其，以LOCOS為佳。若在locos氧化膜之前提供裝置隔離 膜’該LOCOS氧化膜之厚度最好小於裝置隔離膜之厚度。 然後將一部分L〇c〇S氧化膜除去而在半導體基體内形成 =處。除去之部分L〇c〇s氧化膜最好在其中央部分或除 鳥高外之部分或包括一部分鳥嘴之部分。如此該凹處可在 半&體基體已形成L〇c〇S氧化膜之區域内且至少保留整僻 或°卩分鳥嘴。除去部分LOCOS氧化膜之工作最好利用用於 形成LOCOS氧化膜之氮化矽膜進行各向異性蝕刻來完成。
第11頁 五、發明說明（8) 再者’閘電極是P基 ' 以諸如熱氣化 個閘絕緣膜埋入該凹處。、，s 體整個表面積等已知方法形成：半IS 積等已知方法在如化學氣相殿積、機射、 或加以姓刻而將間電接著將之圖；化 形最好是利用在前 里^丰導體基體上之凹處。似 膜來形成閉絕緣膜^電 氧化膜之氮化石夕 之表面露出為止。在此 "再進仃银刻直至氮化石夕膜 成閘絕緣膜並殺積間中可能預先僅在凹處底部形 刻。此外，在此步去圖案化及一 氮化矽膜。 除去用於形成LOCOS氧化膜之 接著利用閘電極與剩餘 子植入而形成源極/沒極;之。L〇^ ，電極及剩餘咖氧化膜厚度適當；二 5° t μV/!fη^111 f ^^40 kev^^^^ 5x10 離子/平方公分之齋丨吾始
Pil t'i έ^ι 9 π ^ ς η 1 y 里植入。如硼、叩2等之ρ型雜質 ^以約20至50 keV之能及約！ wxl 〇15離子/平方公分之劑 置植入。 接著至少在源極/汲極區表面上形成一石夕化膜。若間電 極是以矽所製時，不但在源極/汲極區表面而且也在閘電 極表面形成矽化膜。矽化膜是以所謂矽化物技術形成，亦 即在半導體基體整個表面上澱積橫成矽化膜之金屬膜，然 後加以熱處理而形成矽化金屬並除去未反應之有矽金屬膜 。也可以使用將構成矽化膜金屬之離子選擇性地置入一區 第12頁 508825 五、發明說明（9) 域之方法來形成矽化膜並進行熱處理。構成矽化膜之金屬 膜可用濺射、蒸汽澱積、EB等方法形成，其厚度約為20至 5 0 nm。熱處理可用RTA以大約6 5 0至850 °C進行約1至2分鐘 或約1 0至5 0秒或約3 0秒。可用酸性或鹼性溶劑以濕蝕刻等 方式除去未反應金屬膜。可用離子植入等方式進行選擇性 植入金屬離子。矽化膜之厚度並無特別限制，約為2 〇至5 0 nm即可。
接著在閘電極兩邊下方之半導體基體内形成LD])區。可 用離子植入等方式形成LDD區。可在仍有剩餘LOCOS氧化膜 之情形下進行離子植入但最好是在除去剩餘1〇(：〇8氧化膜 後。離子植入是以一植入能及根據所剩下L0C0S氧化膜大 小^，厚度而適當調整之劑量來進行。例如磷、砷待n型 雜貝疋在除去LOCOS氧化膜後植入，其植入能約為1〇至25 而其劑量約為2至5)(1〇12離子/平方公分。若為硼、卯 等Ρ型雜質時，植入能約為2〇至5〇 keV而劑量 2 IIP離子/平方公分。 主bx 剩餘之LOCOS氧化膜是用酸性或驗性溶液濕餘、 炎各向同性或各向異性乾#法除去。其中 ^射 為佳。若子苜春P 士 & w τ从旱乙蝕！ 聽S氧化膜上方^置門隔離膜日寺，最好使用僅在所剩餘 膜不會被除去方有—開口之蔽罩進行姓刻而使褒置隔離 面可選擇性在上述步驟前或其中或其後進行表 層間絕緣膜、接觸者’形成層與 接觸孔、接線層等一個或兩個步驟可在上、求 五、發明說明（10) 乂驟後統合進行而完成該半導體裝置。 面將參看附圖對本發明製造該半導體裝置方法之實例 加以詳細說明。 直力π <只扒 p i 所不，在矽基體1上首先形成—個大約40〇 nm Z , 虱化膜4做為裝置隔離膜。然後進行離子植入而 形成池區2及一 n池區3。 nm ΐ : ί圖1 (b)所示在矽基體la整個表面上形成-大約10 二氧匕矽膜5與—大約1〇〇㈣厚之氮化 石夕膜“乂照相石版術製成圖案並加以兹 二= 間石夕基體】想要之區域上方形成一些開口弟二C = ':膜7石夕Λ6做為蔽罩而提供第二L0C0S氧化膜7。該第二 Γ ΓΛ弟丰—氧化膜4為薄。按照第二locos氧化膜7之厚 :二ίΓ驟中確定源極/没極區與波道區間將要形成 =问度差。在此階段，第二L0C0S氧化 200 rnn而使得最終之高度差約為1〇〇韻。子度疋為大，力 然後如圖1 (C)所示，仍以氮化矽膜6做為蔽罩來對第-化膜7加以各向異性姓刻直至卿J = 此“ 矽基體1表面將在後來步驟中用做波道區8。在 钱去而仍留在該處。隨後將波道區8加 嘴匕 以HF溶液進行濕餘刻來除去犧 11牲式乳化，再 成之損壞。 m牲虱化朕以便除去蝕刻所造 接下來如圖1(d)所示，以熱氧化在波道區8上 ， nm厚之閘絕緣膜1 〇。接著在矽基 /成、力. /岙整個表面上澱積約4〇() 五、發明說明（11) nm厚之聚矽層而將已有氮化矽膜6 石夕膜6上之聚石夕層完全被除去為止。再、巧直至氮化 2〇〇㈣厚之閘電極u， $皮逼區8内埋入約 P池區2及n池區3進行雜質之離子植入再在、9做為蔽罩對 進行熱處理而形成源極/&極區12，fF以850t 入離子步驟中，在鳥嘴9之直接下方並不』^ :。在植 :HF溶液除去石夕基體！上所形成之氧化石夕膜『貝。 方式在矽基體1之整個表面上形、，，以濺射 μ熱處理而在閘電極n與源、極/没極區膜並 厚之石夕化銘膜13，如圖1⑴所示。然後除去未反應 極11做為蔽罩來植入低濃度雜質而形Z (g)所示以間電 (LDD)區14。 而形成輕度#雜汲極 ，後，化學氣相殿積（CVD)法在石夕基體i上形成一約8〇〇 :1Γ:::::1 再以照相石印法在氧化石夕臈15形成接觸 體裝=r蝕』及連接層16。於是如圖丨⑻所示完成該半導 1如此獲付之半導體裝置中，在閘電極丨丨與源極/汲極 品之表面上提供矽化膜1 3。此外’ LDD區丨4之表面有一 部分傾斜且源極/汲極區12與矽化膜13間之介面可位於在 閘電極η立即下方高出半導體基體表面之處。如此源極/ 508825
508825 發明說明（13) f肢上形成-LDD區。如此閘電極可自動對準 表面之凹處内而可不必變換閘之長度。此 > 肢基肢 區之形成可較波道區有足夠之厚度而防止石夕化没極 極/汲極區内之PN接點並防止增大PN接 妾觸到源 此外’因剩餘之L〇C〇S氧化膜被用 。 可省掉形成側壁間隔物之步驟並確實防·"間隔物而 汲極區間之短路’目而簡化製造步驟。"電極與源極/ 再者’因LDD區是在源極/汲極區及石夕化… ，LDD區除在形成時之熱處理外不栌 、y 才形成 此在LDD區内並無低濃度雜質之橫=壬何熱處理，因 -步小型化，仍可製成高度可靠之 雕壯口 Y使再進 短波道效應。 . ¥版衣置且不會增大 尤其是若L0C0S氧化膜是部分或全部 刻掉而留下鳥嘴或剩餘之L0C0S氧化膜曰Ό向異性方式蝕 及形成LDD區前被除去時，LDD區之开/士疋在形成矽化膜後 簡化製造步驟減少製造成本。 "更適合與方便而可 508825
_案號 90Π0505_年1月5曰_修正 I 圖式簡單說明 元件符號說明
1 矽基板 2 p -池區 3 η -池區 4 第二L0C0S氧化膜 5 氧化砍膜 6 氮化矽膜 7 第二L0C0S氧化膜 8 波道區 9 鳥嘴 10 閘絕緣膜 11 閘電極 12 源極/汲極 區 13 石夕化銘膜 14 L D D 區 15 氧化矽膜 16 連接層 21 源極/沒極區 22 矽層 23 石夕化鈦膜 24 閘電極 25 侧壁間隔物 31 閘電極 32 梦基板 33 源極/汲極 區 34 矽化膜 41 矽層 42 L0C0S 膜 43 波道區 44 源極/汲極區 45 金屬膜 46 石夕化膜 /0941-910828.ptc 第18頁

Claims (1)

  1. 508825 案號 901 10505 彳丨年 月 A 曰 修正 々、申請專利範圍 1 . 一種半導體裝置，含有：隔著一閘絕緣膜在半導體基 體上形成之閘電極及一在其表面有一矽化膜而形成於半導 體基體上之源極/波極區， 其中該源極/;及極區有一其表面部分或全部傾斜之輕 度摻雜汲極（L D D )區及在閘電極下方高出該半導體基體表 面處位於半導體基體與該源極/汲極區矽化膜間之介面。 2 .如申請專利範圍第1項之半導體裝置，其中該閘電極 之表面高出半導體基體無凹下處之表面。 3 .如申請專利範圍第1項之半導體裝置，其中該L D D區對 該半導體基體無凹下處之表面而言呈現部分或全部傾斜且 該LDD區是形成於本身有一傾斜度之平面半導體基體或本 身有一傾斜度之傾斜半導體基體之一傾斜表面上。 4 .如申請專利範圍第3項之半導體裝置，其中該L D D區是 形成於半導體基體之一傾斜表面上。 5 .如申請專利範圍第1項之半導體裝置，其中該局部氧 化矽（LOCOS)氧化膜之厚度為100至3 0 0 nm。 6 · 種製造半導體裝置之方法，包括下述步驟 在一個半導體基體上形成一LOCOS氧化膜； 除去部分LOCOS氧化膜而在半導體基體上形成一凹處 隔著一閘絕緣膜在該凹處内埋入一閘電極； 以該閘電極及剩餘之L 0 C 0 S氧化膜為蔽罩進行離子植 入而形成一源極/汲極區； 至少在該源極/汲極區之表面形成一矽化膜；及
    70941-91082«.pro 第19頁 508825 案號 901 10505 ___ϊ!±Λ Β } a__ - 六、申請專利範圍 在閘電極兩邊下方之半導體裝置内形成一 L D D區。 7 .如申請專利範圍第6項之方法，其中該L 0 C 0 S氧化膜是 利用用於形成L 0 C 0 S氧化膜之蔽罩來形成且使用用於形成 該LOCOS氧化膜之蔽罩來除去一部分LOCOS氧化膜。 . 8 .如申請專利範圍第7項之方法，其中該L 0 C 0 S氧化膜是 以各向異性蝕刻方式除去而使得部分或全部鳥嘴仍予保留 ^ 〇 9 .如申請專利範圍第6項之方法，其中該剩餘L 0 C 0 S氧化 膜是在形成秒化膜後及形成L D D區前被除去。 1 0 .如申請專利範圍第6項之方法，其中L 0 C 0 S氧化膜之 厚度為100至3 0 0 nm。 _
    70941-91082^.pfc 第20頁
TW090110505A 2000-05-02 2001-05-02 Semiconductor device and process of manufacturing the same TW508825B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2000133752A JP3490046B2 (ja) 2000-05-02 2000-05-02 半導体装置及びその製造方法

Publications (1)

Publication Number Publication Date
TW508825B true TW508825B (en) 2002-11-01

Family

ID=18642172

Family Applications (1)

Application Number Title Priority Date Filing Date
TW090110505A TW508825B (en) 2000-05-02 2001-05-02 Semiconductor device and process of manufacturing the same

Country Status (6)

Country Link
US (1) US6492696B2 (zh)
EP (1) EP1152470B1 (zh)
JP (1) JP3490046B2 (zh)
KR (1) KR100393139B1 (zh)
DE (1) DE60132129T2 (zh)
TW (1) TW508825B (zh)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100355034B1 (ko) * 1999-07-15 2002-10-05 삼성전자 주식회사 선택적 에피택셜 성장층을 가진 반도체 장치 및 그 소자분리방법
US6573143B1 (en) * 2001-11-28 2003-06-03 Chartered Semiconductor Manufacturing Ltd. Trench transistor structure and formation method
US6677646B2 (en) * 2002-04-05 2004-01-13 International Business Machines Corporation Method and structure of a disposable reversed spacer process for high performance recessed channel CMOS
US7494894B2 (en) * 2002-08-29 2009-02-24 Micron Technology, Inc. Protection in integrated circuits
US6930030B2 (en) * 2003-06-03 2005-08-16 International Business Machines Corporation Method of forming an electronic device on a recess in the surface of a thin film of silicon etched to a precise thickness
KR100597459B1 (ko) * 2003-12-31 2006-07-05 동부일렉트로닉스 주식회사 반도체 소자의 게이트 전극형성방법
JP4945900B2 (ja) * 2005-01-06 2012-06-06 ソニー株式会社 絶縁ゲート電界効果トランジスタおよびその製造方法
KR100668856B1 (ko) * 2005-06-30 2007-01-16 주식회사 하이닉스반도체 반도체 소자의 제조방법
US8258057B2 (en) * 2006-03-30 2012-09-04 Intel Corporation Copper-filled trench contact for transistor performance improvement
KR100842483B1 (ko) * 2006-12-28 2008-07-01 동부일렉트로닉스 주식회사 반도체장치의 제조방법
FR2995135B1 (fr) * 2012-09-05 2015-12-04 Commissariat Energie Atomique Procede de realisation de transistors fet
CN109300789B (zh) * 2017-07-25 2021-07-09 中芯国际集成电路制造(上海)有限公司 半导体结构及其形成方法
US10861950B2 (en) 2017-11-16 2020-12-08 Samsung Electronics Co., Ltd. Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch
US10910313B2 (en) 2017-11-16 2021-02-02 Samsung Electronics Co., Ltd. Integrated circuit including field effect transistors having a contact on active gate compatible with a small cell area having a small contacted poly pitch

Family Cites Families (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05152320A (ja) * 1991-11-30 1993-06-18 Ricoh Co Ltd Ｌｄｄ構造の半導体装置とその製造方法
US5567966A (en) * 1993-09-29 1996-10-22 Texas Instruments Incorporated Local thinning of channel region for ultra-thin film SOI MOSFET with elevated source/drain
KR950021242A (ko) * 1993-12-28 1995-07-26 김광호 다결정 실리콘 박막 트랜지스터 및 그 제조 방법
JP2906971B2 (ja) * 1993-12-30 1999-06-21 日本電気株式会社 半導体記憶装置の製造方法
KR0162673B1 (ko) * 1994-01-11 1998-12-01 문정환 반도체 도전층 및 반도체소자의 제조방법
US5529942A (en) * 1994-06-23 1996-06-25 United Microelectronics Corp. Self-aligned coding process for mask ROM
JPH08148561A (ja) * 1994-11-16 1996-06-07 Mitsubishi Electric Corp 半導体装置とその製造方法
US5656519A (en) * 1995-02-14 1997-08-12 Nec Corporation Method for manufacturing salicide semiconductor device
US5672524A (en) * 1995-08-01 1997-09-30 Advanced Micro Devices, Inc. Three-dimensional complementary field effect transistor process
JPH0992728A (ja) * 1995-09-21 1997-04-04 Mitsubishi Electric Corp 相補型ｍｏｓ電界効果トランジスタおよびその製造方法
JP3734559B2 (ja) * 1996-03-15 2006-01-11 富士通株式会社 半導体装置の製造方法
JPH1092949A (ja) 1996-09-10 1998-04-10 Hitachi Ltd 半導体集積回路装置およびその製造方法
JP3382840B2 (ja) * 1997-05-23 2003-03-04 シャープ株式会社 半導体装置の製造方法
JPH11154749A (ja) 1997-09-22 1999-06-08 Nippon Steel Corp 半導体装置及びその製造方法
KR100314708B1 (ko) * 1998-07-03 2002-04-24 윤종용 이피롬셀이내장된반도체소자의제조방법
US6261909B1 (en) * 1999-01-05 2001-07-17 Advanced Micron Devices, Inc. Semiconductor device having ultra shallow junctions and a reduced channel length and method for making same

Also Published As

Publication number Publication date
US6492696B2 (en) 2002-12-10
DE60132129T2 (de) 2008-12-11
KR100393139B1 (ko) 2003-07-31
EP1152470A2 (en) 2001-11-07
JP2001320044A (ja) 2001-11-16
KR20010100915A (ko) 2001-11-14
EP1152470B1 (en) 2008-01-02
EP1152470A3 (en) 2004-02-25
DE60132129D1 (de) 2008-02-14
JP3490046B2 (ja) 2004-01-26
US20010039092A1 (en) 2001-11-08

Similar Documents

Publication Publication Date Title
TW408424B (en) Semiconductor device with silicon replacing structure on the insulated layer and the manufacture method thereof
TWI235457B (en) Fin FET devices from bulk semiconductor and method for forming
EP0978141B1 (en) Method of making nmos and pmos devices with reduced masking steps
TW498557B (en) A method of manufacturing a semiconductor device
TW508825B (en) Semiconductor device and process of manufacturing the same
TW201013758A (en) Semiconductor device and method for making semiconductor device having metal gate stack
TW200406886A (en) Semiconductor constructions
TW548703B (en) Manufacturing method of semiconductor device
US20070187774A1 (en) Manufacturing method for an integrated semiconductor structure and corresponding integrated semiconductor structure
TW533596B (en) Semiconductor device and its manufacturing method
JP2001217320A (ja) 自己整列されたウェルバイアス領域を有するモストランジスタ及びその製造方法
TW479280B (en) A method of manufacturing a semiconductor device
TW200415786A (en) Semiconductor device and method for forming
JPH09129752A (ja) Ｃｍｏｓ集積回路の製造方法
JP4491858B2 (ja) 半導体装置の製造方法
TW402818B (en) Semiconductor device and method for manufacturing the same
US4514893A (en) Fabrication of FETs
US20060163661A1 (en) Selective doping and thermal annealing method for forming a gate electrode pair with different work functions
TW455997B (en) A semiconductor device and a method of producing the same
TW557544B (en) Semiconductor device and method of fabricating the same
JP2000243979A (ja) 半導体装置及びその製造方法
US20040094797A1 (en) MOS transistor having short channel and manufacturing method thereof
TW200537649A (en) A semiconductor device
JPS6239549B2 (zh)
JPH11238807A (ja) 半導体集積回路装置

Legal Events

Date Code Title Description
GD4A Issue of patent certificate for granted invention patent
MM4A Annulment or lapse of patent due to non-payment of fees