200537649 九、發明說明 【發明所屬之技術領域】 本發明是有關於一種半導體元件，且特別是有關於一種 互補式金氧半導體電晶體之具凹口間隙壁。 【先前技術】 在今曰，互補式金氧半導體（c〇mp丨 meta|_oxide-semiconduct〇r，CM〇s)技術是一個用來製造 超大型集積電路的主流技術。在過去十年間，半導體結構在 尺寸上的縮減使得半導體晶片在速度、效益、電路密度和單 位功能的成本上均得到顯著的進步。然而’顯見的挑戰在於 面對CMOS元件在尺寸上持續的縮減。 例如，當CMOS電晶體的閘極長度縮減時，源極和汲 極區域和通道的作用增加，目而影響通道電位和閘極。因 此，具有短通道的電晶體需承受關於閘極無法實質上控制通 道開和關狀態切換的問題。像這種伴隨電晶體短通道而生的 閑極控制下降的現象稱之為短通道效應。 一種減少源極和汲極對通道及閘極的影響的方法是在 通道區域引入額外的雜質’雜質的電性和源/汲極之佈植的 電性相反。例如，P型金氧半導體（P-type metal-oxide_semic〇nduct〇r，pM〇s) f 晶體—般係形成於 n-型矽基材之上(或p_型矽基材上之η·型井上）。源，汲極區 域係藉由以閘極為罩幕，在基材上進行ρ型雜質佈植而形 成於基材之上。為了減少短通道效應，雜質區域，一般稱之 200537649 為晕狀佈植（ha丨〇 implants)或口袋注入（卩3^响 _如〇ns)，係在形成延伸源/汲極之前在源/沒極區域的位 置植入額外的n-型雜質而形成的。暈狀佈植一般係以傾斜 的角度將雜質植入基材表面而將高濃度雜質植入在問極下 方的部分。然後以一垂直角度在基材表面進行—型雜質 $植以形成延伸源/汲極。額外的間隙壁即離子佈植可用來 完成源/汲極區域的製程。 為了控制暈狀佈植的濃度和深度，會試圖使用一且凹口 結構作為罩幕之用。如果提高植人的能量或角度，—個位於 閘極基部的凹口或具凹口結構可以使位於閘極下 :植的^部的穿透度提高，而無須增加所需的離子佈植深 二右有人3圖使用具凹口_極，此_間極沿著基材表面 ^凹：士厚度較薄。這樣的結構一般而言不亦控制閑極的 长度，換g之，及不易控制閘極的電性。 另有人試圖在閘極側壁形成薄的 壁一般係以氮切覆蓋氧切而成的間隙 氮化矽-tL “ 吨城错由-乾式蝕刻圖案化 其夕4膜’此一圖案化之氮化石夕薄膜在接續濕式蝕刻沿著 ^ W㈣㈣氧化㈣t程中係作為硬 的製程在閘極底部形成一凹口。凹口 :由乂上 —複口之⑽⑦層及氧㈣層的厚度所決定，凹口 疋源/汲極佈植侧部起點。 又，、 疮,H — 的回度僅係由氧化矽層的厚 度所決疋。凹口的寬度和高度 A佶田+Λ 皮〜寻軍狀佈植的最終形狀。因 = 用兩層來形成具凹口之間隙壁，本質上這樣的製 -’，特別是利用氮化石夕及氧化石夕的厚度來決定^口的寬 6 200537649 度及後續源汲極延伸佈植、暈狀佈植及閘極的相關部分。進 一步而言’使用雙層或多層氧化矽和氮化矽來形成具凹口之 間隙壁限制了凹口的高寬比’凹σ的高寬比係為暈狀佈植條 件之- ’可用來決定暈狀輪廓的側部穿透度。同樣的，對源 以極佈植製㈣言多層具凹口之間隙壁會造成較大的佈植 •罩幕而導致重疊區域縮小和高阻抗。 — 因此’需要—個具凹口之間隙壁來改善暈狀佈植製程和 鲁延伸源/汲極佈植製程。 【發明内容】 前述的和其他問題一般均可藉由本發明的實施例之揭 露來減低、解決或迴避並達成技術上的進步。本發明的實施 例係提供-具凹口之間隙壁以在半導體元件的製造過程中 控制軍狀佈植製程和延伸源/汲極佈植製程。 在本發明—實施例中’提供—半導體㈣，此半導體元 # :具有-基材及位於基材上之閘極。一第一離子佈植罩幕沿 著4極的側邊而形成，因而需移除部份係位於基材上之此第 一離子佈植罩幕。-第-離子佈植區域位於基材之上具有第 離子里匕、雜質，其中第一離子佈植罩幕係作為以一傾斜角 j基材表面進行離子佈植料幕。—第二離子佈植區域位 、土材之上具有第二離子型態雜質’其中第一離子佈植罩幕 =作為以-垂直角度在基材表面進行H子佈植的罩 之後’額外的間隙壁沿著第一離子佈植罩幕的側邊形成 且進行一額外的離子佈植。 7 200537649 在本發明另一實施例中，提供一半 元件沿閘極設置之具凹口之間隙- ’ 導體 於閘極兩側，且位於基材表面# ”土 乂成 入—m 表面和閘極側壁間的轉角的間隙壁 :?全或部分移除。-第二間隙壁沿著具凹口間隙壁而形 二前述另-實施例中，提供形成—半導體元件的方法。 一閘極形成於一基材之上，一第一 ^ A 弟離子佈植罩幕沿著閘極的 侧邊而形成，因而需移除部份位於美 罢苴 咕 彳於基材上之此第一離子佈植 罩幕。以第一離子佈植罩幕為罩幕 二w |θ旱参以一傾斜角度在基材表 面進行一第一離子佈植。以一垂直角许 直角度對基材表面進行一第 二離子佈植。之後，形成額外的罩幕 子佈植。 罩幕…仃-額外的離 在前述另-實施例中’提供另—形成—半導體元件的方 =-第-層形成覆蓋於基材及閉極之上。一第二層形成覆 盖第-層。由第二層形成一間隙壁罩幕以及執行一餘刻製程 以圖案化第-層，沿著基材表面部分第—層被移除。移除間 隙壁罩幕以及以一傾斜角度對基材表面進行一第—離子佈 植。以一垂直角度對基材表面進行—第二離子佈植。之後， 形成額外的罩幕，以及進行一額外的離子佈植。 【實施方式】 本實施例的製造和使用均詳細討論於後。值得讚賞的是 本發明提供許多合用的發明概念’而這些發明概念均可由； 泛且多樣化的說明書内容來具體化。本發明實施例之討論雖 8 200537649 僅描述特別的方式來實施和使用本發明，然其並非用以限定 本發明。 第1a圖至第1i圖係㈣根據本發明較佳實施例所揭露 之在通道區具有暈狀佈植的電晶體的製造方法。特別要指出 的是本實施例僅以在p型基材形成之N型金氧半導體 (N-type meta|_oxide_semic〇nduct〇r’ Nm〇s)電晶體為例來 討論。習知此技術之人當可在瞭解本發明所做得揭露之後等 效應用於PMOS電晶體的製造之上。進_步而言，在此揭 露的製程將可運用於在單一基材上製造一或多個四⑽和 一或多個NMOS。 =參見第1a@ ’ —晶圓⑽包括—具有淺溝渠隔離結 、閉介電層114和間極層116形成於其上之基材 立 1〇。在較佳實施例中，基材110包括具有卩井118形成於 ㈣=㈣基材。其他材質，例如錯、石夕鍺合金或其他類 二的材I均可選擇性使用作為基材110。可替換地，石夕基材 可以為一絕緣層上有矽基材的活性層或是—多層結 例如形成在塊狀矽基材上的矽鍺層。 閉^層m包括氧切、氮氧切、氮切、含 介電係數金屬氧化物或其任意組合。氧化石夕閘極介 :層二可以例如’氧化製程’如濕式或乾式熱製程來形 m佳實施例中，間介電層114的厚度約介於1〇埃至 ，極層116包括導體材質，例如金屬（如纽、欽、翻、 -，、白銘、給、釕）、金屬石夕化物（如石夕化欽、石夕化始、 200537649 矽化鎳、矽化鈕）、金屬氮化物（如氮化鈦、氮化钽）、摻雜 多晶矽、其他導體材質或其任意組合。舉例來說，可以先沉 積非晶矽再以再結晶形成多晶矽。在較佳實施例中，閘極是 夕曰a石夕，以低壓化學氣相沉積沉積厚度介於2〇〇埃至2〇〇〇 埃’較佳為1〇〇〇埃之摻雜或未摻雜多晶矽以形成閘極116。 請參見第1b圖，第1b圖繪示第1a圖的晶圓1〇〇在閑 介電層114和閘極層經圖案化後分別地形成閘介電12〇 和閘極122。閘介冑12〇和閘極122可藉由f知的微影技 術來圖案化。一般而言，微影製程包括旋塗一光阻材質，然 後加上光罩，再做曝光和顯影。在圖案化光阻罩幕之後，執 订非均向蝕刻製程以移除第彳a圖中閘介電層1i4和閘極 層116不要的部分以形成如第㈣所示之閘介電12〇和閘 請參見第1 c圖 第 c圖繪示在形成第一介電層12 和第-介電層128之後的第1b圖的晶圓1〇〇。第一介電^ 酸趟包括以以低壓化學氣相沉積技術，以四乙基偏与 孤 〇S)和氧氣為前驅物形成之氧化矽。其他材質， 丄t實矽、矽和其任意組合或類似材質均可適用。4 歹、，第一介電層126的厚度約介於1()埃至15| 二a，但較佳的厚度係為1〇〇埃。值得注意的是，第一 厚度如同定義凹口最低高度般之定義具凹口㈣ 第-介電層128較佳係包括氮化矽（引義) 匕括以以化學氣相沉積技術，以矽烷和氨氣為前驅物形成之 200537649 ，化矽。其他材質’例如s丨高之外的含氮層，如 氮氧化矽SiOxNv，式甘7立，人 y 中，第-介電/128 使用。在較佳實施例 第一，1電層128的厚度約介於50埃至200埃之間。 …請參見第㈣，圖案化第二介電層128(第1〇圖）以 $成用於形成具凹口間隙壁的具凹口間隙壁罩幕咖。 ，佳實，例中，第二介電層128係為Si3N4,第二介電層12: 、°、藉由執##均向乾式蝕刻來進行。要注意的是形成第 * :介電層128的材質和形成第一介電層126的材質需具有 同的蝕刻選擇比。因此，在以蝕刻移除其中一層時另一層相 對較不受影響。 曰 請參見第1e圖，第1e圖係繪示第一介電層126進行 圖案化形成具凹口間隙壁132之後之第1d0之晶圓1〇〇。 第一介電層1 26的蝕刻係藉由一稀釋之氫氟酸溶液進行一 時間控制均向濕蝕刻製程。凹口的高度係由第一介電層的厚 度、第一介電層的蝕刻速率和蝕刻期間來決定。 鲁 如第1e圖所示，藉由一均向蝕刻製程移除第1d圖所 不之第一介電層126位於具凹口間隙壁罩幕彳3〇下方的部 分以形成具凹口間隙壁。凹口的寬度係由第一介電層126 所決定而凹口的高度係由不同的蝕刻期間所控制。進一步而 言，第1e圖顯示一種情形是第一介電層126被完全移除並 暴露出閘極1 22。在其他情形，部分第一介電層彳26仍殘 留在閘極1 22的側壁上。這是隨需要而定的，例如，較佳 是用來控制植入的深度和角度或保護閘極i 22或閘介電 120免於後續蝕刻製程或其他製程的傷害。 200537649 更進一步值得注意的是，若閘介電1 20和具凹口間隙 壁1 32均是氧化矽材質的時候，用來形成具凹口間隙壁】μ 的蝕刻製程可能會移除部分閘介電1 20因而改變其電性。 因此，需要使用不同的材質來形成閘介電1 20和具凹口間 隙壁1 32或是使用使用在閘介電1 20和具凹口間隙壁1 μ 之間具有高蝕刻選擇比的蝕刻製程。例如，使用高介電係數 材質來形成閘介電1 20及以低壓化學氣相沉積氧化石夕形成 φ具凹口間隙壁1 32。在此情形下.，用來形成具凹口間隙壁 132的蝕刻製程對閘介電12〇及具凹口間隙壁132具有極 高的#刻選擇比。在蝕刻製程之後可以選擇性的執行一回火 製程以修復閘介電1 20的損傷。 第1 f圖係繪示移除第1 e圖具凹口間隙壁罩幕1 3〇及形 成佈植區域1 36之後之第1 e圖之晶圓1 00。藉由使用磷酸 水溶液的均向蝕刻製程移除氮化矽具凹口間隙壁罩幕，3〇 而不會餘刻氧化矽材質之具凹口間隙壁。無可諱言的習知此 φ 技術者均能同意，藉由在形成佈植區域136之前先移除氮 化石夕具凹口間隙壁罩幕13〇,凹口的寬度單獨由具凹口間隙 壁132的寬度來決定，這比習知運用多層結構更容易控制。 在實施例中係形成一 NMOS，如第1f圖所示以一傾斜 角度對基材進行p型雜質的離子佈植以形成佈植區域 136。例如以5keV至5〇keV的能量及劑量約ιχι〇13至 5X1 〇14 (原子/平方公分）的二氟化硼離子佈植以形成佈植 區域1 36。可以選擇性的使用硼、銦或類似的材質進行佈植 製程。為了要形成P〇MS，會使用η型摻雜，例如磷、砷 12 200537649 銻或類似的材質進行佈植製程。 習知此技術者均同意可利用佈植的角度、劑量和能量等 級來控制佈植區域1 36的的深度和側部的大小。因此，可 以為了特定的應用和閘極長度來定做佈植區域1 的大小 和密度。 • 第μ圖係繪示形成源/汲極延伸區域138之後之第1e 圖之晶圓100。在實施例中係形成一 nm〇s，如第ig圖所 籲示以一垂直角度對基材進行n型雜質的離子佈植以形成源/ 汲極延伸區域138。例如以1keV至5keV的能量及劑量約 5X1014至3X1 G15(原子/平方公分）的珅離子佈植以形成源 /沒極延伸區域138。可以選擇性的使用磷、綈或類似的材 質進行佈植製程。為了要形成P0MS，會使用p型捧雜， 例如硼、二氟化硼、銦或類似的村質進行佈植製程。 值得注意的是，閘極122和具凹口之間隙壁彳32在形 成源/汲極延伸區域138的佈植製程中係作為罩幕之用。因 #為佈植區域136係藉由一傾斜角度對基材”〇進行雜質的 離子佈植而形成，源/汲極延伸區域138則是藉由一垂直角 度對基材m進行離子佈植而形成，部分佈植區域136延 伸超過源/沒極延伸區域138而進入位於如帛ig圖所示之 閘極下方的區域，因此而行程暈狀佈植或口袋佈植區域。 第讣圖形成主間隙壁14〇之後之第1g目之晶圓 主間隙壁140係為第三佈植製程之間隙壁，較佳包 材質，例如氧化石夕、氮化石夕（Si3N4)、引3〜之外的含氮層， 如S|Ay，氮氧化石夕Si〇xNy，或其任意組合或類似材質。在 13 200537649 較佳實施例中，間隙壁140係藉由兩介電層，包括二氧化 石夕層及由低μ化學氣相沉積並覆蓋在二氧化㈣之上之氮 化石夕層所形成。氮切層沉積的厚度約介於测埃至測 埃之間而能藉由一非均向蝕刻進行圖案化。位於下方之二氧 化石夕層的厚度約介於2〇埃至_埃之間，且在氮切層形 成之後藉由一非均向或均向蝕刻進行圖案化。在佈植之後及 額外之高溫製程之前-般會進行—快速熱回火Μ此在晕狀 7植和源/汲極延伸區域佈植之後，一般會在主間隙壁140 2程之前進行一快速熱回火製程，其目的在於修復離子佈植 造成的損傷，進而降低後續伴隨間隙壁製作之熱循環所產生 的摻雜擴散。儘管如此，暈狀佈植和源/汲極延伸區域無可 避免的會垂直地擴散進ρ井118較深之處及閘介電12〇下 方的側部。 第1丨圖係繪示執行一第三離子佈植製程形成源/汲極區 142之後之第1 h圖之晶圓1 〇〇。源/汲極區彳42係以例如， 一 η型摻雜，如以5keV至5〇keV的能量及劑量約ιχι〇13 至5X10 (原子/平方公分）的填離子佈植以形成。其他η 型摻雜’例如砷、銻或類似的材質亦可選擇性地使用。ρ型 換雜，例如侧、二氟化硼、銦或類似的材質可用於製造PM〇S 元件。一般在源/汲極佈植之後，一額外的快速熱回火製程 會用來移除損傷及活化佈植摻雜以確定形成高導電性之源/ 及極和源/汲極延伸。除了快速熱回火製程外，其他回火製 程’閃光燈或雷射回火也可以用來移除佈植損傷及活化佈植 播雜。 200537649 此後’標準製程技術可用來完成半導體元件的製造。例 如，源/汲，區域和閘極形成矽化金屬，形成内層介電層， 形成接觸窗和介層窗’製造金屬線或其他類似的製程。 雖然本毛明及其優點已被詳細的揭露，必須理解的是在 不脫離本發明之精神和範圍内，任何各種之更動、取代與潤 •飾均屬本發明申請專利範圍之内。例如，PM0S電晶體可以 .以使用各種材質、厚度、濃度或類似的條件來製造。又例如， •本發明所揭露的元件和製造方法在為任何熟習此技藝者理 解之後而引用在包含其他元件的半導體元件之中均屬於本 發明申請專利範圍所界定之保護範圍。 更進一步而言，本說明書的範圍並非蓄意來限制本說 月書中之特別的製程、機械、製造、物質組成、裝置、 方法和步驟的實施例。而熟悉此領域技藝者於領悟本發 明、製程、機械、製造、物質組成、裝置、方法和步驟 的揭露後，現在存在或稍後發展的能如同本發明相關實 •施例執行實質相同的功能或達成實質相同的結果均數本 發明之應用。因&，本發明之申請專利範圍所欲保護的 範圍包括製程、機械、製造、物質組成、裝置、方法和 步驟。 【圖式簡單說明】 為讓本發明之上述和其他目的、特徵、和優點能更明顯 易懂，下文特舉一較佳實施例，並配合所附圖式，作詳細說 明如下： 15 200537649 第1 a圖至第1 i圖係繪示經由本發明之實施例所揭露不 同的製程之後的晶圓剖面示意圖。 【主要元件符號說明】 100 :晶圓 110 :基材200537649 IX. Description of the invention [Technical field to which the invention belongs] The present invention relates to a semiconductor device, and more particularly to a notch gap wall of a complementary metal-oxide-semiconductor transistor. [Previous technology] In today's day, complementary metal-oxide-semiconductor (CMOS) technology is a mainstream technology used to manufacture very large-scale integrated circuits. Over the past decade, the reduction in the size of semiconductor structures has led to significant advances in semiconductor wafers in terms of speed, efficiency, circuit density, and cost per unit function. However, the obvious challenge lies in the continued reduction in size of CMOS devices. For example, when the gate length of a CMOS transistor is reduced, the effects of the source and drain regions and channels increase, which affects the channel potential and the gate. Therefore, transistors with short channels need to withstand the problem that the gate cannot substantially control channel switching between on and off states. The phenomenon that the idler control decreases with the short channel of the transistor is called the short channel effect. One way to reduce the influence of the source and drain on the channel and gate is to introduce additional impurities in the channel region. The electrical properties of the impurities are opposite to the electrical properties of the source / drain implant. For example, P-type metal-oxide semiconductors (pM〇s) f crystals-generally formed on an n-type silicon substrate (or η · on a p-type silicon substrate). Type Inoue). The source and drain regions are formed on the substrate by implanting a p-type impurity on the substrate with a gate electrode mask. In order to reduce the short-channel effect, the impurity region, generally referred to as 200537649, is halo implants or pocket implants (卩 3 ^ 响 _ 如 〇ns), which is formed before the source / drain is formed in the source / It is formed by implanting additional n-type impurities at the position of the non-polar region. The halo implantation generally implants impurities into the surface of the substrate at an oblique angle and implants high-concentration impurities below the interrogator. Then-type impurities are implanted on the surface of the substrate at a vertical angle to form an extended source / drain. An additional spacer, ion implantation, can be used to complete the source / drain region process. In order to control the density and depth of halo implants, an attempt is made to use a notched structure as a mask. If you increase the energy or angle of planting, a notch or a notched structure at the base of the gate can make it below the gate: the penetration of the ^ part of the plant is increased without increasing the required ion implantation depth The second figure shows that the 3rd figure has a notch _ pole, and this _ pole is recessed along the surface of the substrate: the thickness of the soldier is thin. Such a structure generally does not control the length of the idler pole, in other words, it is difficult to control the electrical property of the gate. Others have tried to form a thin wall on the gate sidewall. The gap is generally formed by nitrogen cutting and oxygen cutting. The silicon nitride-tL "Tonsuoyou-dry etching patterned its film 4" this patterned nitride In the subsequent wet etching, the thin film is formed as a hard process at the bottom of the gate electrode along the ^ W㈣㈣oxidation process. The notch: determined by the thickness of the ⑽⑦ layer and the ㈣ layer on the 乂 on the complex mouth, The notch 疋 source / sink pole is implanted at the lateral starting point. Also, the soreness of the sore, H — is determined only by the thickness of the silicon oxide layer. The width and height of the notch A 佶 田 + Λ Skin ~ The final shape of the shape-like planting. Because = two layers are used to form the gap wall with a notch, which is essentially such a system-', especially the thickness of the nitride stone and the oxide stone is used to determine the width of the mouth 6 200537649 degrees And subsequent source-drain extensions, halo implants, and related parts of the gate. Further, 'the use of double or multiple layers of silicon oxide and silicon nitride to form a notched gap wall limits the height and width of the notch The aspect ratio of 'concave σ is the condition of halo planting-' can be used to determine the halo contour In the same way, using multiple layers of recessed walls with a notch on the source will result in a larger implantation and screen, which will reduce the overlap area and high impedance. — So 'needed — a tool The gap wall of the notch can improve the halo-shaped implantation process and the Luan extension source / drain electrode implantation process. [Summary of the Invention] The foregoing and other problems can generally be reduced, solved or avoided by the disclosure of the embodiments of the present invention. Achieve technical progress. Embodiments of the present invention provide a notch-shaped gap wall to control the military-like implantation process and the extended source / drain implantation process in the manufacturing process of the semiconductor device. In the present invention-embodiments Provided-semiconductor, this semiconductor element #:-has a substrate and a gate electrode on the substrate. A first ion implantation mask is formed along the side of the 4 poles, so some parts need to be removed. The first ion implantation mask is located on the substrate.-The-ion implantation region is located on the substrate with a second ion implanter and impurities, wherein the first ion implantation mask is used as a base at an oblique angle. Surface of the material is implanted with material curtain.— 第Ion implantation area, the second ion type impurity on the soil material, where the first ion implantation mask = as a mask after -H-subplantation on the substrate surface at -vertical angle An additional ion implantation is formed and performed on the side of the first ion implantation mask. 7 200537649 In another embodiment of the present invention, a notched gap is provided for half of the components along the gate-'the conductor in the gate On both sides of the pole, and located on the surface of the substrate # ”土 乂 成 入 —m The gap between the surface and the side wall of the gate: Remove all or part of the gap. -The second gap wall is formed along the gap wall with the notch. In the foregoing another embodiment, a method for forming a semiconductor element is provided. A gate is formed on a substrate, and a first ^ A ion implantation mask is formed along the side of the gate. Therefore, the part to be removed is located on the substrate. The first ion implanted mask. The first ion implantation mask was used as the mask. Two w | θ dry ginsengs were subjected to a first ion implantation at an inclined angle on the surface of the substrate. A second ion implantation is performed on the surface of the substrate at a vertical angle and a right angle. After that, additional masks are formed. The mask ... 仃 -extra separation In the foregoing alternative embodiment, the method of providing another-formation-semiconductor element = -the first layer is formed to cover the substrate and the closed electrode. A second layer is formed to cover the first layer. A gap wall curtain is formed from the second layer and an etch process is performed to pattern the first layer, and the first layer is removed along the surface portion of the substrate. The gap wall mask is removed and a first-ion implant is performed on the substrate surface at an oblique angle. Perform a second ion implantation on the substrate surface at a vertical angle. Thereafter, an additional mask is formed, and an additional ion implantation is performed. [Embodiment] The manufacture and use of this embodiment are discussed in detail later. It is commendable that the present invention provides many applicable inventive concepts', and these inventive concepts can be embodied by a broad and diversified description content. Although the discussion of the embodiment of the present invention 8 200537649 only describes a specific way to implement and use the present invention, it is not intended to limit the present invention. Figures 1a to 1i show a method for manufacturing a transistor having a halo-shaped implant in a channel region according to a preferred embodiment of the present invention. It should be particularly pointed out that this embodiment is only discussed by taking an N-type meta-oxide semiconductor (N-type meta) transistor formed on a p-type substrate as an example. Those who are familiar with this technology can apply the effects to the fabrication of PMOS transistors after understanding the disclosure of the present invention. Further, the processes disclosed herein will be applicable to the manufacture of one or more quadrupoles and one or more NMOS on a single substrate. = See Section 1a @ '— Wafers include — a substrate with shallow trench isolation junctions, closed dielectric layer 114 and interlayer 116 formed thereon. In a preferred embodiment, the substrate 110 includes a substrate having a well 118 formed on a ㈣ = ㈣ substrate. Other materials, such as tungsten, germanium alloy, or other types of materials I, can be selectively used as the substrate 110. Alternatively, the Shi Xi substrate may be an active layer with a silicon substrate on the insulating layer or a multilayer junction such as a silicon germanium layer formed on a bulk silicon substrate. The closing layer m includes oxygen cutting, nitrogen cutting, nitrogen cutting, a dielectric metal oxide or any combination thereof. Oxide stone gate dielectric: Layer two can be shaped by, for example, an 'oxidation process' such as a wet or dry thermal process. In the preferred embodiment, the thickness of the interlayer dielectric layer 114 is between about 10 Angstroms and the electrode layer 116 includes a conductor. Material, such as metal (such as New Zealand, Qin, Fan,-,, Bai Ming, to, ruthenium), metal stone compounds (such as Shi Xihua Qin, Shi Xihuashi, 200537649 nickel silicide, silicon button), metal nitride (Such as titanium nitride, tantalum nitride), doped polycrystalline silicon, other conductor materials, or any combination thereof. For example, amorphous silicon can be deposited first and then recrystallized to form polycrystalline silicon. In a preferred embodiment, the gate electrode is a Shi Xi, and a low-pressure chemical vapor deposition is used to deposit a thickness between 2000 Angstroms and 2000 Angstroms. Polysilicon is doped to form the gate electrode 116. Please refer to FIG. 1b. FIG. 1b shows the wafer 100 of FIG. 1a. After the idle dielectric layer 114 and the gate layer are patterned, a gate dielectric 12 and a gate 122 are formed. The gate electrode 120 and the gate electrode 122 can be patterned by a lithography technique. Generally speaking, the lithography process includes spin-coating a photoresist material, then adding a photomask, and then performing exposure and development. After patterning the photoresist mask, a non-uniform etching process is performed to remove the unnecessary portions of the gate dielectric layer 1i4 and the gate layer 116 in the second figure to form the gate dielectric 12 as shown in the second figure. For the sum gate, see FIG. 1 c. FIG. C shows the wafer 100 in FIG. 1b after the first dielectric layer 12 and the -dielectric layer 128 are formed. The first dielectric layer includes silicon oxide formed using a low-pressure chemical vapor deposition technique, using tetraethylisophthalate (SOS) and oxygen as precursors. Other materials, 实 t solid silicon, silicon and any combination thereof or similar materials can be used. 4. The thickness of the first dielectric layer 126 is between about 1 angstrom and 15 angstroms. However, the preferred thickness is about 100 angstroms. It is worth noting that the first thickness is defined with a notch as the minimum height of the notch is defined. The first-dielectric layer 128 preferably includes silicon nitride (quote), and is chemically vapor-deposited with silane. 200537649 and ammonia formed as precursors, and silicon. Other materials ’such as nitrogen-containing layers other than s 丨 high, such as silicon oxynitride SiOxNv, Shi Gan 7 Li, in y, the -dielectric / 128 is used. In the first embodiment, the thickness of the electrical layer 128 is approximately between 50 angstroms and 200 angstroms. … See Section IX. The patterned second dielectric layer 128 (FIG. 10) is used to form a recessed gap wall curtain curtain for forming a recessed gap wall. Jiashi, in the example, the second dielectric layer 128 is Si3N4, and the second dielectric layer 12: is formed by dry etching. It should be noted that the material forming the first *: dielectric layer 128 and the material forming the first dielectric layer 126 need to have the same etching selection ratio. Therefore, the other layer is relatively less affected when one layer is removed by etching. Please refer to FIG. 1e. FIG. 1e shows the 1d0 wafer 100 after the first dielectric layer 126 is patterned to form the notch spacer 132. The first dielectric layer 126 is etched by a dilute hydrofluoric acid solution for a time-controlled isotropic wet etching process. The height of the notch is determined by the thickness of the first dielectric layer, the etching rate of the first dielectric layer, and the etching period. As shown in FIG. 1e, the portion of the first dielectric layer 126 not shown in FIG. 1d, which is located below the recessed gap cover curtain 30, is removed by a uniform etching process to form a recessed gap. . The width of the notch is determined by the first dielectric layer 126 and the height of the notch is controlled by different etching periods. Further, FIG. 1e shows a case where the first dielectric layer 126 is completely removed and the gate electrode 12 is exposed. In other cases, part of the first dielectric layer 彳 26 remains on the side wall of the gate electrode 122. This is as needed, for example, it is preferably used to control the depth and angle of implantation or to protect the gate electrode 22 or the gate dielectric 120 from the damage of the subsequent etching process or other processes. 200537649 It is further worth noting that if the gate dielectric 1 20 and the notch gap wall 1 32 are made of silicon oxide, it is used to form the notch gap wall. Μ The etching process may remove some of the gate dielectric Electricity 1 20 thus changes its electrical properties. Therefore, it is necessary to use different materials to form the gate dielectric 1 20 and the notched gap wall 1 32 or use an etching process with a high etching selection ratio between the gate dielectric 1 20 and the notched gap wall 1 μ. . For example, a high dielectric constant material is used to form the gate dielectric 1 20 and a low-pressure chemical vapor deposition of oxidized stone is used to form a φ-notched partition wall 1 32. In this case, the etching process used to form the notch gap wall 132 has a very high #cut select ratio for the gate dielectric 120 and the notch gap wall 132. After the etching process, a tempering process may be selectively performed to repair the damage of the gate dielectric 120. Fig. 1f shows the wafer 100 of Fig. 1e after removing the notch gap wall cover 130 of Fig. 1e and forming the implantation area 136. By using a homogeneous etching process using a phosphoric acid aqueous solution, the silicon nitride notch gap wall cover is removed, and the silicon notch gap wall is not etched. It is undeniable that all φ technicians can agree that by removing the nitride stone before forming the planting area 136, the notch gap wall curtain 13 is formed, and the width of the notch is independently changed by the notch gap wall. 132 width to determine, which is easier to control than the conventional use of multilayer structures. In the embodiment, an NMOS is formed. As shown in FIG. 1f, the substrate is subjected to ion implantation of p-type impurities at an inclined angle to form a implanted region 136. For example, boron difluoride ions are implanted at an energy and dose of about 5 keV to 50 keV and a dose of about 13 × 5 × 10 14 (atoms / cm 2) to form a coating region 1 36. Optionally, boron, indium, or similar materials can be used for the implantation process. In order to form POMS, n-type doping is used, such as phosphorus, arsenic 12 200537649 antimony or similar materials for the implantation process. Those skilled in the art agree that the angle, dose, and energy level of the implant can be used to control the depth of the implant area 1 36 and the size of the sides. Therefore, the size and density of the implanted area 1 can be customized for specific applications and gate lengths. • Figure μ shows the wafer 100 in Figure 1e after the source / drain extension region 138 is formed. In the embodiment, a nmos is formed. As shown in FIG. Ig, the substrate is subjected to ion implantation of n-type impurities at a vertical angle to form a source / drain extension region 138. For example, the erbium ions are implanted with an energy and a dose of about 5X1014 to 3X1 G15 (atoms per square centimeter) to form a source / dimer extension region 138 at an energy of 1 keV to 5 keV. Optionally, phosphorus, osmium, or similar materials can be used for the planting process. In order to form a POMS, a p-type dopant, such as boron, boron difluoride, indium, or a similar substrate, is used for the implantation process. It is worth noting that the gate electrode 122 and the notch gap niche 32 are used as a mask in the process of forming the source / drain extension region 138. Because # is the implanted region 136 is formed by implanting impurities into the substrate by an oblique angle, and the source / drain extension region 138 is formed by ion implanting the substrate m at a vertical angle. Formation, part of the implantation area 136 extends beyond the source / electrode extension area 138 and enters the area below the gate as shown in the 帛 ig diagram, so the stroke or halo implantation area is formed. The main spacer 140 of the 1g mesh wafer after the spacer 14 is the spacer of the third implantation process, and the preferred packaging material is, for example, oxide stone, nitride stone (Si3N4), and other materials Nitrogen-containing layers, such as S | Ay, oxynitride SiOxNy, or any combination or similar materials. In a preferred embodiment of 13 200537649, the spacer 140 is formed by two dielectric layers, including SiO2 Layer and a layer of nitride nitride layer deposited by low μ chemical vapor deposition and covered with hafnium dioxide. The thickness of the nitrogen-cut layer is between about Angstrom to Angstrom and can be etched by an anisotropy. Patterning. The thickness of the SiO2 layer below is about 20 angstroms to _ After the formation of the nitrogen-cut layer, the patterning is performed by an anisotropic or isotropic etching. After the implantation and before the additional high-temperature process-as usual-rapid thermal tempering. After the source / drain extension area is implanted, a rapid thermal tempering process is generally performed before the main gap wall 140 2 passes. The purpose is to repair the damage caused by ion implantation, thereby reducing the subsequent thermal cycle with the gap wall The resulting dopant diffusion. Nevertheless, the halo implant and source / drain extension regions inevitably diffuse vertically into the deeper part of the p-well 118 and the sides below the gate dielectric 120. Part 1丨 The diagram shows the wafer 100 in the 1 h diagram after performing a third ion implantation process to form the source / drain region 142. The source / drain region 彳 42 is, for example, an n-type doped, For example, it can be formed by implanting ion-filled ions with an energy and dose of about 5keV to 50keV and a dose of about 13 to 5X10 (atoms per square centimeter). Other n-type dopings such as arsenic, antimony, or similar materials can also be selectively Use .ρ type replacement, such as side, boron difluoride, indium or similar materials can be Used to make PMOS devices. Generally after source / drain implantation, an additional rapid thermal tempering process is used to remove damage and activate implant doping to determine the formation of highly conductive source / electrode and Source / drain extension. In addition to the rapid thermal tempering process, other tempering processes 'flash or laser tempering can also be used to remove implant damage and activate implant seeding. 200537649 Thereafter' standard process technology can be used to complete Manufacturing of semiconductor components. For example, source / drain, regions and gates form silicided metals, form inner dielectric layers, form contact windows and interlayer windows to make metal wires or other similar processes. Although Ben Maoming and its advantages have After being disclosed in detail, it must be understood that without departing from the spirit and scope of the present invention, any changes, substitutions, and decorations are within the scope of the patent application of the present invention. For example, PMOS transistors can be manufactured using a variety of materials, thicknesses, concentrations, or similar conditions. For another example, • The components and manufacturing methods disclosed in the present invention, after being understood by any person skilled in the art, are cited in the semiconductor components containing other components, which all fall within the protection scope defined by the scope of patent application of the present invention. Furthermore, the scope of this specification is not intended to limit the specific process, machinery, manufacturing, material composition, device, method, and embodiment of the examples in this book. However, those skilled in the art will understand that the present invention, process, machinery, manufacturing, material composition, device, method, and steps are disclosed, and those existing or later developed can perform substantially the same functions as the related embodiments of the present invention. Or achieve substantially the same result as the average application of the present invention. Because of &, the scope of protection of the patent application scope of the present invention includes manufacturing process, machinery, manufacturing, material composition, device, method and step. [Brief description of the drawings] In order to make the above and other objects, features, and advantages of the present invention more comprehensible, a preferred embodiment is given below in conjunction with the accompanying drawings to make a detailed description as follows: 1 a to 1 i are schematic cross-sectional views of a wafer after different processes are disclosed according to embodiments of the present invention. [Description of main component symbols] 100: Wafer 110: Substrate
112 :淺溝渠隔離結構 114 :閘介電層 11 6 :閘極層 118 : P 井 120 :閘介電 122 :閘極 126、128 :介電層 130 :具凹口間隙壁罩幕 132 :具凹口間隙壁 136 :佈植區域 1 3 8 :源/汲極延伸區域 140 :主間隙壁 142 :源/汲極區 16112: Shallow trench isolation structure 114: Gate dielectric layer 116: Gate layer 118: P well 120: Gate dielectric 122: Gate electrode 126, 128: Dielectric layer 130: Notch gap wall cover 132: Notch gap wall 136: implanted area 1 3 8: source / drain extension area 140: main gap wall 142: source / drain area 16