TW476990B - Semiconductor device - Google Patents

Semiconductor device Download PDF

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Publication number
TW476990B
TW476990B TW090104917A TW90104917A TW476990B TW 476990 B TW476990 B TW 476990B TW 090104917 A TW090104917 A TW 090104917A TW 90104917 A TW90104917 A TW 90104917A TW 476990 B TW476990 B TW 476990B
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TW
Taiwan
Prior art keywords
film
point metal
melting point
high melting
intermediate layer
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Application number
TW090104917A
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English (en)
Inventor
Masaaki Hatano
Takamasa Usui
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Toshiba Corp
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Publication of TW476990B publication Critical patent/TW476990B/zh

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/31Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to form insulating layers thereon, e.g. for masking or by using photolithographic techniques; After treatment of these layers; Selection of materials for these layers
    • H01L21/3205Deposition of non-insulating-, e.g. conductive- or resistive-, layers on insulating layers; After-treatment of these layers
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    • H01L23/522Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/532Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body characterised by the materials
    • H01L23/53204Conductive materials
    • H01L23/53209Conductive materials based on metals, e.g. alloys, metal silicides
    • H01L23/53228Conductive materials based on metals, e.g. alloys, metal silicides the principal metal being copper
    • H01L23/53238Additional layers associated with copper layers, e.g. adhesion, barrier, cladding layers
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Description

476990 經濟部智慧財產局員工消費合作社印制衣 A7 B7 五、發明說明(1 ) 發明説明 本發明是有關以LSI爲代表之半導體裝置,特別是與配 線(wring)用之銅膜層及墊層用之鋁膜之接續有關。 圖10是具有銅膜層及墊層用之鋁膜構造之以往之半導裝 置之斷面圖。 、 如圖10所示,第1層區(由層間絕緣膜interlayer insulating film 11、能障層(barrier layer )12、及配線用金 屬膜13所組成),其上形成第2層區(由層間絕緣膜2 1、能障 層22、及配線用金屬膜23所組成),在第2層區之上又形成 第3層區(由矽氮化膜silicon nitride film 31、上層絕緣膜32 、能障層33、及墊襯用鋁膜34所組成)。 如圖所示,配線用之銅膜23及墊襯用鋁膜34之間設有能 障層33。此能障層33是防止銅膜23及塾襯用鋁膜34之間相 互擴散。能障層33之能障金屬有TaN、NbN、TiN、VN等高 溶點金屬氮化物(refactory metal nitride )。 然而如上述以往技術鋁膜3 4是用濺鍍等方法形成,銘膜 34含有之鋁和能障層33含有之氮反應成絕緣物氮化鋁ΑιΝχ ’因這Α1ΝΧ使電阻上升(特別是接觸孔Via電阻)而產生問題 。又上層絕緣膜32用的矽氧化膜(silicon oxcide film )和能 障層33用的高熔點金屬氮化物膜之接著性不佳,在兩者之 間的空隙滲入氧氣氧化銅膜23也產生問題。 如此爲防止配線用銅膜23及墊襯用鋁膜34之間相互擴散 ,以往在兩者之間設有高熔點金屬氮化物膜之能障層,然 而銘和氮之間反應產生A1NX使電阻上升,又上層絕緣膜和 -4- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) — — — — — — — — ----· I I I # (請先閱讀背面之注意事項再填寫本頁) 訂---------
經濟部智慧財產局員工消費合作社印制农 旎障層之接著性不佳使銅膜氧化。這是造成半導體裝置之 特性或信賴不良的原因。 發明之簡單説明 針對以上問題,提高具有配線用銅膜及和此接續墊襯用 鋁膜之半導體裝置之特性或信賴性是本發明之目的。 本發明之第一個重點是針對在半導體基板主面上形成構 成配線層(wiring layer)之銅膜,至少在銅膜上形成中間層 ,及在中間層上形成構成墊層之鋁膜之半導體裝置,而中 間層是在高熔點金屬氮化物膜及高熔點金屬氮化物膜上形 成之高熔點金屬膜。 依本發明方法在鋁膜和鬲溶點金屬氮化物膜之間置入一 層高熔點金屬膜。因此可防止鋁膜含有之鋁和高熔點金屬 氮化物膜含有之氮反應生成絕緣物A1NX。因此可防止因 A1NX造成之電阻上升問題,得到特性優良之半導體裝置。 本發明之第二個重點是針對在半導體基板主面上形成構 成配線層之銅膜,至少在銅膜上形成中間層,及在中間層 上形成構成墊層之鋁膜之半導體裝置,而中間層是在高溶 點金屬膜及高熔點金屬物膜上形成之高熔點金屬氮化物膜。 依本發明方法在鬲熔點金屬氮化物膜之下形成一層比高 少谷”:、占至屬氮化物膜對、纟巴緣膜(特別是石夕氧化膜系絕緣膜)接 著性好之高熔點金屬膜,提高中間層和絕緣膜之接著性。 因此可防止因接著不良產生間隙滲入氧氣氧化銅膜等問題 ,得到信賴性優良之半導體裝置。 在%述第一及第二重點提及含於高溶點金屬膜之高溶點 金屬和含於高熔點金屬氮化物膜之高熔點金屬最好是同一 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ·裝--------訂--------- (請先閱讀背面之注音?事項再填寫本頁) 476990 A7 B7 經 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 印 製 五、發明說明(3 ) 種金屬。因使用同一種金屬在濺鍍高熔點金屬氮化物膜和 高溶點金屬膜時用同一藏鍍革巴,可同時縮減工時及成本。 在前述第一及第二重點提及含於高熔點金屬膜之高溶點 金屬可在Ta(銥)、Nb(說)、Ti(鈦)、V(釩)擇一使用,又前述 含於尚溶點金屬氮》化物fl吴之南 '丨容點金屬最好在、Nb、τι 、V擇一使用。 在前述第一及第二重點提及高熔點金屬膜之厚度最好在 5nm以下。 本發明之第三個重點是針對在半導體基板主面上形成構 成配線層之銅膜,至少在銅膜上形成中間層,及在中間層 上形成構成墊層之鋁膜之半導體裝置,而中間層是由第一 高熔點金屬膜及前述第一高熔點金屬物膜上形成之高熔點 金屬氮化物膜及前述高熔點金屬氮化物膜上形成之第二高 溶點金屬膜所組成。 在前述第三重點提及含^第―高以金屬膜之高溶點金 屬和含於高熔點金屬氮化物膜之高熔點金屬及含於第二高 溶點金屬膜之高熔點金屬最好是同一種金屬。口、 问 在前述第三重點提及含於第一高烷 、丄 U金屬腰1鬲溶點金 屬可在Ta、Nb、Ti、V擇一使用,又4丄人 卜 文〗又則述含於高熔點金屬 鼠化物膜之高熔點金屬最好在丁&、Nb、τ· 人、,. b、Τι、V擇一使用, έ於第二高熔點金屬膜之高熔點金屬 /旬 J 在 Ta、Nb、Ti、ν 擇一使用。 在前述第三重點提及高炫點金相之厚度最好在5n_ 下0 (請先閱讀背面之注意事項再填寫本頁) --------訂--------- -6 - 經濟部智慧財產局員工消費合作社印制衣 476990 A7 B7 ------—---— 五、發明說明(4 ) 在前述第一、第二、及第三重點提及高熔點金屬氮化物 膜是指高熔點金屬及氮爲主成分之化合物。 在前述第一、第二、及第三重點提及之中間層包本和前 述銅膜接觸之第一部分及不和銅膜接觸之第二部分,最好 於前述第二部分和絕緣膜接觸。 在前述第一、第二、及第三重點提及由鋁膜構成之塾層 最好和接合配線(bonding wire)接續。 發明之實施形態 以下參照圖面説明本發明之實施形態。 (實施形態1) 圖1是與本發明第一實施形態有關半導體裝置構成之斷 面圖。 如圖1所示’半導體基板1 〇上形成第1層區(由層間絕緣 膜11、能障層12、及配線用金屬膜13所組成),在其上形成 第2層區(由層間絕緣膜21、能障層22、及配線用銅膜23所 組成),在第2層區之上又形成第3層區(由矽氮化膜3丨、上層 絕緣膜32、能障層33、及墊襯用鋁膜34所組成)。又在半導 體基板10和第一層區之間·亦可再加一下層區。 圖2A〜圖2G是與本發明第一實施形態有關半導體裝置製 造万法工程之斷面圖。又將如圖丨所示半導體基板1〇之圖示 省略。 首先如圖2A所不電晶體等半導體元件(未圖示)形成之半 導to基板(未圖tf )之主表面上形成包括層間絕緣膜丨丨、能障 (請先閱讀背面之注意事項再填寫本頁) · ϋ n I n ϋ 一· n n ϋ I ϋ ϋ
476990 A7 B7 五、發明說明(5 ) 層12、及配線用金屬膜13所組成之第1層區。在其上形成第 一層區之層間絕緣膜21 (例TEOS -Si〇2膜或Low-k膜(低電容 率膜)、或這些層積膜)。 其次如圖2B所示,將層間絕緣膜21加工形成接觸孔、 配線用或墊襯用溝糟。 其次如圖2C所示,全面形成TaN、NbN等高溶點金屬氮 化物構成之能障層(能障金屬層)22。在能障層22上形成銅膜 23。此銅膜23是在能障層22上形成之薄片層銅膜,以電解 鍍敷法(electroplating)形成之銅膜。 其次如圖 2D 所示,以 CMP(chemical mechanical polishing)法平坦化處理,只允許能障層22及銅膜23在接觸 孔、配線用或墊襯用溝糟内部殘留。以此處理方法形成第 二層區之接觸孔、配線及塾襯。 之後形成TE0S-Si02膜構成之保護膜或Low-k膜(低電容 率膜)之絕緣膜,在此絕緣膜上形成墊襯用孔使銅墊部之表 面呈露出狀態。因此不僅銅墊部氧化,經過一段時間銅配 線全部氧化。 在此爲防止銅墊部氧化在上層再形成鋁墊區構成之第三 層區。本例在此形成鋁墊區如圖2E〜圖2G所示,以雙鑲金 (dual damascene)法處理。 如圖2E所示,爲防止銅膜23之銅擴散全面形成矽氮化 膜31(電漿SiN膜)。然後在矽氮化膜上形成上層絕緣膜32(例 TEOS-Si〇2膜或Low-k膜(低電容率膜)、或這些層積膜)。之 後對矽氮化膜3 1及上層絕緣膜32加工形成接觸孔及墊襯用 -8- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) ------------裝--- (請先閱讀背面之注意事項再填寫本頁) 訂 經濟部智慧財產局員工消費合作社印制衣 476990 石 _I__ 經濟部智慧財產局員工消費合作社印製 A7 B7 發明說明(6) 溝。 ’ 其次如圖2F所示,全面形成中間層其構造容後再述。 又在中間層33上以濺鍍法(最好是長擲濺鍍i〇ng thr〇w spattering或反射流濺鍍reflow )等形成銘膜34。 其次如圖2G所示,以CMP法平坦化處理,只允許中間 層3 3及鋁膜3 4在接觸孔、配線用或塾襯用溝糟内部殘留。 以此處理方法形成第三層區之接觸孔、配線及墊襯。如此 得到和接合配線(未圖示)連接之錯整。 圖3 A〜圖3C説明上述中間層33之幾種構造例。 圖3A其中間層33是由高熔點金屬氮化物膜33b(例TaN膜 等之能障金屬膜)及高溶點金屬膜3 3 c(例Ta膜等)之層積構 造。如此在銘膜34和高熔點金屬氮化物膜33b之間夾有高熔 點金屬膜33c,得以防止以往的問題。即含有鋁之鋁膜34和 含有氮之高熔點金屬氮化物膜33b反應形成絕緣物A1NX,得 以防止因A1NX產生之電阻(特別是接孔電阻)上升問題。 圖3B其中間層33是由高熔點金屬膜33 a (例Ta膜等)及高 熔點金屬氮化物膜33b(例TaN膜等)之層積構造。如此在高 溶點金屬氮化物膜33b和上層絕緣膜32(矽氧化膜系膜)之間 炎有接著性良好的高熔點金屬膜33a(例Ta膜等),得以提高 中間層33和上層絕緣膜32之接著性。因此可防止因上層絕 緣膜3 2和中間層3 3接著不良產生間隙滲入氧氣氧化銅膜3 2 寺問題。 圖3C其中間層是由高熔點金屬膜33 a(例Ta膜等)及高熔 點金屬氮化物膜33b(例TaN膜等)及高熔點金屬膜33c(例Ta 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) ·裝 476990 A7 --------- -B7__ 五、發明細(7 ) 膜等)之層積構造。如此得到如圖从及圖3B之構造兼得兩 者之效果。 (請先閱讀背面之注意事項再填寫本頁) 又高熔點金屬膜33&及高熔點金屬膜33〇可在^膜、Nb 、TiM、V膜中擇_使用,又高溶點金屬氮化物膜说可 在 TaN、NbN、TiN、VN 中擇一使用。 在圖3A〜圖3C中之各構造其含於統點金屬膜内之高溶 點金屬7L素及高熔點金屬氮化物膜内之高熔點金屬元素可 以是兩種不同的金屬元素,但最好是選用同一種金屬元素 。在圖3C之構造中高熔點金屬膜33a、高熔點金屬氮化物膜 33b、及高熔點金屬膜33c最好選用同一種高熔點金屬元素 ,因使用同一種金屬在濺鍍各高熔點金屬膜時用同一濺鍍 靶,可同時縮減工時及成本。 經濟部智慧財產局員工消費合作社印制衣 又以能障性的觀點高熔點金屬氮化物膜是愈厚愈好,但 從電阻(特別是接觸孔電阻)及CMp的觀點是愈薄愈好。圖4 疋改變回火條件,不同TaN膜厚和薄層電阻關係實驗結果。 如圖所不’將鋼配線做Em試驗時之條件(450°C4min(相當反 射泥漱鍵時間)+400°C 30min(相當燒結sinter時間)+ 350°C 6h(相當EM試驗時間),TaN膜最好在20nm以上。若考慮加 上熱壓(相當增加EM試驗時間),TaN膜最好在40nm以上。 但Ta膜太厚時CMP處理困難最好在5nm以下。 又在第三層區之上層絕緣膜32形成之接觸孔圖樣伸到在 第二層區形成之墊襯用溝槽圖樣之外側區時,如圖5所示產 生不良情形。即如圖2E所示步驟中使上層絕緣膜32及矽氮 化膜3 1過餘刻時第二層區之層間絕緣膜2 1也被蝕刻。如圖5 本紙張尺度_+國國家規格⑽ X 297公爱) 476990 A7 B7 五、發明說明(8 ) 所示產生凹陷。因此在圖2F步驟中堆積中間層33及鋁膜34 時這些膜無法完全填入這凹陷部分。因此位於第三層區所 有接觸孔用之孔洞圖樣最好是位於第二層區墊襯用溝槽圖 樣之内側。 又鋁墊部最好是分割墊構造。因分割墊構造可減少因能 障金屬等和矽氧化膜系絕緣膜之膨脹係數不同降低接著性 等問題。 圖6是提鬲接合配線時耐性之構造。即使由铭膜3 4及中 間層33構成之墊部延伸,在這延伸區連接接合配線4〇。這 種構造縱使在接合配線時接合之配線突到中間層33也不會 影響銅膜23和鋁膜34之間的連接。 (實施形態2) 圖7A〜圖7C是與本發明第二實施形態有關半導體裝置製 造方法步驟之剖面圖。在本實施形態形成第三層區之鋁塾 邵時是用單鑲金法。到圖2D以前的步驟和第一實施形態相 同,以下説明其後之步驟。 圖2 D所示步驟後係如圖7 A所示,和第一實施形態一樣 全面形成矽氮化膜(電漿SiN膜)31。接著在矽氮化膜3 1上形 成上層絕緣膜32(例TE0S-Si02膜或Low-k膜(低電容率膜)、 或這些層積膜)。之後對矽氮化膜3 1及上層絕緣膜32加工形 成墊襯用溝槽。 其次如圖7B所示,全面形成中間層3 3。在中間層3 3上 以濺鏡法(最好是長擲濺鍍或反射流濺鍍)形成鋁膜34。中間 層33和第一實施形態相同,即如圖3 A〜圖3C所示層積構造 -11 - 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁)
· 1— 11 1·— ϋ I ·1 ϋ 一:0雩 I 1_1 ^1 ^1 1_1 1 ϋ I 經濟部智慧財產局員工消費合作社印製 經濟部智慧財產局員工消費合作社印製 476990 A7 B7___ 五、發明說明(9 ) 。具體説就是高熔點金屬膜/高熔點金屬氮化物膜之層積構 造、高熔點金屬氮化物膜/高熔點金屬膜之層積構造、或是 向溶點金屬膜/高熔點金屬氮化物膜/高熔點金屬膜之層積構 造。又高溶點金屬氮膜及高熔點金屬氮化物膜所使用的材 料和其組合也和第一實施形態相同。 其次如圖7C所示,以CMP法平坦化處理,只允許中間 層3 3及銘膜3 4在塾襯用溝糟内部殘留。以此處理方法形成 第三層區之墊襯。 圖7D是對應於圖7C之主要部分構造之斷面圖。在第三 層區之上層絕緣膜32形成之墊襯用圖樣伸到在第二層區形 成之塾襯用溝槽圖樣之外側區時,如第一實施形態所述產 生不良情形。如圖7D所示,因此位於第三層區所有整襯用 溝槽圖樣最好是位第二層區墊襯用溝槽圖樣之内側。 (實施形態3) 圖8A〜圖8C是與本發明第三實施形態有關半導體裝置製 造方法工程之斷面圖。在本實施形態形成第三層區之鋁墊
邵時是用穿孔程序及RIE(reactive ion etching)法。到圖2D 以前的步驟和第一實施形態相同,以下説明其後之步驟。 圖2 D所示’步驟後、如圖8 A所示,和第一實施形態一 樣全面形成矽氮化膜(電漿SiN膜)31。接著在矽氮化膜31上 形成上層絕緣膜32(例TEOS-Si〇2膜或Low-k膜(低電容率膜) 、或這些層積膜)。之後對矽氮化膜3丨及上層絕緣膜32加工 形成接觸孔。 其次如圖8B所示,全面形成中間層33。在中間層33上 -12· 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公爱) " --- (請先閱讀背面之注意事項再填寫本頁) * n n I B·— n ϋ ϋ 訂--------- 脅 4/()990 、發明說明(10 以表鍍法(最好是長擲濺鍍或反射流濺鍍)形成鋁膜34。中間 層33和第一貫施形態相同。即中間層33之構造如圖3A〜圖 3C所不層積構造,具體説就是高熔點金屬膜/高熔點金屬氮 化物膜之層積構造、高熔點金屬氮化物膜/高熔點金屬膜之 層積構造、或是高熔點金屬膜/高熔點金屬氮化物膜/高熔點 金屬膜之層積構造。又高熔點金屬氮膜及高熔點金屬氮化 物膜所使用的材料和其組合也和第一實施形態相同。 其次如圖7C所示,以光阻罩(未圖示)蝕刻鋁膜34及中間 層33形成第三區之墊襯。 圖8D是對應於圖8C之主要部分構造之斷面圖。在第三 層區 < 上層絕緣膜32形成之接觸孔圖樣伸到在第二層區形 成足塾襯用溝槽圖樣之外側區時,如第一實施形態所述產 生不良情形。如圖8D所示,因此位於第三層區所有接觸孔 用圖樣最好是位第二層區墊襯用溝槽圖樣之内側。 (實施形態4) 圖9A及圖9C是與本發明第四實施形態有關半導體裝置 製造方法工程之斷面圖。在本實施形態形成第三層區之鋁 整邵時是用RIE法。到圖2D以前的步驟和第一實施形態相同 ’以下説明其後之步驟。. 圖2D所示之步驟後,其次如圖9A所示,全面形成中間 層33。在中間層33上以濺鍍法(最好是長擲濺鍍或反射流濺 鐘)开^成銘膜3 4。中間層3 3和第一實施形態相同。即中間層 33之構造如圖3A〜圖3C所示層積構造,具體説就是高熔點 金屬膜/高熔點金屬氮化物膜之層積構造、高熔點金屬氮化 -13 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) · I Ml· IW 囉 — Ο··· I ΜΜ I > 經濟部智慧財產局員工消費合作社印製 476990 A7 . —— B7 五、發明說明(”) 物fe/鬲熔點金屬膜之層積構造、或是高熔點金屬膜/高熔點 金屬氮化物膜/高熔點金屬膜之層積構造。又高熔點金屬氮 月吴及鬲熔點金屬氮化物膜所使用的材料和其組合也 實施形態相同。 其次如9B所示,以光阻罩(未圖示)蝕刻鋁膜34及中間層 33形成第三區之墊襯。 日 圖9C是對應於圖9B之主要部分構造之斷面圖。以第三 層區之鋁墊的圖樣不能覆蓋在第二層區形成之銅墊的圖樣 襯用溝槽圖樣時在第二層上形成之銅墊會產生氧化等不良 情形。如圖9C所示,因此位於第三層區墊襯圖樣最好是可 完全覆蓋全部第二層區墊襯圖樣。換這之最好將全部第二 層區塾襯圖樣置於第三層區墊襯圖樣内側。 圖式之簡單説明 圖1是與本發明第一實施形態有關半導體裝置構成之斷 面圖。 圖2A〜圖2G是與本發明第一實施形態有關半導體裝置製 造方法工程之斷面圖。 圖3A〜圖3C是與本發明第一實施形態有關半導體裝置之 主要邵分構造之斷面圖。 圖4是TaN膜和薄膜電姐關係圖。 圖5是有關墊層間接續不良情形。 圖6是本發明實施形態配線接合(wire b〇nding)時爲提高 耐性構造之斷面圖。 圖7A〜圖7C是與本發明第二實施形態有關半導體裝置製 造方法工程之斷面圖。圖7D是對應於圖7C之主要部分構造 -14- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐) (請先閱讀背面之注意事項再填寫本頁) 裝 訂· 經濟部智慧財產局員工消費合作社印製 476990 A7 B7 五、發明說明(12 ) 之斷面圖。 (請先閱讀背面之注意事項再填寫本頁) 圖8A〜圖8C是是與本發明第三實施形態有關半導體裝置 製造方法工程之斷面圖。圖8D是對應於圖8C之主要部分構 造之斷面圖。 圖9A及圖9B是與本發明第四實施形態有關半導體裝置 製造方法工程之斷面圖。圖9C是對應於圖9B之主要部分構 造之斷面圖。 圖10是與以往技術有關半導體裝置構造之斷面圖。 經濟部智慧財產局員工消費合作社印製 -15- 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)

Claims (1)

  1. 經濟部智慧財產局員工消費合作社印製 476990
    六、申請專利範圍 種半導f豆裝置(semiconductor device),其特徵爲具有 在半導體基板主面上形成構成配線層之銅膜;至少在銅 膜上形成中間層;及在中間層上形成構成墊層之鋁膜; 这中間層包含咼溶點金屬氮化物膜 rntride film)及於前述高熔點金屬氮化物膜上形成之高熔 點金屬膜(refractory metal film)。 2. 如申請專利範圍第1項之半導體裝置,其中中間層包含和 前j銅膜接觸之第一部分及不和銅膜接觸之第二部;, 於前述第二部分和絕緣膜接觸。 3. 如申請專利範圍第丨項之半導體裝置,其中包含於前述高 熔點金屬膜之高熔點金屬和包含於前述高熔點金屬氮化 物膜之高熔點金屬是同一種金屬。 人 4. 如申請專利範圍第1項之半導體裝置,其中包含於前述高 熔點金屬膜之高熔點金屬可在Ta、Nb、Ti、V擇一使用 二又前述包含於前述高熔點金屬氮化物膜之高熔點金屬 最好在Ta、Nb、Ti、V擇一使用。 5· 一種半導體裝置’其特徵爲具有在半導體基板主面上形 成構成配線層之銅膜;至少在銅膜上形成中間層;及在 中間層上形成構成墊層之鋁膜;前述中間層包含高熔點 金屬膜及於前述高熔點金屬膜上形成之高熔點:屬氮化 物膜。 6.如申請專利範圍第5項之半導體裝置,其中中間層包含和 岫述銅膜接觸之第一部分及不和銅膜接觸之第二部分, 於則述第二邵分和絕緣膜接觸。 本紙張尺度適財_家鮮χ挪公爱) (請先閱讀背面之注意事項再填寫本頁)
    &8 ^/0990 &8 ^/0990 經濟部智慧財產局員工消費合作社印製 ----— _ D8_ 六、申請專利範圍 7·如申請專利範圍第5項之半導體裝置,其中包含於前述高 燦點金屬膜之高熔點金屬和包含於前述高熔點金屬氮化 物膜之高熔點金屬是同一種金屬。 8·如申請專利範圍第5項之半導體裝置,其中包含於前述高 溶點金屬膜之高熔點金屬可在Ta、Nb、Ti、V擇—使用 ,又前述包含於前述高熔點金屬氮化物膜之高燦點金屬 最好在Ta、Nb、Ti、V擇一使用。 9· 一種半導體裝置,其特徵爲具有在半導體基板主面上形 成構成配線層之銅膜;至少在銅膜上形成中間層;及在 中間層上形成構成墊層之鋁膜;前述中間層包含第一言 溶點金屬膜、在前述第一高溶點金屬膜上形成之高燦點 金屬氮化物膜及前述高熔點金屬氮化物膜上形成之第一 高熔點金屬膜。 — W·如申請專利範圍第9項之半導體裝置,其中中間層包含和 别述銅膜接觸之第一部分及不和銅膜接觸之第二部分 於前述第二部分和絕緣膜接觸。 11·如申請專利範圍第9項之半導體裝置,其中包含於前述第 一高熔點金屬膜之高熔點金屬、包含於前述高熔點 氮化物膜之南溶點金屬及包含於前述第二高溶點金屬月L 之南溶點金屬是同一種金屬。 12.如申請專利範圍第9項之半導體裝置,其中含於前述第一 咼谷點金屬膜之南溶點金屬可在Ta、Nb、Ti、V擇 用,前述含於前述高熔點金屬氮化物膜之高熔點金屬最 好在Ta、Nb、Ti、V擇—使用,及含於前述第二高 -17- 本紙張尺度適用中國國家標準(CNS)A4規格(21〇 X 297公愛) --------訂--------- (請先閲讀背面之注意事項再填寫本頁} 476990 A8B8C8D8 六、申請專利範圍 金屬膜之高熔點金屬可在Ta、Nb、Ti、V擇一使用 (請先閱讀背面之注意事項再填寫本頁) 濟 部 智 慧 財 產 局 員 工 消 費 合 作 社 -18 印 製 本紙張尺度適用中國國家標準(CNS)A4規格(210 X 297公釐)
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Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4170103B2 (ja) * 2003-01-30 2008-10-22 Necエレクトロニクス株式会社 半導体装置、および半導体装置の製造方法
JP3802002B2 (ja) * 2003-03-27 2006-07-26 三星電子株式会社 半導体装置の製造方法
KR100564430B1 (ko) * 2003-07-16 2006-03-28 주식회사 하이닉스반도체 유기 반사 방지막 중합체, 이의 제조 방법 및 이를함유하는 반사 방지막 조성물
US20050206007A1 (en) * 2004-03-18 2005-09-22 Lei Li Structure and method for contact pads having a recessed bondable metal plug over of copper-metallized integrated circuits
US7242102B2 (en) * 2004-07-08 2007-07-10 Spansion Llc Bond pad structure for copper metallization having increased reliability and method for fabricating same
JP4674522B2 (ja) * 2004-11-11 2011-04-20 株式会社デンソー 半導体装置
US7351656B2 (en) * 2005-01-21 2008-04-01 Kabushiki Kaihsa Toshiba Semiconductor device having oxidized metal film and manufacture method of the same
US8319343B2 (en) 2005-09-21 2012-11-27 Agere Systems Llc Routing under bond pad for the replacement of an interconnect layer
JP2007266073A (ja) * 2006-03-27 2007-10-11 Toshiba Corp 半導体装置及びその製造方法
JP2008091835A (ja) * 2006-10-05 2008-04-17 Toshiba Corp 半導体装置およびその製造方法
KR100824622B1 (ko) 2006-11-27 2008-04-24 동부일렉트로닉스 주식회사 반도체 소자의 제조 방법
KR100885186B1 (ko) 2007-05-03 2009-02-23 삼성전자주식회사 확산 베리어 필름을 포함하는 반도체 소자의 형성 방법
KR100914982B1 (ko) * 2008-01-02 2009-09-02 주식회사 하이닉스반도체 반도체 소자의 금속배선 및 그 형성방법
CN101630667A (zh) * 2008-07-15 2010-01-20 中芯国际集成电路制造(上海)有限公司 形成具有铜互连的导电凸块的方法和系统
JP5249080B2 (ja) * 2009-02-19 2013-07-31 セイコーインスツル株式会社 半導体装置
JP6329027B2 (ja) * 2014-08-04 2018-05-23 ミネベアミツミ株式会社 フレキシブルプリント基板
CN105826213B (zh) * 2015-01-06 2018-12-21 中芯国际集成电路制造(上海)有限公司 晶圆键合方法以及晶圆键合结构

Family Cites Families (38)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4498121A (en) * 1983-01-13 1985-02-05 Olin Corporation Copper alloys for suppressing growth of Cu-Al intermetallic compounds
JPS63128648A (ja) * 1986-11-18 1988-06-01 Seiko Epson Corp 半導体装置
US5658828A (en) 1989-11-30 1997-08-19 Sgs-Thomson Microelectronics, Inc. Method for forming an aluminum contact through an insulating layer
JPH06236878A (ja) * 1993-02-09 1994-08-23 Kawasaki Steel Corp 金属配線
US5455195A (en) * 1994-05-06 1995-10-03 Texas Instruments Incorporated Method for obtaining metallurgical stability in integrated circuit conductive bonds
JPH0817913A (ja) 1994-06-24 1996-01-19 Sony Corp 埋め込み構造、埋め込み構造の形成方法、埋め込み構造を有する半導体装置、及び該半導体装置の製造方法
JP2725611B2 (ja) 1994-10-19 1998-03-11 株式会社デンソー 半導体装置
US20020033533A1 (en) 1994-11-14 2002-03-21 Marvin Liao Interconnect structure for use in an integrated circuit
EP0751566A3 (en) * 1995-06-30 1997-02-26 Ibm Metal thin film barrier for electrical connections
JPH09115866A (ja) * 1995-10-17 1997-05-02 Mitsubishi Electric Corp 半導体装置の製造方法
US5918149A (en) 1996-02-16 1999-06-29 Advanced Micro Devices, Inc. Deposition of a conductor in a via hole or trench
KR100215846B1 (ko) 1996-05-16 1999-08-16 구본준 반도체장치의 배선형성방법
US5783868A (en) * 1996-09-20 1998-07-21 Integrated Device Technology, Inc. Extended bond pads with a plurality of perforations
US6057237A (en) * 1997-04-29 2000-05-02 Applied Materials, Inc. Tantalum-containing barrier layers for copper
KR100470923B1 (ko) * 1997-05-16 2005-05-10 매그나칩 반도체 유한회사 반도체장치의금속배선형성방법
US6069068A (en) * 1997-05-30 2000-05-30 International Business Machines Corporation Sub-quarter-micron copper interconnections with improved electromigration resistance and reduced defect sensitivity
JP3605291B2 (ja) 1997-08-29 2004-12-22 株式会社日立製作所 半導体集積回路装置
JPH11111842A (ja) * 1997-09-30 1999-04-23 Sony Corp 多層配線構造およびその製造方法
JPH11121615A (ja) 1997-10-08 1999-04-30 Sony Corp 半導体装置及びその製造方法
KR19990040755A (ko) * 1997-11-19 1999-06-05 김영환 반도체 소자의 금속 배선층 콘택 형성 방법
US6117769A (en) * 1998-08-11 2000-09-12 Advanced Micro Devices, Inc. Pad structure for copper interconnection and its formation
US6187680B1 (en) * 1998-10-07 2001-02-13 International Business Machines Corporation Method/structure for creating aluminum wirebound pad on copper BEOL
US6150272A (en) * 1998-11-16 2000-11-21 Taiwan Semiconductor Manufacturing Company Method for making metal plug contacts and metal lines in an insulating layer by chemical/mechanical polishing that reduces polishing-induced damage
TW445616B (en) * 1998-12-04 2001-07-11 Koninkl Philips Electronics Nv An integrated circuit device
US6346745B1 (en) * 1998-12-04 2002-02-12 Advanced Micro Devices, Inc. Cu-A1 combined interconnect system
US6124203A (en) * 1998-12-07 2000-09-26 Advanced Micro Devices, Inc. Method for forming conformal barrier layers
US6359328B1 (en) * 1998-12-31 2002-03-19 Intel Corporation Methods for making interconnects and diffusion barriers in integrated circuits
TW426980B (en) * 1999-01-23 2001-03-21 Lucent Technologies Inc Wire bonding to copper
US6320263B1 (en) * 1999-02-18 2001-11-20 Advanced Micro Devices, Inc. Semiconductor metalization barrier and manufacturing method therefor
JP4237325B2 (ja) * 1999-03-11 2009-03-11 株式会社東芝 半導体素子およびその製造方法
US6133136A (en) * 1999-05-19 2000-10-17 International Business Machines Corporation Robust interconnect structure
JP2001015516A (ja) * 1999-06-30 2001-01-19 Toshiba Corp 半導体装置及びその製造方法
US6312830B1 (en) * 1999-09-02 2001-11-06 Intel Corporation Method and an apparatus for forming an under bump metallization structure
US6350667B1 (en) * 1999-11-01 2002-02-26 Taiwan Semiconductor Manufacturing Company Method of improving pad metal adhesion
US6191023B1 (en) * 1999-11-18 2001-02-20 Taiwan Semiconductor Manufacturing Company Method of improving copper pad adhesion
US6362531B1 (en) * 2000-05-04 2002-03-26 International Business Machines Corporation Recessed bond pad
US6376353B1 (en) * 2000-07-03 2002-04-23 Chartered Semiconductor Manufacturing Ltd. Aluminum and copper bimetallic bond pad scheme for copper damascene interconnects
US6560862B1 (en) * 2001-02-06 2003-05-13 Taiwan Semiconductor Manufacturing Company Modified pad for copper/low-k

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