TW513778B - Method of fabricating a barrier layer with high tensile strength - Google Patents

Abstract

A semiconductor wafer is provided, which has a low k layer positioned on the semiconductor wafer and a dual damascene structure positioned in the low k layer. The dual damascene structure includes a trench and a via hole, the via hole connecting to a conductive layer laid beneath. A barrier layer is formed at a temperature of 300 to 400 DEG C to cover the dual damascene structure and the low k layer. Thereafter, the semiconductor wafer is cooled to room temperature.

Description

513778

FIELD OF THE INVENTION The present invention relates to a metal interconnect method used in a semiconductor process, and more particularly to a method for forming a barrier layer having high tensile strength (tensUe strength) for modifying the cover. Reliability of double damascene copper interconnects. Background Description Copper double damascene (dua 1 damascene) technology combined with low dielectric constant materials (inter metal dielectric) is currently the most popular combination of metal interconnection processes, especially for high-volume, high-degree , High-speed logic integrated circuit chip manufacturing, and deep sub-micro semiconductor processes below 0.8 m. This is: Copper has a low resistance value (3 0 lower than aluminum %) And anti-electromigration resistance, and low dielectric constant materials can help reduce the RC delay (RC del ay) effect between metal wires. Therefore, copper metal dual-mosaic interconnect technology It appears to be very important in integrated circuit manufacturing, and it is bound to become the standard interconnect technology for the next generation of semiconductor manufacturing. Τ

Refer to Fig. 1 '. Fig. 1 is a partial cross-sectional audio diagram of a semiconductor wafer 10, showing a typical dual damascene structure 11. As shown in FIG. 1, the dual damascene structure 11 is formed in a dielectric layer 20 and includes a lower contact window.

513778 V. Description of the invention (2) (v i a) structure 22 and an upper trench structure 23. A first-layer wire (metal-1) 14 is formed in a dielectric layer 12 and an upper-layer copper wire 24 is filled in the upper trench structure 23. The upper-layer copper wire 24 and the first-layer wire 14 can be connected to each other through the dielectric layer 12 and the protective layer 18 between the dielectric layer 20 through a via plug 22a. In order to prevent the copper metal filled in the dual damascene structure 11 from diffusing into the adjacent dielectric layer 20, a conventional method needs to form a barrier (b a r r i e r) layer 25 on the surface of the dual damascene structure 1 1. Generally, the barrier layer 25 needs to have at least the following conditions: (1) good diffusion barrier properties; (2) good adhesion to copper metal and dielectric layers; (3) the resistance value cannot be too high (< 1000 // Ω -cm); (4) Good step coverage. Common barrier layer materials include titanium, titanium nitride (TiN), tantalum nitride (TaN), and tungsten nitride (WN). However, the conventional double damascene copper process often observes the failure of via open. The opening of the contact window is mainly due to the diffusion of copper metal into the dielectric layer 20 through the leakage of the barrier layer 25, and thus the conduction between the upper-layer copper wire 24 and the first-layer wire 14 cannot be conducted. Circuit failure. This phenomenon is particularly serious when the dielectric layer 20 uses a low dielectric constant material having a high thermal expansion coefficient, such as a Si LK τ domain porous structure dielectric layer. Taking the copper-metal double intercalation copper process with Si LKT as the dielectric layer 20 and the nitride button (TaN) as the barrier layer 25 as examples, since Si L K TM, copper metal and nitrogen

Page 5 513778 V. Description of the invention (3) The thermal expansion coefficients of tantalum (TaN) are 60 ppm / ° C, 17 ppm / t: and 3 ppm / ° C, so when the metallized semiconductor wafer 10 undergoes heat again After the process, the thermal stress generated by the Si LK τ valence layer 20 will cause the nitrided group barrier layer 25 with a lower thermal expansion coefficient to crack, thereby causing via open failure. SUMMARY OF THE INVENTION Therefore, the main object of the present invention is to provide a dual damascene process method to solve the above problems. Another object of the present invention is to provide a method for forming a barrier layer with high tensile strength for improving the reliability of a copper dual damascene interconnect process. According to a preferred embodiment of the present invention, the present invention first provides a semiconductor wafer including a Si LK dielectric constant material layer having a dual damascene structure. The dual mosaic structure includes a wire trench structure and a contact window opening, wherein the contact window opening leads to a lower layer of metal wire. A barrier layer is then formed on the surface of the dual damascene structure and the Si LK dielectric constant material layer. The barrier layer is formed by using physical vapor deposition (PVD) at a temperature of about 300 to 400 ° C. Thereafter, the semiconductor wafer was cooled to room temperature. The low dielectric constant material layer has a first thermal expansion coefficient, the barrier layer has a second thermal expansion coefficient, and the second thermal expansion coefficient is smaller than the first thermal expansion coefficient. In some

Page 6 513778

5. Description of the invention (4) In the embodiment, the first thermal expansion coefficient is greater than 50 ppm / ° C, and the second thermal expansion coefficient is less than 10 ppm / ° C. In another embodiment of the present invention, a self-massed butadiene wafer is composed of a SiLKT 牴 dielectric constant material layer having a dual damascene structure. The dual-mosaic structure includes a wire trench structure and a-interface, wherein the opening of the contact window leads to a lower metal wire. Then, the surface of the damascene structure and the SiLKT 牴 dielectric constant material layer come up to the barrier layer. The barrier layer is formed below a temperature of 10 (rc.) Then, at about 300 ° C, the semiconductor wafer is formed / lit on the barrier layer by PVWjt to cool to room temperature. I mouth layer. Will be packaged in this package. 〇 ， The embedding layer. The phase sink layer is covered with a room-temperature adhesive sheet, and the material layer is double-embedded. The gas barrier chip is yet another embodiment. The double-mosaic structure of the SlLKT medium is composed of a wire trench structure and a contact: the contact window opening leads to a lower metal wire. Xiyang Junli a ί * 1T is formed on the material layer. The chemical vapor deposit ι · ηη, ι ^ = layers are then used. The Tl: 2 is deposited at a high temperature. The semiconductor crystals are then combined to form a group on the TlN layer ( Ta)

513778 V. Description of the invention (5) Detailed description of the invention Example 1: T a N single-layer barrier layer

Please refer to FIG. 2A to FIG. 2D, FIG. 2A to FIG. 2D are too private policies :: Example-a partial cross-sectional view S of a semiconductor wafer 30. First of all: ^-Actually, the semiconductor wafer 3Q includes-the bottom layer and the F-port number A are larger than the thermal expansion system of the barrier formed on the subsequent transfer coating (training-spin the case, low dielectric constant material layer 34 is made by | γ ° The material layer 34 here can be commonly used in the industry: organic; dielectric; polystyrene: poly (arylene ethe " column ^ ΠΥδ ' Τ; αΤ: = = The dielectric constant of the material layer 34, such as imine (fu〇rinated polyimide), hsq, is generally between 2.2 to 3.5, with a low ^ 厗 degree, and 々 is thousands of angstroms (angstrom). Up to several micrometers. ”= The invention began in a low dielectric constant material layer 31. The dual damascene structure 31 includes-a wire trench structure 2, a window opening 35, wherein the contact window opening 35 leads to a The bottom layer 3 is the line 37. The lower layer metal wire 37 may be the following layer: For the convenience of describing the features of the present invention, other elements in the bottom layer 32 ^ 513778

For other interconnecting structures, do n’t be tortoise-μ ^ Α 山 山 沾 4 致 0 H, + ♦ ,, and the members are not shown in Figure 2A and the following illustration. You can use the double-bladed, double-bladed structure, 1 formation, such as pile 勰 + i-type copper metal interconnects of the same type of double inlay system, such as contact ® priority double inlay process, guideline. (Trench- first) Double inlay cutting jealousy 枉 线 Trunking priority st 〇 ^ ^ ^ ^ ^. 桎, buried etch stop (buriedetch stop) double table process or embedded inlay process. Mosquito aurietetchmask) Double

The surface is made up of ^ rv; mm 33 3 surface, the contact window opening 35 table (⑽). However, the nitrided group of people with == properties · servant 锊 π · μ, 、, 匕 are selected from the following Any one or a group of materials. Titanium (TiN), titanium tungsten alloy (Tiw al 10y), button tungsten alloy), or other similar barrier materials are also suitable for the present invention. "The barrier layer is located in an environment with a temperature of about 300 to 400 ° C, preferably 300 ° C, using physical vapor deposition (Physicai vap〇r dep〇siti〇n). , PvD) or high-density plasma PVD technology, with a thickness of about 100 to 600 angstroms, preferably " between 150 and 400 angstroms. In addition, a barrier layer & & The method can choose to use sputtering or chemical vapor deposition technology, which is well known to those skilled in the art, so it will not be described in detail.

The formation of the barrier layer 44 from $ is performed under a high temperature (300 ° C) environment. The Zn dielectric material layer 34 will thermally expand, and the dual damascene structure 31 will be extended by M q 1 ^ Α. The layer 44 is initially deposited on the thermally expanded double damascene junction. Subsequently, as shown in FIG. 2C, the semiconductor wafer 30 is cooled again.

Page 513 778

V. Description of the invention (7) At this date, the low-dielectric-constant material layer 34 returns to its original thick sound, resulting in a pre-stressed barrier layer 44 ′. The pre-deer barrier layer 44 has a greater tensile strength than the barrier layer 44 and can withstand the thermal expansion effect of the subsequent low-dielectric-constant material layer 34 undergoing a thermal process. Next, as shown in FIG. 2D, a copper seed layer 46 is formed on the surface of the prestressed barrier layer 44. The steel seed layer 46 can be formed by using p v D technology or other methods well known to those skilled in the art. Next, an electrodeless steel deposition (ECD) technique is used to fill a dual-metal embedded structure 31 with a copper metal layer 48. After depositing the copper metal layer 48, a chemical mechanical polishing (CMP) process is usually performed to remove a portion of the copper metal layer 48, leaving behind the lead trenches 33 and the contact windows 35.铜 金属 层 4 8. The copper metal layer 4 8. Since the technical features of the present invention are the processing of the barrier layer 44 and the formation of the prestressed barrier layer 4 ′, the subsequent steps will not be repeated. 9 Second embodiment: T a N / T a double-layer barrier layer 凊 Refer to FIG. 2A to FIG. 3D ′ FIG. 2A to FIG. 3D are schematic cross-sectional views of a part of a semiconductor wafer 30 of a second embodiment of the present invention . As shown in the figure, the semiconductor wafer 30 includes a bottom layer 32, a low dielectric constant material layer 34 formed on the bottom layer 32, and a dual damascene structure 31 formed in the low "constant material layer 34. Similarly, the dual mosaic structure 31 includes a two-line trench

MJ // 8

3 3 and a lower and lower metal wire system of a contact window is larger than the subsequent formation = 3 5 'where the contact window opening 3 5 reaches a 7: the low dielectric constant material layer 34' barrier layer, preferably SiLK% Make up. Expansion, number, double table, owing structure 3 1 can be formed by the Litian 夂 & inlay process, such as contact window J: the same type of copper metal interconnecting double inlay process, the first inlay, the wire groove priority inlay process. In addition, the low dielectric constant is often 2 = the process or buried in the name of the organic low dielectric constant materials, as the 邛 layer 3 4 can be commonly used in the industry (arylene ethe〇1 ^ ;; ^ ^ ^ ^ ^ amine ( (Polyimide) is a high score or a pirarre class / dagger compound. Polyimide), HSQ and so on. The fluorinated surface ^ ^ ^ surface, j 组 contact window opening 35 surface group (Tam composition. However, m 'others are selected from the following combinations of titanium nitride (τ 1 Ν), titanium tungsten composite ( τ · w.,. aw alloy), = aU〇y), button tungsten alloy i,. ~ physical vapor deposition (physica

2320 / = 1 tn, PVD) or high-density plasma PVD technology, which is about 100 to 600 angstroms, preferably 150 to 400 angstroms. between. The method of forming the barrier layer 54 can be selected to use sputtering or chemical vapor deposition technology, which is well known to those skilled in the art, and therefore will not be described in detail.

513778

V. Explanation of the invention (9) Next, as shown in FIG. 3C, at a temperature of about 30 ° C, the PVm / density plasma PVD technology is used in the barrier axe 5 4 5 5 5 5 54 spot adhesive layer 56 Qiu Tongfang 7 雔 1 opens up to form ~ M layer 56. Barrier 34, 鄱. Dt), 问 In the case of a two-layer barrier layer, the adhesive layer 56 is composed of group (Ta). f = f; two ^ ^ ^ r ^ η n ° r ^ πτ ττ / 1. The wind field is formed at the point of integration 5 6 under a single plate U ϋ ϋ C) ¼ i, so it has low dilation. And the gland sacrifice hill #a low quotation pen layer material layer 34 will thermally swell and will stretch the inlaid structure 31 to lengthen, crack (cracung) phenomenon, in the barrier layer 5 = layer T

However, in the process of forming the bonding layer 56, the tantalum (Ta) metal in the bonding layer 56 in the s C original + the bonding λ π

The original thousand W were filled in to repair these cracks. (After k, as shown in FIG. 3D, the semiconductor wafer 30 is cooled to room temperature. At this time, the low-dielectric-constant material layer 34 is restored to the original thickness, resulting in a pre-stressed double layer ( dual-layer) barrier layer 58. The pre-stressed double-layer barrier layer 5 8 has a greater tensile strength than the double-layer barrier layer 5 8 'so it can withstand subsequent low dielectric constant material layers 3 4 undergoing heat The thermal expansion effect produced by the process. Next, to complete the copper dual damascene conductor process, the following steps are also included (not shown): (丨) on the prestressed barrier layer 5 8 and 幵 > forming a copper sun-dried layer on the surface (2) Using the eiectroless copper deposition (ECD) technology in the dual damascene structure 31, fill in

A copper metal layer; (3) performing a chemical mechanical polishing (CMP) process to remove a portion of the copper metal layer. Example 3 · TaN / CVD-TiN / Ta multilayer barrier layer

Page 12 V. Description of Invention (10)-^ -----

凊 Referring to FIGS. 4A to 4D, FIG. 4A-a partial cross-section of a semiconductor wafer 30 is shown in FIG. 4D, which is a third embodiment of the present invention. The body wafer 30 includes a bottom layer 32 and two. As shown in FIG. 4A, a semiconducting substrate 32 and a low dielectric constant material layer 34 are formed on the structure 31. Similarly, the double damascene structure = the double damascene junction in the material layer 34 and—the contact window opening 35, where the contact = two has a conductive trench structure 33 and the lower metal wiring 37. The low-dielectric constant 35 reaches one of the bottom layers 32, which is a barrier layer formed later, preferably SiL4KTa. The thermal expansion coefficient is large. The double damascene structure 31 can be formed by the Jute τ rn damascene process, such as contact Copper-gold process, / rrr pavilion double inlay wheel = inlay: clever process. In addition, the low-dielectric-constant material layer 34 may be available in the industry. For example, the low-dielectric-constant material layer 34 may be a low-dielectric-constant material, for example, an arylene ether polymer (ριι = eth ^) (Polymer) or a paryUn compound, a polyamine pol ^ (ide) is a southern molecule, fluorinat polyimide, HSQ, and the like. As shown in FIG. 24B, a barrier layer 64 is formed on the surface of the lead trench μ, the contact window opening μ, and the low dielectric constant material layer 34. In this third embodiment, the barrier layer 64 is composed of nitrided (TaN) with good adhesion properties to s i LK TM. The barrier layer 64 is formed at a temperature of 100 ° C or lower, and is formed using physical vapor deposition (PVD) or high-density plasma P VD technology. The thickness of the barrier layer 64 is between 1000 and 600 angstroms. &Amp;

513778 V. Description of the invention (11) The method can choose to make the skilled person between 150 and 400 angstroms. In addition, the method of forming the barrier layer β 4 is sputtering or chemical vapor deposition. This is a conventional reading, so it will not be described again. Then, as shown in Figure 4, a chemical vapor deposition (chemicai (TiN)) layer 66 is used. While the TiN layer 66 is deposited, the semiconductor is heated to about 400 ° C. At this temperature, Low dielectric constant 'thickness will thermally expand' and extend the dual mosaic structure 31, and at the same time, the barrier layer β 4 in 雔 \ 雔 Structure · 31 will crack (cracking) phenomenon: forming column II, ° T i N The layers 66 will fill and repair these cracks. Afterwards, as shown in FIG. 4D, the semiconductor wafer 30 is cooled. At this time, the barrier layer 64 and titanium nitride (TiN ^ 66 are subjected to :. The material layer 34 reverts to the original thickness, and is pre-stressed γ ^ stressed). Then at room temperature, titanium nitride (η into a button (Ta) is formed; ^ Japanese bb upper-shaped wire system, lambda spoon & 5 layers 68. Then, to complete the copper double damascene layer D step (not shown): ⑴ formation-copper crystal / remove some copper metal layer 1 Into a chemical mechanical polishing (CMP) process, in general, titanium nitride uses argon (A r) as the (1 ^ [^) layer 6 6 at a pressure of 1 to 101111′〇1′1 * Down, It means the plasma gas by magnetron DC sputtering Shen

513778 V. Description of invention (12). Or use TDMAT or TEMAT as a precursor and perform a thermal reaction at a temperature of 300 to 4200 ° C and a pressure of 0.5 to 2.0 mTorr to obtain a titanium nitride layer with a resistivity of 3 0 u 0 h in / cm Deposition. Or use T i C 1 and N Η as precursors and perform thermal reaction at a high temperature of 6 30 to 700 ° C to obtain a step coverage of about 80% and a resistivity of 2 0 0 // 〇hm / cm of titanium nitride layer deposited. Compared with the conventional method, the method of the present invention makes use of different temperature combinations of the resistance I1? Layer deposition step to pre-stress the barrier layer, can form a barrier layer with high tensile strength, can effectively isolate the diffusion of copper and improve Reliable dual damascene interconnect process. The above description is only a preferred embodiment of the present invention, and any equivalent changes and modifications made in accordance with the scope of the present invention shall fall within the scope of the patent of the present invention.

Page 513778 Simple illustration of the diagram Simple illustration of the diagram FIG. 1 is a schematic cross-sectional view of a conventional dual-mosaic interconnect structure FIG. 2A to FIG. 2D are schematic diagrams of the first embodiment of the present invention FIG. 3A to FIG. 3D This is a schematic diagram of the second embodiment of the present invention. Figures 4A to 4D are schematic illustrations of the schematic diagrams of the third embodiment of the present invention. 10 Semiconductor wafer 11 Dual damascene structure 12 Dielectric layer 14 Conductive layer 18 Protective layer 20 Dielectric Layer 22 Contact window structure 22a Contact plug 23 Wire trench structure 24 Upper copper wire 25 Barrier layer 30 Semiconductor wafer 31 Double damascene structure 32 Bottom layer 33 Wire trench structure 34 Low dielectric constant material layer 35 Contact window opening 〇37 Lower metal wire 44 Barrier layer 44 'Pre-stressed barrier layer 46 Copper seed layer 48 Copper metal layer 54 Barrier layer 56 Adhesive layer 58 Double barrier layer 58' Pre-stressed barrier layer 64 Barrier layer 66 TiN layer 68 Adhesive layer

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Claims (1)

513778 VI. Application Patent Scope 1. A method for improving the reliability of a dual damascene process, the method includes the following steps: providing a semiconductor wafer including a spin-coating (spin- on-coating (SOC) dielectric layer, the dual damascene structure includes a wire trench structure and a contact window opening; heating the semiconductor wafer to a predetermined temperature, and simultaneously forming a barrier layer on the surface of the dual damascene structure, The predetermined temperature may cause thermal expansion of the spin-coated dielectric layer; and cooling the semiconductor wafer and the barrier layer so that the barrier layer is pre-stressed; wherein the spin-coated dielectric layer has A first thermal expansion coefficient, the barrier layer has a second thermal expansion coefficient, and the second thermal expansion coefficient is smaller than the first thermal expansion coefficient. 2. The method according to item 1 of the patent application, wherein the spin-on dielectric layer is composed of SiLKT,; t. 3. The method according to item 1 of the patent scope, wherein the predetermined temperature is between 300 and 40 (TC). 4. The method according to item 1 of the patent scope, wherein the first thermal expansion coefficient is greater than 50 ppm / ° C. Page 17 513778 6. Scope of Patent Application 5. The method of the first scope of patent application, wherein the second thermal expansion coefficient is less than 10 p p m / ° C. 6. The method of claim 1 in which the semiconductor wafer and the barrier layer are cooled to room temperature. 7. The method according to item 1 of the patent application scope, wherein the barrier layer is made of TaN. 8. The method according to item 7 of the patent application, wherein the method for forming the barrier layer uses a physical vapor deposition (PVD) technique. 9. The method of claim 1, wherein after cooling the semiconductor wafer and the barrier layer, the method further comprises the following steps: forming a copper seed layer on the barrier layer; and forming a copper seed layer on the copper crystal. A copper metal layer is deposited on the seed layer, and the copper metal layer fills the wire trench and the contact window opening; a chemical mechanical polishing (CMP) process is performed to form a double damascene copper in the wire trench A conductive wire; and forming a protective layer on the dual damascene copper conductive wire. 1 0. A method for interconnecting dual towns, which includes the following steps: providing a semiconductor wafer including a low dielectric constant material layer; Page 18 513778 VI. The scope of the patent application forms a double damascene structure in the low dielectric constant material layer, wherein the double damascene structure includes a wire trench structure and a contact window opening; at a first predetermined temperature, the Forming a barrier layer on the surface of the dual damascene structure; heating the semiconductor wafer to a second predetermined temperature, and forming an adhesive layer on the barrier layer, wherein the second predetermined temperature is higher than the first predetermined temperature, and The low dielectric constant material layer generates thermal expansion, causing cracking of the barrier layer; cooling the semiconductor wafer and the barrier layer / adhesive layer, so that the barrier layer / adhesive layer is pre-stressed ); Wherein the low dielectric constant material layer has a first thermal expansion coefficient, the barrier layer has a second thermal expansion coefficient, and the second thermal expansion coefficient is smaller than the first thermal expansion coefficient. 11. The method of claim 10, wherein the low dielectric constant material layer is made of Si LKT. 1 2. The method according to item 10 of the scope of patent application, wherein the first predetermined temperature is less than 100 ° C. 1 3. The method according to item 10 of the patent application range, wherein the second predetermined temperature is between 300 and 400 ° C. 14 4. The method of claim 10 in the patent application range, wherein the semiconductor wafer starts with Page 19 513778 6. Scope of patent application and the barrier / adhesive layer system is cooled to room temperature. 15. The method of claim 10 in the scope of patent application, wherein the barrier layer is composed of a nitrided group (T a N), and the adhesive layer is composed of a group (T a). 16. A method of dual damascene interconnects, which includes the following steps: providing a semiconductor wafer including a spin-on dielectric layer; forming a dual damascene structure in the spin-on dielectric layer, The dual damascene structure includes a wire trench structure and a contact window opening; a barrier layer is formed on the surface of the dual damascene structure at a first predetermined temperature; and the semiconductor wafer is heated to a second predetermined temperature while A titanium nitride (T i N) layer is formed on the barrier layer, wherein the second predetermined temperature is higher than the first predetermined temperature, and the spin-coated dielectric layer can cause thermal expansion, causing the barrier layer Cracking phenomenon; cooling the semiconductor wafer and the barrier layer / titanium nitride layer to a third predetermined temperature, so that the barrier layer / titanium nitride layer is pre-stressed in advance, and simultaneously An adhesive layer is formed on the titanium nitride layer; wherein the spin-on dielectric layer has a first thermal expansion coefficient, the barrier layer has a second thermal expansion coefficient, and the second thermal expansion coefficient is smaller than the first thermal expansion coefficient. Factor. 0 1 7. The method according to item 16 of the scope of patent application, wherein the spin-on dielectric layer is composed of SiLKT. Page 20 513778 VI. Application scope of patent 1 8 · If the method of the scope of patent application No. 16 is adopted, wherein the first predetermined temperature is less than 100 ° C 1 9. If the method of the scope of patent application No. 16 is applied, The second predetermined temperature is between 300 and 400 ° C, and the third predetermined temperature is room temperature. 20. The method according to item 16 of the patent application scope, wherein the barrier layer is composed of a nitrided group (T a N), and the adhesive layer is composed of a group (T a). Page 21